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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit Magnitude Comparator
High-Performance Silicon-Gate CMOS
The MC74HC85 is identical in pinout and function to the LS85. This device is similar in function to the MM74C85 and L85, but has a different pinout. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This 4-Bit Magnitude Comparator compares two 4-bit nibbles and gives a high voltage level on either the A > Bout, A = Bout, or A < Bout output, leaving the other two at a low voltage level. This device also has A > Bin, A = Bin, and A < Bin inputs, eliminating the need for external gates when cascading. * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 248 FETs or 62 Equivalent Gates
16 1
MC74HC85
N SUFFIX PLASTIC PACKAGE CASE 648-08
16 1
DT SUFFIX TSSOP PACKAGE CASE 948F-01
ORDERING INFORMATION MC74HCXXN MC74HCXXDT Plastic TSSOP
PIN ASSIGNMENT
A
LOGIC DIAGRAM
10 12 13 15 5 B0 B1 B2 B3 9 11 14 1 6 7 A > Bout A = Bout A < Bout COMPARISON OUTPUTS
t Bin
B3
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC A3 B2 A2 A1 B1 A0 B0
A0 A1 A2 DATA INPUTS A3
u Bin A u Bout
A A = Bout A
A = Bin
t Bout
GND
A > Bin CASCADING INPUTS A = Bin A < Bin
4 3 2 PIN 16 = VCC PIN 8 = GND
10/95
(c) Motorola, Inc. 1995
1
REV 6
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* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
RECOMMENDED OPERATING CONDITIONS
MAXIMUM RATINGS*
MC74HC85
Symbol
Vin, Vout
Symbol
Symbol
VCC
Vout
Tstg
ICC
Iout
VCC
Vin
PD
TL
VOH
tr, tf
Iin
VOL
ICC
TA
VIH
VIL
Iin
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or TSSOP)
Storage Temperature
Power Dissipation in Still Air
DC Supply Current, VCC and GND Pins
DC Output Current, per Pin
DC Input Current, per Pin
DC Output Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Input Rise and Fall Time (Figure 1)
Operating Temperature, All Package Types
DC Input Voltage, Output Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Maximum Quiescent Supply Current (per Package)
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
Parameter
Parameter
Plastic DIP TSSOP Package
Vin = VIH or VIL |Iout| 20 A
Vin = VIH or VIL |Iout| 20 A
Vin = VCC or GND Iout = 0 A
Vin = VCC or GND
Vin = VIH or VIL |Iout| |Iout|
Vin = VIH or VIL |Iout| |Iout|
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v
v
v
v
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Test Conditions
- 0.5 to VCC + 0.5
- 1.5 to VCC + 1.5
- 65 to + 150
- 0.5 to + 7.0
2 - 55 Min 2.0 Value
v 4.0 mA v 5.2 mA
v 4.0 mA v 5.2 mA
0 0 0
0
50
25
20
260
750 450
+ 125
1000 500 400
VCC
Max
6.0
VCC V
6.0
6.0
4.5 6.0
2.0 4.5 6.0
4.5 6.0
2.0 4.5 6.0
2.0 4.5 6.0
2.0 4.5 6.0
Unit
Unit
mW
mA
mA
mA
_C
_C
_C
ns
V
V
V
V
V
- 55 to 25_C
0.1
1.5 3.15 4.2
0.26 0.26
3.98 5.48
0.1 0.1 0.1
1.9 4.4 5.9
0.3 0.9 1.2
8
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Guaranteed Limit
v 85_C v 125_C
High-Speed CMOS Logic Data DL129 -- Rev 6 1.0 1.5 3.15 4.2 0.33 0.33 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2 80
v
1.0 1.5 3.15 4.2 0.40 0.40 3.70 5.20 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2
160
v
Unit
A A V V V V
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I
NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129 -- Rev 6 OUTPUTS OUTPUTS INPUTS Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL CPD Cin tr tPLH 10% tPHL Power Dissipation Capacitance (Per Package)* Maximum Input Capacitance Maximum Output Transition Time, Any Output (Figures 1 and 2) tTHL 90% 50%
* Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Maximum Propagation Delay, Input A = B to Output A = B (Figures 1 and 2)
Maximum Propagation Delay, Inputs A > B or A = B to Output A B (Figures 1 and 2)
Maximum Propagation Delay, Inputs A or B to Output A = B (Figures 1 and 2)
Maximum Propagation Delay, Inputs A or B to Outputs A> B or A < B (Figures 1 and 2)
Figure 1. Switching Waveforms
90% 50% 10%
50%
tPLH
tPHL
Parameter
tf
tTLH
GND
VCC
3 VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- - 55 to 25_C Typical @ 25C, VCC = 5.0 V 145 29 25 175 35 30 175 35 30 200 40 34 230 46 39 10 75 15 13 DEVICE UNDER TEST Guaranteed Limit 180 36 31 220 44 37 220 44 37 250 50 43 290 58 49 10 95 19 16 50 OUTPUT 220 44 38 265 53 45 265 53 45 300 60 51 345 69 59 110 22 19 10
* Includes all probe and jig capacitance
Figure 2. Test Circuit
v 85_C v 125_C
TEST POINT
MC74HC85
MOTOROLA CL* Unit pF pF ns ns ns ns ns ns
MC74HC85
PIN DESCRIPTIONS
INPUTS A0, A1, A2, A3 (Pins 10, 12, 13, 15) Data Nibble A Inputs. The data nibble present at these inputs is compared to Data Nibble B. A3 is the most significant bit and A0 is the least significant bit. B0, B1, B2, B3 (Pins 9, 11, 14, 1) Data Nibble B Inputs. The data nibble present at these inputs is compared to Data Nibble A. B3 is the most significant bit and B0 is the least significant bit. CONTROLS A > B in , A = B in , A B in and A B in inputs should be tied to ground and the A = Bin input tied to V CC. Between cascaded comparators, the A B out OUTPUTS A > Bout (Pin 5) A-Greater-Than-B Output. This output is at a high voltage level when Nibble A is greater than Nibble B, regardless of the data present at the cascading inputs. This output is also high when Nibble A equals Nibble B and the A > B in input is high (A Bin have no effect when the comparator is in this condition and A = B in is at a high voltage level. A < Bout (Pin 7) A-Less-Than-B Output. This output is at a high voltage level when Nibble A is less than Nibble B, regardless of data present at the cascading inputs. This output is also high when Nibble A equals Nibble B and the A B in and A = B in are at a low voltage level). outputs should be tied to A B in, respectively, of the succeeding stage.
FUNCTION TABLE
Data Inputs A3, B3 A3 > B3 A3 < B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 X = Don't Care A2, B2 X X A2 > B2 A2 < B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A1, B1 X X X X A1 > B1 A1 < B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A0, B0 X X X X X X A0 > B0 A0 < B0 A0 = B0 A0 = B0 A0 = B0 A0 = B0 A0 = B0 Cascading Inputs A > Bin X X X X X X X X L L H H X A = Bin X X X X X X X X L L L L H A < Bin X X X X X X X X L H L H X A > Bout H L H L H L H L H L H L L Output A = Bout L L L L L L L L L L L L H A < Bout L H L H L H L H H H L L L
MOTOROLA
4
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC85
EXPANDED LOGIC PROGRAM
B3 A3
1 15
5
A > Bout
B2 14 A2 13
B1 11 A1 12 7 A < Bout
B0
9
A0
A < Bin 2
6 A = Bin 3
A = Bout
A > Bin
4
High-Speed CMOS Logic Data DL129 -- Rev 6
5
MOTOROLA
MC74HC85
TYPICAL APPLICATION CASCADING COMPARATORS
GND VCC GND
A > Bin A = Bin A < Bin
A0 A1 A2 LEAST- SIGNIFICANT 4-BIT NIBBLES A3 B0 B1 B2 B3 A > Bout A = Bout A < Bout A > Bin A = Bin A < Bin HC85
A4 A5 A6 A7 B4 B5 B6 B7 A8 A9 A10 MOST- SIGNIFICANT 4-BIT NIBBLES A11 B8 B9 B10 B11 A > Bout A = Bout A < Bout OUTPUTS HC85 A > Bout A = Bout A < Bout A > Bin A = Bin A < Bin HC85
MOTOROLA
6
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC85
OUTLINE DIMENSIONS
N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R
9
-A -
16
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
2X
L/2
16
9
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
High-Speed CMOS Logic Data DL129 -- Rev 6
7
EEE CCC EEE CCC EEE CCC EEE CCC
K K1 M
SECTION N-N
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MOTOROLA
MC74HC85
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MOTOROLA
CODELINE
8
*MC74HC85/D*
MC74HC85/D High-Speed CMOS Logic Data DL129 -- Rev 6

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