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ISL6413
Data Sheet October 2003 FN9129
PRELIMINARY
Triple Output Regulator with Single Synchronous Buck and Dual LDO
The ISL6413 is a highly integrated triple output regulator which provides a single chip solution for wireless chipset power management. The device integrates high efficiency synchronous buck regulator with two ultra low noise LDO regulators. The IC accepts an input voltage range of 3.0V to 3.6V and provides three regulated output voltages: 1.8V (PWM), 2.84V (LDO1), and another ultra-clean 2.84V (LDO2). The Synchronous current mode PWM regulator with integrated N- and P-channel power MOSFET provides preset 1.8V for BBP/MAC core supply. Synchronous rectification with internal MOSFETs is used to achieve higher efficiency and reduced number of external components. Operating frequency is typically 750kHz allowing the use of smaller inductor and capacitor values. The device can be synchronized to an external clock signal in the range of 500kHz to 1MHz. The PG_PWM output indicates loss of regulation on PWM output. The ISL6413 also has two LDO regulators which use an internal PMOS transistor as the pass device. LDO2 features ultra low noise that does not typically exceed 30V RMS to aid VCO stability. The EN_LDO pin controls LDO1 and LDO2 outputs. The ISL6413 also integrates a RESET function, which eliminates the need for additional RESET IC required in WLAN applications. The IC asserts a RESET signal whenever the VIN supply voltage drops below a preset threshold, keeping it asserted for at least 25ms after VIN has risen above the reset threshold. The PG_LDO output indicates loss of regulation on either of the two LDO outputs. Other features include over current protection for all three outputs and thermal shutdown. High integration and the thin Quad Flat No-lead (QFN) package makes ISL6413 an ideal choice to power many of today's small form factor industry standard wireless cards such as PCMCIA, mini-PCI and Cardbus-32.
Features
* Fully Integrated Synchronous Buck Regulator + Dual LDO * High Output Current (For QFN package) - PWM, 1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400mA - LDO1, 2.84V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA - LDO2, 2.84V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA * Ultra-Compact DC-DC Converter Design * Stable with Small Ceramic Output Capacitors * High conversion efficiency * Low Shutdown supply current * Ultra-Low Dropout Voltage for LDOs - LDO1, 2.84V. . . . . . . . . . . . . . . 125mV (typ.) at 300mA - LDO2, 2.84V. . . . . . . . . . . . . . . 100mV (typ.) at 200mA * Ultra-Low Output Voltage Noise - <30VRMS (typ.) for LDO2 (VCO Supply) * PG_LDO, PG_PWM and PG_PWM outputs * Extensive circuit protection and monitoring features - Over voltage protection - Over current protection - Shutdown - Thermal Shutdown * Integrated RESET output for microprocessor reset * Proven Reference Design for Total WLAN System Solution * QFN Package - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - Near Chip-Scale Package Footprint Improves PCB Efficiency and Is Thinner in Profile
Applications
* WLAN Cards - PCMCIA, Cardbus32, MiniPCI Cards - Compact Flash Cards * Liberty Chipset * Hand-Held Instruments
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. DWG. # ISL6413IR -40 to 85 24 Ld QFN L24.4x4B
Related Literature
* TB363 - Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) * TB389 - PCB Land Pattern Design and Surface Mount Guidelines for QFN Packages
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6413 Pinout
ISL6413 (QFN) TOP VIEW
SGND PGND 20 PVCC GND 19 18 VOUT 17 CC2 16 VOUT2 15 GND_LDO 14 VOUT1 13 CC1 7 RESET 8 CT 9 VIN_LDO 10 VIN_LDO 11 RESET 12 EN_LDO L1 10H 0.1F SGND PGND PVCC GND VIN LX 1.8V C7 10F 19 18 17 16 ISL6413 15 14 13 7 RESET CT 8 VIN_LDO 9 10 VIN_LDO 11 RESET 12 EN_LDO VOUT CC2 VOUT2 GND_LDO VOUT1 CC1 C2 C3 33nF 10F C4 10F 2.84V C6 33nF 2.84V
VIN
24 PG_PWM PG_PWM SYNC NC EN_PWM PG_LDO 1 2 3 4 5 6
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Typical Application Schematic
3.3V C10 10F C8 C9 1.0F
R1
10K PG_PWM PG_PWM SYNC NC 1 2 3 4 5 6
24
23
22
21
LX 21
20
3.3V
EN R3 10K PG_LDO
C1 10nF
3.3V C5 4.7F
NOTE: All capacitors are ceramic.
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ISL6413 Functional Block Diagram
Gm CT RESET RESET RESET BAND GAP REF 1.2V WINDOW COMP. VIN_LDO VIN_LDO + LDO1 OUT1
PG_LDO
POR
POR
VIN_LDO CONTROL LOGIC EN_LDO
EN Gm
CC1 CC2
GND_LDO THERMAL SHUTDOWN 150oC
+ LDO2 WINDOW COMP. OUT2
VIN CURRENT SENSE SOFT START SLOPE COMPENSATION EN EA GM PWM OVERCURRENT, OVERVOLTAGE LOGIC
PVCC
SGND
GATE DRIVE
LX
VOUT
COMPENSATION PGND
750kHz OSCILLATOR ANTI-RINGING POWER GOOD PWM VOUT VIN
UVLO
ZERO CURRENT DETECT
GND
PWM REFERENCE 0.45V VOUT SYNC EN PG_PWM PG_PWM
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ISL6413 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L24.4x4B
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VGGD-2 ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.30 2.19 2.19 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.23 4.00 BSC 3.75 BSC 2.34 4.00 BSC 3.75 BSC 2.34 0.50 BSC 0.40 24 6 6 0.60 12 0.50 0.15 2.49 2.49 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 0 10/03 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
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