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 HFA3763
Data Sheet June 1999 File Number
4237.4
400MHz Quadrature Modulator and AGC
The HFA3763 is a highly integrated baseband converter for quadrature modulation applications. The HFA3763 400MHz quadrature modulator and AGC is one of the seven chips in the PRISM(R) full duplex chip set (see Typical Application Diagram). It features all the necessary blocks for baseband modulation of I and Q signals. An output AGC and Baseband shaping filters are integrated in the design. Four filter bandwidths are programmable via a two bit digital control interface. In addition, these filters are continuously tunable over a 20% frequency range via one external resistor. The modulator channel receives digital or analog I and Q data for processing. To achieve broadband operation, the Local Oscillator frequency input is required to be twice the desired frequency of modulation. A selectable buffered divide by 2 LO output and a stable reference voltage are provided for convenience of the user.
TM
Features
* Integrates all IF Transmit Functions * Broad Frequency Range . . . . . . . . . . . 10MHz to 400MHz * I/Q Amplitude and Phase Balance . . . . . . . . . . . 0.2dB, 2o * 5th Order Programmable Low Pass Filter. . . . . . . . . . . . . . . . . . . 2.2MHz - 17.6MHz * 400MHz Output AGC Amplifier/Attenuator . . . . . . . .45dB * Selectable Digital or Analog TX Baseband Inputs * Low LO Drive Level . . . . . . . . . . . . . . . . . . . . . . . -15dBm * Fast Transmit-on Switching . . . . . . . . . . . . . . . . . . . . . 1s * Power Management/Standby Mode * Single Supply 2.7V to 5.5V Operation
Applications
* Wireless Local Loop Systems * Wireless Local Area Networks * PCMCIA Wireless Duplex Transceivers
Ordering Information
PART NUMBER HFA3763IN TEMP. RANGE (oC) -40 to 85 PACKAGE 80 Ld TQFP PKG. NO. Q80.14x14
* ISM Systems * TDMA Packet Protocol Radios * PCS/Wireless PBX
Simplified Block Diagram
LPF_TUNE_1 LPF_TUNE_0 LPF_SEL0 LPF_SEL1 2V REF 0o/90o MOD_LO_IN
2V REF
MOD_LO_OUT LO_GND
/2
LPF_TXI_IN IF_OUT
I
LPF_TXQ_IN Q IF_AGC_IN MOD_TX_IF_OUT MOD_TX_Q AGC_CTRL LPF_TX_Q TX D OR A MOD_TX_I LPF_TX_I
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 PRISM(R) is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.
HFA3763 Pinout
80 LEAD TQFP TOP VIEW
GND GND GND GND GND GND GND GND GND GND GND GND GND AGC_VCC GND IF_OUT GND AGC_PE GND AGC_VCC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 GND GND GND GND GND GND GND GND LPF_VCC 2V REF LPF_BYP LPF_TXI_IN LPF_TXQ_IN NC NC LPF_SEL1 LPF_SEL0 LPF_TUNE1 LPF_TUNE0 TX D or A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND LPF_TX_PE LPF_TXQLPF_TXQ+ LPF_TXILPF_TXI+ NC NC NC NC GND GND NC NC NC NC MOD_TXI+ MOD_TXIMOD_TXQ+ MOD_TXQ60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 GND AGC_CTRL GND AGC_VCC GND IF_AGC_IN GND GND GND GND LO_GND MOD_BYP MOD_BYP MOD_VCC MOD_LO_OUT MOD_VCC MOD_LO_IN GND MOD_TX_IF_OUT MOD_TX_PE
Typical Application Diagram
PRISM FULL DUPLEX CHIP SET
HFA3424/21 (File #4131) D U P L E X E R LNA BPF HFA3661 (File #4240) LNA RF/IF CONVERTER RF LO1 HFA3524 (File #4062) SYNTHESIZER IF LO1 BASEBAND HFA3524 (File #4062) HFA3925 (File #4132) PA BPF SYNTHESIZER RF LO2 AGC IF/RF CONVERTER HFA3663 (File #4241) HFA3664 (File #4242) AGC QMODEM LPF OPTIONAL WHEN IN ANALOG MODE PRISM FULL DUPLEX RADIO CHIP SET, FILE #4238 IF LO2 HFA3763 (File #4237) LPF D/A HFA3761 (File #4236) FILTER IF AGC QMODEM LPF LPF A/D
4-2
HFA3763 Block Diagram
LPF_TXQ_IN
LPF_TXI_IN
TX D or A
LPF_SEL1 LPF_SEL0 LPF_TUNE0 LPF_TUNE1 1.25V Q I
LPF_TX_PE
LPF_TX_Q LPF_TX_Q + LPF_TX_I LPF_TX_I +
2V REF
0o
/ 90o
MOD TX I + MOD TX I MOD TX Q + MOD TX Q -
MOD_TX_PE
/2
VCC MOD_TX_IF_OUT 250 IF_AGC_IN
AGC_CTRL 10K
LO_GND
VCC L1
C1 C2 50 NETWORK
OUTPUT MATCH COMPONENTS TABLE FREQ. L1 C1 12pF 5.0pF L2 82nH 33nH C2 15pF 6.0pF
L2 (2XLO) MOD_LO_IN 50 MOD_LO_OUT
105MHz 270nH 280MHz 82nH
IF_OUT
NOTE: VCC, GND and Bypass capacitors not shown.
4-3
HFA3763 Pin Descriptions
PIN 9 10 11 12 13 14 15 16 17 SYMBOL LPF_VCC 2V REF LPF_BYP LPF_TXI_In LPF_TXQ_In NC NC LPF_Sel1 LPF_Sel0 DESCRIPTION Supply pin for the Low pass filter. Use high quality decoupling capacitors right at the pin. Stable 2V reference voltage output for external applications. Loading must be higher than 10k. A bypass capacitor of at least 0.1F is required. Internal reference bypass pin. This is the common voltage (VCM) used for the LPF digital thresholds. Requires 0.1F decoupling capacitor. Low pass filter in phase (I) channel transmit input. Conventional or attenuated direct coupling is required for digital inputs. AC couple for analog input. Low pass filter quadrature (Q) channel transmit input. Conventional or attenuated direct coupling is required for digital inputs. AC couple for analog input. Connected internally for test purpose. Leave this pin floating. Connected internally for test purpose. Leave this pin floating. Digital control input pins. Selects four programmed cut off frequencies for the transmit channel. Tuning speed from one cutoff to another is less than 1s. SEL1 LO LO 18 19 20 LPF_Tune1 LPF_Tune0 TX D or A SEL0 LO HI CUTOFF FREQUENCY 2.2MHz 4.4MHz SEL1 HI HI SEL0 LO HI CUTOFF FREQUENCY 8.8MHz 17.6MHz
These two pins are used to fine tune the Low pass filter cutoff frequency. A resistor connected between the two pins (RTUNE) will fine tune the transmit filters. Refer to the tuning equation in the LPF AC specifications. Selects the configuration of the Transmit baseband input for either Digital or Analog (500mVP-P max). Tie to a High for Analog and Ground for Digital inputs. Requires decoupling capacitor for analog and a simple direct coupled attenuator for digital inputs. Digital input control pin to enable the LPF transmit mode of operation. Enable logic level is High. Negative output of the transmit Low pass filter, quadrature channel. AC coupling is required. Normally connects to the inverting input of the quadrature Modulator (Mod_TXQ-), pin 40. Positive output of the transmit Low pass filter, quadrature channel. AC coupling is required. Normally connects to the non inverting input of the quadrature Modulator (Mod_TXQ+), pin 39. Negative output of the transmit Low pass filter, in phase channel. AC coupling is required. Normally connects to the inverting input of the in phase Modulator (Mod_TXI-), pin 38. Positive output of the transmit Low pass filter, in phase channel. AC coupling is required. Normally connects to the non inverting input of the in phase Modulator (Mod_TXI+), pin 37. Connected internally for test purpose. Leave this pin floating. Connected internally for test purpose. Leave this pin floating. Connected internally for test purpose. Leave this pin floating. Connected internally for test purpose. Leave this pin floating. Connected internally for test purpose. Leave this pin floating. Connected internally for test purpose. Leave this pin floating. Connected internally for test purpose. Leave this pin floating. Connected internally for test purpose. Leave this pin floating. In phase modulator non inverting input. AC coupling is required. This input is normally coupled to the Low pass filter positive output (LPF_TXI+), pin 26. In phase modulator inverting input. AC coupling is required. This input is normally coupled to the Low pass filter negative output (LPF_TXI-), pin 25. Quadrature modulator non inverting input. AC coupling is required. This input is normally coupled to the Low pass filter positive output (LPF_TXQ+), pin 24. Quadrature modulator inverting input. AC coupling is required. This input is normally coupled to the Low pass filter negative output (LPF_TXQ-), pin 23.
22 23 24 25 26 27 28 29 30 33 34 35 36 37 38 39 40
LPF_TX_PE LPF_TXQLPF_TXQ+ LPF_TXILPF_TXI+ NC NC NC NC NC NC NC NC Mod_TXI+ Mod_TXIMod_TXQ+ Mod_TXQ-
4-4
HFA3763 Pin Descriptions
PIN 41 42 44 SYMBOL Mod_TX_PE Mod_TX_IF_Out Mod_LO_In (2XLO) (Continued) DESCRIPTION Digital input control to enable the Modulator section. Enable logic level is High for transmit. Modulator open collector output, single ended. Termination resistor to VCC with a typical value of 250. Single ended local oscillator current input. Frequency of input signal must be twice the required modulator carrier LO frequency. Input current is optimum at 200ARMS. Input matching networks and filters can be designed for a wide range of power and impedances at this port. Typical input impedance is 130.This pin requires AC coupling. NOTE: High second harmonic content input waveforms may degrade I/Q phase accuracy. Modulator supply pin. Use high quality decoupling capacitors right at the pin. Divide by 2 buffered output reference from "Mod_LO_in" input. Used for external applications where the modulating and demodulating carrier reference frequency is required. 50 single end driving capability. AC coupling is required. This output can be disabled by shorting to VCC or floating pin 50. Modulator supply pin. Use high quality decoupling capacitors right at the pin. This pin must be connected to pin 49 and decoupled to gnd. (Note 1) This pin must be connected to pin 48. (Note 1) When grounded, this pin enables the LO buffer (Mod_LO_Out). When open (NC) it disables the LO buffer. AC coupled input to the AGC amplifier. AGC supply pin supply pin. Use high quality decoupling capacitors right at the pin. AGC control DC control voltage input requires external resistor to set scale factor. 10K for optimum temp. co. May require decoupling filtering capacitor. AGC supply pin supply pin. Use high quality decoupling capacitors right at the pin. Digital input control for the AGC amplifier. Enable logic level is High. AGC amplifier output. Output impedance of 250. Need to be connected to VCC by an inductor with reactance well above 250. AGC supply pin supply pin. Use high quality decoupling capacitors right at the pin. All remaining pins not listed above must be connected to a solid ground plane.
45 46
Mod_VCC Mod_LO_Out
47 48 49 50 55 57 59 61 63 65 67 See Pinout NOTE:
Mod_VCC MOD_BYP MOD_BYP LO_GND IF_AGC_IN AGC_VCC AGC_CTRL AGC_VCC AGC_PE AGC_IF_OUT AGC_VCC GND
1. If pin 50 is grounded, otherwise float.
4-5
HFA3763
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Package Power Dissipation at 70oC Plastic TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.1W Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . . -65 TA 150 Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (TQFP - Lead Tips Only)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Voltage on Any Other Pin. . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
Operating Conditions
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . +2.7V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . -40oC TA 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Cascaded DC Electrical Specifications
VCC = 4.5V to 5.5V, Unless Otherwise Specified (NOTE 2) TEST LEVEL A A A A A A A A A A A A A A C A B B C TEMP (oC) Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25 Full Full 25 25
PARAMETER Total Supply Current, TX Mode at 5.5V Shutdown Current at 5.5V All Digital Inputs VIH (TTL Threshold for All VCC) All Digital Inputs VIL (TTL Threshold for All VCC) High Level Input Current at 5.5V VCC for pin 16 with VIN = 2.4V High Level Input Current at 5.5V VCC for pin 16 with VIN = 4.0V Low Level Input Current at 5.5V VCC for pin 16 with VIN = 0.8V High Level Input Current at 5.5V VCC for pins 17, 20, and 22 with VIN = 2.4V High Level Input Current at 5.5V VCC for pins 17, 20, and 22 with VIN = 4.0V Low Level Input Current at 5.5V VCC for pins 17, 20, and 22 with VIN = 0.8V High Level Input Current at 5.5V VCC for pins 41 and 63 with VIN = 2.4V High Level Input Current at 5.5V VCC for pin 41 with VIN = 4.0V High Level Input Current at 5.5V VCC for pin 63 with VIN = 4.0V Low Level Input Current at 5.5V VCC for pins 41 and 63 with VIN = 0.8V Power Down/Up Switching Speed Reference Voltage Reference Voltage Variation Over Temperature Reference Voltage Variation Over Supply Voltage Reference Voltage Minimum Load Resistance NOTE: 2. A = Production Tested, B = Based on Characterization, C = By Design
MIN 2.0 -0.2 -200 -150 -300 0 0 0 -20 0 -20 -20 1.85 10
TYP 80 0.8 -65 -30 -95 50 80 15 1 110 1.5 .1 10 2.0 800 1.6 -
MAX 106 1.0 VCC 0.8 0 0 0 200 300 150 20 300 20 20 2.15 -
UNITS mA mA V V A A A A A A A A A A s V V/oC mV/V k
Cascaded AC Electrical Specifications, Modulator Performance
PARAMETER IF Modulator Output Power (Note 6) IF Modulator I/Q Amplitude Balance (Note 4) IF Modulator I/Q Phase Balance (Note 4) (NOTE 3) TEST LEVEL A B B
VCC = 4.5V to 5.5V TEMP (oC) 25 Full Full MIN -4 -1.0 -4.0 TYP 1 0 0 MAX 6 +1.0 +4.0 UNITS dBm dB Degrees
4-6
HFA3763
Cascaded AC Electrical Specifications, Modulator Performance
PARAMETER IF Modulator Side Band Suppression at 105MHz (Note 5) (NOTE 3) TEST LEVEL A A IF Modulator Side Band Suppression at 400MHz IF Mod Carrier Suppression (LO Buffer Enabled) (Note 5) IF Mod Carrier Suppression (LO Buffer Disabled) (Note 5) IF Modulator I/Q 3dB Cutoff SEL0/1 = 2.2MHz IF Modulator I/Q 3dB Cutoff SEL0/1 = 4.4MHz IF Modulator I/Q 3dB Cutoff SEL0/1 = 8.8MHz IF Modulator I/Q 3dB Cutoff SEL0/1 = 17.6MHz NOTES: 3. A = Production Tested, B = Based on Characterization, C = By Design 4. Data is characterized by DC levels applied to MOD TXI and Q pins for 4 quadrants with LO output as reference or indirectly by the SSB characteristics. 5. Analog mode with an input frequency of 1MHz and an input amplitude of 400mVP-P and a 2.2MHz lowpass filter cutoff with VAGC = 1.25V. 6. Data is characterized with VAGC = 1V with an input of 400mVP-P at LPF_TXI_IN and LPF_TXQ_IN. C C A B B B B VCC = 4.5V to 5.5V (Continued) TEMP (oC) Full 25 25 25 25 25 25 25 25 MIN 25 33 28 28 28 1.98 3.96 7.92 15.84 TYP 41 41 30 38 2.2 4.4 8.8 17.6 MAX 2.42 4.84 9.68 19.36 UNITS dBc dBc dBc dBc dBc MHz MHz MHz MHz
DC/AC Electrical Specifications AGC/Attenuator, Individual Performance
PARAMETER (NOTE 7) TEST LEVEL
VCC = 4.5V to 5.5V Unless Otherwise Specified MIN TYP MAX UNITS
TEMP (oC)
DC ELECTRICAL SPECIFICATIONS AGC ATTENUATOR INDIVIDUAL PERFORMANCE AGC Scale Factor at 100MHz at 3dB AGC Linearity: Max-to-Min Scale Factor at 0dB to 45dB AGC with External 10k AGC Control Input for 45dB Max Attenuation with External 10k AGC Control Input for -3 dB from Minimum Attenuation (Gain Approx. = 6dB) with External 10k AGC Input Bias Current with External 10k at -45 dB A A A A A 25 25 25 25 Full 36 0.9:1 1.7 1.0 45 2:1 2.0 1.2 54 3:1 2.5 1.4 120 dB/V V V A
AC ELECTRICAL SPECIFICATIONS AGC ATTENUATOR INDIVIDUAL PERFORMANCE Frequency Range Power Gain at min AGC at 100MHz VAGC = 1.0V Power Gain Temperature Coefficient VAGC = 1.0V Output P1dB at Minimum AGC, 100MHz VAGC = 1.0V Output IP3 at Minimum AGC, 100MHz VAGC = 1.0V AGC/Attenuator Range AGC Settling Time to 1dB, 0dB to -40dB Output Impedance Input Impedance Gain Flatness, 20MHz Bandwidth Phase Shift vs AGC at 100MHz Power Down/Up Switching Speed (Note 3) NOTE: 7. A = Production Tested, B = Based on Characterization, C = By Design B C B B B A C C C C C C 25 25 25 25 25 25 25 25 25 25 25 25 10 42 9.0 +0.013 8.0 17.5 45 250 250 0.02 -0.045 400 10 10 MHz dB dB/deg dBm dBm dB s dB deg/dB s
4-7
HFA3763
AC Electrical Specifications, I/Q Up Converter and LO Individual Performance
VCC = 4.5V to 5.5V Unless Otherwise Specified PARAMETER 2XLO Input Frequency Range (2 X Input Range) 2XLO Input Current Range 2XLO Input Impedance Buffered LO Output Voltage, Single Ended Buffered LO Output Impedance Quadrature IF Modulator Output Frequency Range IF Modulator I/Q Input Frequency Range IF Modulator Differential I/Q Max Input Voltage IF Modulator Differential I/Q Input Impedance IF Modulator Differential Input Capacitance IF Modulator I/Q Amplitude Balance IF Modulator I/Q Phase Balance at 105MHz IF Modulator I/Q Phase Balance at 400MHz IF Modulator Carrier Suppression (LO Buffer Enabled) IF Modulator Carrier Suppression (LO Buffer Disabled) IF Modulator SSB Sideband Suppression at 105MHz (NOTE 8) TEST LEVEL B C C A C B C C C C B B C C A A A IF Modulator SSB Sideband Suppression at 400MHz IF Output Level Compression Point IF Modulator Intermodulation Suppression NOTE: 8. A = Production Tested, B = Based on Characterization, C = By Design C C B TEMP (oC) 25 25 25 25 25 25 25 25 25 25 Full Full 25 25 25 Full 25 25 25 25 MIN 20 50 80 10 -1.0 -4 -4 28 28 25 33 28 26 TYP 200 130 100 50 2.25 4 0.5 30 38 41 41 1.0 MAX 800 300 400 30 1.0 4 4 UNITS MHz ARMS mVP-P MHz MHz VP-P k pF dB Degrees Degrees dBc dBc dBc dBc dBc VP-P dBc
AC Electrical Specifications, TX Buffer Individual Performance
PARAMETER TX LPF Buffer Analog Input Range TX LPF Buffer Analog/Digital Input Impedance NOTE: 9. A = Production Tested, B = Based on Characterization, C = By Design
VCC = 4.5V to 5.5V Unless Otherwise Specified TEMP (oC) 25 25 MIN 10 TYP 500 12.5 MAX UNITS mVP-P k
(NOTE 9) TEST LEVEL A C
AC Electrical Specifications, RX/TX 5TH Order LPF Individual Performance
VCC = 4.5V to 5.5V Unless Otherwise Specified PARAMETER TX LPF 3dB Bandwidth, Sel0 = 0, Sel1 = 0 TX LPF 3dB Bandwidth, Sel0 = 1, Sel1 = 0 TX LPF 3dB Bandwidth, Sel0 = 0, Sel1 = 1 TX LPF 3dB Bandwidth, Sel0 = 1, Sel1 = 1 TX LPF Sel0, Sel1 Tuning Speed (NOTE 10) TEST LEVEL B B B B B TEMP (oC) 25 25 25 25 25 MIN 1.98 3.96 7.92 15.84 TYP 2.20 4.40 8.80 17.60 MAX 2.42 4.84 9.68 19.36 1 UNITS MHz MHz MHz MHz s
4-8
HFA3763
AC Electrical Specifications, RX/TX 5TH Order LPF Individual Performance
VCC = 4.5V to 5.5V Unless Otherwise Specified (Continued) PARAMETER TX LPF 3dB Bandwidth Tuning LPF Tune Nominal Resistance TX/RX LPF Total Harmonic Distortion LPF Output Impedance, Single Ended NOTE: 10. A = Production Tested, B = Based on Characterization, C = By Design (NOTE 10) TEST LEVEL B B B C TEMP (oC) 25 25 25 25 MIN -20 TYP 787 1 50 MAX +20 UNITS % %
TABLE 1. LOW PASS FILTER PROGRAMING AND TUNING INFORMATION MODE BW0 BW1 BW2 BW3 LPF SEL1 0 0 1 1 LPF SEL0 0 1 0 1 f3dB (NOMINAL RTUNE) 2.2MHz 4.4MHz 8.8MHz 17.6MHz
f 3dBNOMINAL 787 f TUNED 3dB = --------------------------------------------------R TUNE
PERCENT OF NOMINAL FREQUENCY
+20%
-20% -30 -25 -20 -15 -10 -5 0 +5 +10 +15 +20 +25 +30
[(787 - RTUNE)/RTUNE] * 100%
FREQUENCY 20% Low Nominal 20% High
RTUNE 984 787 656
FIGURE 1. TYPICAL f3dB vs RTUNE
4-9
HFA3763 Thin Plastic Quad Flatpack Packages (LQFP)
D D1 -D-
Q80.14x14 (JEDEC MS-026BEC ISSUE C)
80 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE SYMBOL A A1 A2 INCHES MIN 0.002 0.054 0.009 0.009 0.626 0.547 0.626 0.547 0.018 80 0.026 BSC MAX 0.062 0.005 0.057 0.014 0.012 0.634 0.555 0.634 0.555 0.029 MILLIMETERS MIN 0.05 1.35 0.22 0.22 15.90 13.90 15.90 13.90 0.45 80 0.65 BSC MAX 1.60 0.15 1.45 0.38 0.33 16.10 14.10 16.10 14.10 0.75 NOTES 6 3 4, 5 3 4, 5 7 Rev. 2 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- .
0.13 A-B S 0.005 M C DS b b1 0.09/0.16 0.004/0.006 BASE METAL WITH PLATING
-AE E1
-B-
b b1 D D1 E
e
PIN 1 SEATING A PLANE 0.08 0.003 -C-
E1 L N e
-H-
4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 7. "N" is the number of terminal positions.
11o-13o 0.020 0.008 MIN 0o MIN GAGE PLANE L 0o-7o 0.25 0.010 11o-13o A2 A1
0.09/0.20 0.004/0.008
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
4-10


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