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M491B
SINGLE-CHIP VOLTAGE SYNTHESIS TUNING SYSTEM WITH 1 ANALOG CONTROL
. . . . . . . . . . . . . . .
16-STATION MEMORY - 7-SEGMENT LED DISPLAY VOLTAGE SYNTHESIZER : 13 BITS 4-BAND PRESET CAPABILITY NON-VOLATILE MEMORY : 304 BITS - 16 WORDS OF 19 BITS FOR TUNING VOLTAGE (13 bits) - BAND (2 bits) - FINE DETUNING (4 bits) - 104 MODIFY CYCLES PER WORD - MIN 10 YEARS DATA RETENTION PCM REMOTE CONTROL RECEIVER : DECODES SIGNAL TRANSMITTED BY M708 VOLUME D/A : 6-BIT RESOLUTION / 8kHz MEMORY SKIP FUNCTION AUTOMATIC SEARCH WITH DIGITAL AFT CONTROL FINE DETUNING D/A ACTING ON AFT DISCRIMINATOR (16 steps) WITH SEPARATE STORAGE FOR EACH MEMORY POSITION. ALTERNATIVELY IT CAN BE USED TO CONTROL BRIGHTNESS OR COLOUR SATURATION MANUAL SEARCH WITH DIGITAL AFT CONTROL MANUAL SEARCH WITH LINEAR AFT SWEEP SEARCH DISPLAY OUTPUT SUPPLY VOLTAGES : VDD = + 5V, VPP = + 25V FOR THE MEMORY CLOCK OSCILLATOR : 445 TO 510kHz INTEGRATED DIGITAL POWER ON RESET (no external initialization circuitry required)
tion with the transmitter M708. The highly reliable transmission code ensures error-free signal detection even in presence of high noise conditions. Search of the station is possible in automatic or manual modes. The circuit can operate with a Digital or Linear AFT control. The Digital AFT mode is necessary for automatic search and requires an external circuit (TDA4433 or equivalent, e.g. dual comparator plus TV station detector) to convert the AFC-S-curve into an Up/Down command. Fine tuning (detuning) is also possible with different modes of operation. The circuit is assembled in 40-pindual in-line plastic package.
DIP40 (Plastic Package) ORDER CODE : M491B1
PIN CONNECTIONS
V SS (GND) MEMORY SUPPLY MEMORY TIMING FINE TUNING D/A TUNING D/A DIGITAL AFT STATUS OSC. IN OSC. OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VHF I VHF III CATV UHF SEGM.h + i SEGM. g SEGM.f SEGM. e VS S (GND) OPT. 8/16 SEGM. d SEGM.c SEGM. b SEGM. a MAINSON/OFF MAINS ON OPTION X1 X2 X3 X4 491B-01.EPS
DESCRIPTION The M491B is a monolithic N-MOS LSI circuit including a Floating-gate Non-Volatile Memory for storage of up to 16 stations. Tuning of the station is performed with a 8192 step D/A converter, using the principle of voltage synthesis. It is designed for 7-segment LED displays. Direct memory selection is possible only from remote control while Up/Down memory scanning is possible on the set and also from remote control. An option input for 8 or 16 stations is available. The circuit also includes a PCM remote control receiver operating in conjuncSeptember 1992
VDD TEST I.R. INPUT AFT 1 AFT 2 SWEEP DISPLAY OUT VOLUME D/A LINEAR AFT DEF. DIGITAL AFT EN. V3 V2 V1
1/16
2/16
V PP (25V) +5V IR V DD V SS
M491B
FUNCTIONAL DIAGRAM
445 to 510MHz
M708
TDA2320 or 8160
445 to 510MHz
MT
1 3 2 7 8 10
MS
OSC IN
OSC OUT
TEST
11 V SS 32 5
TUNING D/A FINE TUNING D/A VHF I
9
OPT. 8/16 40
VHF III
31
4
4.5 to 13.2V
h CAT V 38 UHF 37 14 SWEEP DISPLAY OUT AFT1 12
BAND OUT
f
a 39
g
b
i
e
c
d
+12V
M491B
a
27
b
28 29 30 33 34 35 36 17 16 15 26 25 6 13
c
AFT2
AUTO SEARCH STOP DIGITAL AFT
DIGITAL AFT STATUS DIGITAL AFT ENABLE
UP (AFT1) (AFT2) DOWN
AFC-Scurve
d
e
LINEAR AFT DEFEAT VOLUME D/A MAINS ON/OFF
f
g
h-i
MAINSON OPTION
20 V1
V2
19
18 V3
24 22 21 23 X1 X2 X3 X4
491B-02.EPS
M491B
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VPP VI VO (off) IOL Parameter Supply Voltage Memory Supply Voltage Input Voltage Off State Input Voltage (except pin 3) Pin 3 Output Low Current Led Driver Outputs Pins 6 - 14 Pins 4 - 5 All Other Outputs Max. Delay between Memory Timing and Memory Supply Pulses Total Package Power Dissipation Storage Teperature Operating Temperature Value - 0.3, + 7 - 0.3, + 26 - 0.3, + 15 15 28 20 20 7.5 5 5 1 - 25, + 125 0, + 70 Unit V V V V V mA
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Tamb = 0 to + 70C, VDD = +5V unless otherwise specified)
Pin 2-Memory Supply Symbol IPP Parameter Memory Supply Current Test Conditions VPP = 25V Write Peak Average Erase Peak Average Read Peak Average VDD = 4.75 V, VDD = 4.75 V, VDD = 5.25 V, VDD = 4.75 V, VDD = 4.75 V, VDD = 5.25 V, VDD = 5.25 V IOL = 2.5 mA VOUT = 26 V VO (off) = 13.2 V IOL = 5 mA IOL = 20 mA VO (off) = 13.2 V 0.5 VDD = 5.25 V VDD = 5.25 V VDD = 5.25 V, VIL = 1.5 V VDD = 4.75 V, VDD = 5.25 V, VDD = 4.75 V, VDD = 5.25 V, VDD = 4.75 V, VDD = 5.25 V, IOL = 20 mA VO (off) = 13.2 V IOL = 4 mA VO (off) = 13.2 V IOL = 1 mA VO (off) = 13.2 V 2.0 VDD = 5.25 V, VIL = 0.8 V Pull-up Resistor 3.5 Min. Typ. Max. Unit mA 42 12 9 5 8 2.5 25 k 8 V 100 A 50 A 1 V 1.5 V 100 A 100 mA 13.2 V 1.5 V V -0.4 mA 30 k 1.5 V 100 A 1 V 50 A 0.4 V 50 A 0.8 V V -0.4 mA 30 k
3-Write Timing Out 4-Fine Tuning D/A 5-Tuning D/A 6-Digital AFT Out 9-Power Supply 11-I.R. Input 12-AFT1 13-AFT2
R VOL IO (off) IO (off) VOL VOL IO (off) IDD VIPP VIL VIH IIL R VOL IO (off) VOL IO (off) VOL IO (off) VIL VIH IIL R
Pull Down Resistor Output Low Voltage Output Leakage Current
Supply Current Peak-to-Peak Voltage Input low Voltage Input High Voltage Input Low Current Pull-up Resistor
14--Display Out 15-Volume D/A 16-Linear AFT Out
3/16
491B-02.TBL
17-Digital AFT Enable
491B-01.TBL
tpd Ptot Tstg Top
s W C C
M491B
DC ELECTRICAL CHARACTERISTICS (continued)
Pin 18-19-20 V3 V2 V1 Symbol VIL VIH IIL R VOL X4 X3 X2 X1 Pull-up Resistor VDD = 4.75 V, IOL = 1 mA VDD = 5.25 V, VIL = 0.8 V 30 0.4 3.5 -0.4 Parameter Test Conditions Min. Typ. Max. 1.5 Unit V V mA k V A V V -0.4 30 0.4 -1.6 0.4 50 3 2.4 0.3 3 VDD = 5.25 V, VO (off) = 13.2 V VDD = 4.75 V, IOL = 20 mA VDD = 4.75 V, IOL = 30 mA 2.0 0.8 50 1.5 1.5 mA k V mA V A V V V V A V
491B-03.TBL
} }
Keyboard In
21-22-23-24 Keyboard Out
IO (off) VIL
VO (off) = 5.5 V
25 0.8 2.4
25-Mains On Enable
VIH IIL R Pull-up Resistor VOL IO VOL IO (off) VOL VDD = 5.25 V VIL = 0.8 V VDD = 4.75 V, IOL = 100 A VDD = 4.75 V, VO = 0.7 V VDD = 4.75 V, IOL = 1 mA VDD = 5.25 V, VO (off) = 13.2 V VDD = 4.75 V, IOL = 1 mA VDD = 4.75 V, IOH = - 150 A
26-Mains On/Off 31-Z2 32-Z1 MPX for Display Out 37-UHF 38-CATV 39-VHFIII 40-VHFI B A N D
}
VOH VIL VIH IO (off) VOL VOL VIH VIL
27-28-29-30-3334-35 Display Out 36-Display Out 31-Memory 8/16
V V V
DESCRIPTION (All timings at fclock = 500kHz) PIN 1 : VSS The substrate of the IC is connectedto this pin. This is the reference pin for all parameters of the IC. PIN 2 : MEMORY SUPPLY VOLTAGE A supply voltage of 25 1 V has to be applied to this pin during the modify and read cycles. MODIFY CYCLE A modify cycle consists of three steps : 1. All "1"s are written in the bits of the selected word. 2. All bits of the selected word are erased (all "0"s) 3. The new content is written. Thus a constant aging of all the bits of the word is obtained. During both write and erase cycles the memory status is checked continuously ; therefore after each writeor erase pulsea read operationis carried out. The write or the erase operations are stopped as soon as the result of the read operation is valid. WRITE CYCLE. The peak of the current flowing through pin 2 during a write operation is shown in fig. 1, while fig. 2 shows the envelope of the same current. The typical write time is 3-4 ms for the first cycles and increases to about 30 ms after 1000 cycles.
4/16
M491B
Figure 1
40mA
12mA 6mA
64
32 44 256s
116s
After about 30msec
491B-03.EPS
Figure 2
I (mA) 40
12
491B-04.EPS
5 Typ. max. 20msec Typ. max. 8msec
t (ms)
ERASE CYCLE Figure 3 shows the timing and the waveform of the current flowing through Pin 2 during the erase operation. The peak current is 7mA (max) during the erase cycle and 6mA (max) during the read cycle. The typical erase time is 10ms for a new device and increases with the number of modify Figure 3
7mA 6mA
operations up to 200ms after 1000 cycles. In order to protect the memory in case of failure of some bits the modify operation is stopped after 1sec. READ CYCLE Figure 4 shows the waveform of the current during a read operation. Figure 4
6mA
128s
32 44
52
491B-05.EPS
44
84s
491B-06.EPS
128s
256s
480s
5/16
M491B
PIN 3 : MEMORY TIMING OUTPUT This output gives the timing for the pulses to be applied at Pin 2 during the modify and read cycles. The output consists of an open drain transistor. PIN 4 : FINE TUNING D/A (see Figure 5) A D/A converter with 16-step resolution and a frequency of 15kHz can be used to generate a voltage which, if fed to a varicap diode in parallel to the AFC discriminator, will detune the receiver by a small f while maintaining the action of the Digital AFT. This output can be used in conjunction with both Linear and Digital AFT modes of operations. The Fine tuning function operates as follows : - At the start of any automatic or manual search, the output is set at the mid range. - When the search has been completed it is possible to operate on FT commands. The store command memorizes this information Figure 5
64s
together with the 13 tuning voltage bits and 2 information bits. - Modification time of FT D/A is of 1 step every 200ms if issued locally or every 2 received signals from Remote control transmitter. PIN 5 : TUNING D/A (see Figure 6) A 213 = 8192 step pulse modulated signal for the tuning voltage is available on this pin. Pulse modulation is implemented by combination of a rate multiplier and pulse width principle. With a tuning voltage increasing from zero, the number of pulses increases continuously up to 28 = 256 ; starting from this point the number of pulses remains the same but the pulses get larger until they reach the maximum content of the internal counter. The output consists of an open drain transistor which offers a low impedance to ground when in the ON state.
9
7
FT FT
Mid Range
VOUT
Fine Tuning Output
6/16
491B-07.EPS
M491B
Figure 6
D/A Converter VA VB
Varicap VC
VA VB
VC down-up
PIN 6 : DIGITAL AFT STATUS OUTPUT (see Figure 7) This output shows the status of the digital AFT. It is low when the digital AFT is enabled and it can directly drive a LED. The output consists of an open drain transistor. PINS 7 & 8 : OSCILLATOR INPUT/OUTPUT (see Figure 8) The frequency of the clock oscillator should be between 445 and 510kHzusing a low-cost ceramic resonator. In these conditions the value of the reference frequency of the transmitter can be in the same range. In other words the transmitter and the receiver can operate with different reference frequencies. Figure 7
max. 13.2V
Figure 8
7 455 to 510kHz 100pF
8
100pF
6
PIN 9 : VDD The supply voltage has to be comprised in the range 4.75 to 5.25V. When it is applied an internal power on reset of 0.5s is generated. The memory position 1 is automatically read if the mains on option input (Pin 25) is grounded. PIN 10 : TEST This pin is used for testing and has to be connected to VSS. PIN 11 : I.R. SIGNAL INPUT (see Figure 9) The integrated receiver decodes signals transmitted by M708, address 9. The minimum signal to be applied is 0.5V peak-topeak. (AC-coupled). The receiver input section performs the following tests on the incoming signal to achieve the necessary noise immunity : - measurement of the pulse distance (time base synchronization)
491B-09.EPS
7/16
491B-10.EPS
491B-08.EPS
M491B
- check of the position of the received bits opening window at the time bases - check of the parity bit - checkof the absenceof pulses between the parity bit and the stop pulse - checkof noise level ; the receiver checks parasitic transients inside and outside the time windows. If the above test conditions are not fulfilled, the Figure 9
TDA2320 or TDA8160 R C M491B
received word is rejected and not decoded. If the received signal is acknowledged as a valid word it is stored an decoded. The end of transmission will be acknowledged by receiving the end of transmission code or by means of an internal timer if the transmission remains interrupted for more than about 550ms.
M491B REMOTE CONTROL RECEIVER TRUTH TABLE. Transmitter M708 ; Address Code 9
Command Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 C1 0 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 C2 0 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 I.R. Code C3 C4 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 C5 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 C6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Function End to Transmission Power On/Off Mute On/Off Memory 1 Memory 2 Memory 3 Memory 4 Fine Detuning Up Fine Detuning Down Memory 5 Memory 6 Memory 7 Memory 8 Memory Up Memory Down Memory 9 Memory 10 Memory 11 Memory 12 Manual Search Up Manual Search Down Memory 13 Memory 14 Memory 15 Memory 16 Mute Volume Up Volume Down Memory Addressing Digital AFT On Band Sequential Automatic Search
}
PINS 12 & 13 : AFT1-AFT2 (STOP/AFT INPUTS) These pins are enabled during the automatic search and during normal operation, when the digital AFT is enabled (see description of Pin 17). The STOP/AFT inputs are also disabled internally during any program or bandchange for the duration of the Mute signal.
8/16
491B-04.TBL
491B-11.EPS
Supply Voltage of TDA2320 5 12
R 2.2k 10k
C 4.7nF 4.7nF
M491B
These pins work according to the truth table given below :
M491B Pin 12 TDA4433 Pin 2 H L L H M491 B Pin 13 TDA4433 Pin 6 L H L H Function (referred to the tuning voltage) Up Down Middle No Operation
These inputs have two different functions depending on whether the system is in the search or in normal operation (AFT control). The inputs have internal pull-up resistors of 30k typ. A) Search mode : after depressing the Automatic search or preset keys, the levels of the signals coming from the TDA4433, applied to these pins, control the search function and determine when the search must stop, i.e. a TV stationhas been recognized. The circuit operates in the following sequence (see Figure 10 for reference) : 1 - after pressing the search start key the search occurs in the FAST UP mode. 2 - eventual transitions available on these inputs are ignored during the first 15 search steps if the system is in the UHF or CATV bands. If the system operates in VHF I and III bands, the first 60 search steps are ignored. The acceptance delay of 15 (60) search steps has been introduced to prevent the system from stopping at the previous station. Aft er this time the FAST UP speed is automatically reduced to half during each UP signal (MEDIUM UP = FAST UP/2). A DOWN signal preceded by at least an UP signal will set the search to MEDIUM DOWN mode (FAST UP/4). 3 - the next UP signal will switch the search to SLOW UP speed (61Hz). At this point the systems is in normal AFT operation.
B) Digital AFT operation : when a station is perfectly tuned, the input signals coming from TDA4433 are at middle condition. If the tuning moves lower than the threshold below 38.9MHz, the Pin 12 is put H and Pin 13 is put L ; the 13 bit internal counter is moved SLOW UP speed to increase the varicap voltage. When a detuning occurs in the opposite direction the input 12 goes Low and 13 goes High and the tuning voltage falls at VERY SLOW DOWN speed (7.6Hz). The increase or decrease of the tuning voltage is stopped as soon as the input returns to middle conditions. Therefore during normal operation Pins 12 and 13 act as digital AFT control commands. C) Recall from memory : when the digital AFT is enabled and data is recalled from Memory, a fixed value of 8 steps ( 31.2mV) is subtracted from the tuning voltage. This corresponds to a detuning of 0.6MHz (UHF) and of 0.3MHz in VHF III into that part of the IF response curve which corresponds to the fully transmitted sideband. At this point the AFT operation takes over as described in point B above and the exact tuning is achieved in about 0.2 sec. This feature increases the AFT capture range and fullfills the stability requirements of the tu ne r, voltage refere nces and the D/A converter. If the Digital AFT is disabled (Pin 17 at VSS), the memory content is read without any change.
9/16
461B-05.TBL
M491B
Figure 10
34 35 36 37 38MHz
IF RESPONSE
38.8 39
NORMAL AFC POSITION
40MHz TRANSMITTER IDENTIFICATION Pin 6 SIGNALS ON TDA4433 SEARCH START t 40 39
SEARCH DIRECTION
38.8 Pin 2 FAST UP S1 MEDIUM UP S2 = 0.5 S1 MEDIUM DOWN S3 = 0.25 S1 SLOW UP S3 = 67Hz NORMAL AFC OPERATION VARICAP VOLTAGE STOP
38.8 MHz
DIGITAL INFORMATION
139.0MHz AFC THESHOLD 38.8MHz
t
PIN 14 : SWEEP SEARCH DISPLAY OUTPUT This output, which is normally Low, goes High during automatic search automatic preset et intervals of 160ms for about 40ms to blank the LED of band display. Figure 11
BAND LEDS
10/16
491B-13.EPS
V SS
PIN 15 : VOLUME D/A OUTPUT This output delivers a square wave signal of 7.8 kHz and duty cycle variable in 63 steps. In case of a continuous command for varying the volume, the duty cycle is changed at the rate of the transmitted signal (approximately every 102ms with fref = 500kHz) or every 112ms if issued locally. Overflow and underflow protection are provided. The volume output can be switched to VSS and reset to the previous level by means of the Mute On/Off command. It is also reset by the Volume Up/Down and the Mains On/Off commands. The volume is muted for about 1s at each mains on and off command during the power on reset time and program change (0.5s). At the first power on reset of VDD the volume D/A is set at the level 21/64. The last level is preserved until VDD is not removed.
491B-12.EPS
M491B
PIN 16 : LINEAR AFT DEFEAT OUTPUT This output is normally High and goes Low when a Manual Up/Down command is issued. It returns High with a 1 second delay from the release of the key, in order to give the user the possibility of the tuning adjustment without the AFT intervention. It goes Low for 0.5s during program change. Figure 12
MAN UP/DOWN KEY PRESSED MAN UP/DOWN KEY RELEASED
1sec
PIN 17 : DIGITAL AFT ENABLE INPUT If this input is connected to VSS (GND), the digital AFT loop is always disabled. If pin 17 is left open or is connected to VDD, the digital AFT is automatically enabled at power on. When a manual up/down search commandis issued, the digitalAFT loop is disabled and the digital AFT status output is inhibited. The digital AFT loop is restored by the commands: Digital AFT on/Automaticsearch/Automatic preset. PINS 18-19-20-21-22-23-24 : KEYBOARD MATRIX (see Figure 13) A command is accepted if the corresponding conFigure 13
V1 20 MEMORY UP MEMORY DOWN MAN SEARCH UP MAN SEARCH DOWN DIGITAL AFT ON AUTOMATIC SEARCH FT. UP FT. DOWN V2 19 BAND SEQ. POWER ON/OFF VOLUME UP VOLUME DOWN
491B-14.EPS
LINEAR AFT DEFEAT OUTPUT
tact has been closed for a minimum time of 30ms. Local input commands and I.R. commands have the same priority. If a complete I.R. command has been received, the local inputs are blocked until the command has been executed and the "end of transmission code" generated. Viceversa an I.R. signal cannot be decoded until an issued local command has been executed. MEMORY UP/DOWN Depressing one of these two commands, the memory position is stepped in the UP or DOWN direction. If the key is kept closed, the channels are stepped UP/DOWN every 0.5 second or every 5 commands from the transmitter. The memory locations 9 to 16 are jumped if pin 31 is at GND level. BAND SELECTION The bands can be selected either directly or with a step-by-step command in the following sequence : VHF I CATV VHF III UHF VHF I and so on Only one band change is performed at each accepted command. Disabled bands are automatically skipped. A band can be disabled connecting the corresponding output to VSS.
V3 18 BAND I BAND III BAND UHF BAND CATV AUTOMATIC PRESET
X1 24
X2 23
X3 22
X4 21
MEMORY ADDRESSING STORE
491B-15.EPS
MUTE
11/16
M491B
SEARCH MODES 4 modes are available : a) Automatic search (digiatl AFT) b) Automatic preset c) Manual up/down (digital and linear AFT) d) Manual up/down (linear AFT) a) AUTOMATIC SEARCH. The search starts from the actual tuning and band position. During the search the tuning voltage is always changing from lower to higher voltage levels. When the end of the band is reached the search restarts from the beginning of the next band after a 480 ms interruption with the sequence of step-by-step band selection. Disabled bands are automaticallyskipped. The search is stopped when the first station is found or if a channel selection command is given. Stop of the automatic search is determined by the STOP/AFTinputs controlledby the TDA4433 which converts the AFC-S-curve into an up/down command. At the end of the search the up/down command controls the correct tuning acting on the counter of the voltage synthesizer (Digital AFT). It is important to call the attention to the Digital AFT capture range which is larger than the normallinear AFT as shown in fig. 14. Figure 14 VHF I 8 second VHF III 8 second UHF 32 second CATV 32 second The tuning and band information can be stored using the store/memory addressing command. The search can be stopped by a memory selection command. b) AUTOMATIC PRESET. The search starts from the lowest memory address, tuning voltage and VHF I band as described in automatic search mode. When an active station is encountered, the corresponding tuning and band information is automatically stored in the Non-Volatile Memory. Afterwards the system starts to search for the next station. The cycle is repeated until all bands have been scanned or the tuning information has been stored into all address locations. After completing this cycle the system reads out the tuning information of the lowest address. c) MANUAL UP/DOWN WITH DIGITAL AND LINEAR AFT (pin 17 at VDD). Holding one of these commands pressed, the tuning voltage is increased or decreased. During this operation, the Digital AFT is automatically defeated and can only be reconnected with the "AFT on" command or by an Automatic search or preset command. The search speed is kept at minimum (there is no increment with the time)
Band
LINEAR AFT CAPTURE RANGE DIGITAL AFT CAPTURE RANGE
491B-16.EPS
VHF I VHF III UHF CATV seconds
Sweep Timefor the Complete Band 128 seconds 128 seconds 512 seconds 512 16
Number of Tuning Steps/Second 64 64 16
Additionally the use of the Digital AFT allows storage of the tuning information corresponding to the zero point of the AFC-S-curve. This cannot be guaranteed using the Linear AFT method only. The latter is a cheaper system, because it does not require the use of the TDA4433 but it cannot guarantee what described above. As a result of the use of the Digital AFT, the requirements for stability of the tuner, of the reference voltage source and of stability of the D/A converter are less critical. Tuning speed in automatic search, if no station is found is :
In case of command received from remote control, the counter is increased/decreased every two received commands. No band switching is provided at the upper or lower tuning positions. The volume is automatically muted 3 second after the key pressure is immediately restored at the release of the key. d) MANUAL UP/DOWN WITH LINEAR AFT (pin 17 at VSS). When this control is used the Digital AFT is disabled. The Linear AFT output goes low after an up or down command is issued and remains Low for 1 second after the release of the key.
12/16
M491B
The volume is automatically muted for 3 seconds after the key pressure and is immediately restored at the release of the key. Tuning speeds are as follows : - FINE TUNING UP/DOWN See description of pin 4. - DIGITAL AFT ON See description of pin 17. - VOLUME UP/DOWN See description of pin 15. - MAINS ON/OFF See description of pins 25 and 26.
Band VHF I VHF III UHF CATV Number of Tuning Steps Second Time 0 64 64 16 16 After 1 s 128 128 32 32 After 2 s 256 256 64 64 After 3 s
491B-06.TBL
Figure 15
+5V
512 512 128 128
STORE COMMANDS 2 modes of operations are available. a)store b)memory addressing In order to protect the memory, the store function is internally disabled after one store cycle. It is enabled after a program change or a tuning operation (it is not disabled by the Digital AFT control). a) STORE. The tuning information (Tuning D/A, Fine tuning D/A and band) is stored in a previously selected memory address when this command is issued. b) MEMORY ADDRESSING. The tuning information can also be stored with this command followed by the memory position selection. When this command is accepted all the memory LEDs are blanked. Selection of the memory position initiates the store operations and restores the display. MUTE ON/OFF See description of pin 15. PIN 25 : MAINS ON OPTION INPUT If connected to VSS (GND) the Mains output is automatically switched on when VDD is applied and memory 1 is read. If it is connected to VDD the circuit goes in stand by condition. PIN 26 : MAINS ON/OFF OUTPUT Switch on of the set is controlled by the Mains on command issued for more than 0.3 s. The output transistor is set in the off condition to drive through an integrated pull-up resistor, an external NPN transistor.
At each Mains on command a memory read out occurs. AVPP (+ 25 V) is required for this operation, a 1 second delay starts when the mains output is switched off. For a correct reading of the memory the VPP supply voltage must reach the value of 25 V within 1 second after a Mains on command. In case of automatic switch on at power on caused by pin 25 at GND, the total delay is of 1.13 second (0.13s for VDD power on reset plus 1 second for mains on). The Mains on/off command, if repeated, will switch the output on (set off). The last address information is preserved until VDD is present. Next Mains on command will switch the set at the previously selected memory address and a read operation will be performed. PINS 27-28-29-30-33-34-35-36: MEMORY ADDRESS OUTPUT These pins operate as output only for display of the selected memory location. Max drive capability is of 15 mA/1.2 V with the exception of pin 36 that is of 30 mA/1.5 V. Direct memory selection is only possible by remote control. A local memory up/down command is available in case of emergency. Pin 32 must be grounded. If pin 31 is grounded, the memory position 9 to 16 are skipped in case of memory up/down commands. For normal operation pin 31 can be left open or, better, connected to VDD. PINS 31-32 See description of pins 27 to 30 and 33 to 36. PINS 37-38-39-40 : BAND INPUT/OUTPUT These outputs are provided to select up to 4 bands via external PNPs. If one or more bands have to be skipped, the corresponding outputs have to be short-circuited to VSS.
13/16
491B-17.EPS
M491B
Figure 16
max. 13.2V
INPUT/OUTPUT CONFIGURATION Output Open Drain Inputs/Outputs (std)
491B-19.EPS
Pins 3, 4, 5, 6, 14, 15, 16, 30, 33, 34, 35, 36
Pins 37, 38, 39, 40, 21, 22, 23, 24 (21, 22, 23, 24 are used only for testing purposes)
Output Push-pull
VDD
Oscillator
VDD
26
7
491B-20.EPS
8
491B-23.EPS
Inputs with Pull-up Load
V DD
IR Input
V DD
Pins 12, 13, 17 18, 19, 20, 25, 31
491B-21.EPS
11
491B-24.EPS
14/16
491B-22.EPS
491B-18.EPS
The relation between pins and bands are as follows : Pin 37 = UHF Pin 38 = CATV Pin 39 = VHF III Pin 40 = VHF I
R2 HIGH VOLTAGE R1(k) = 11mA R2 = R1/4 33k TUNING VOLTAGE 33V TAA550B 100nF 150nF 100nF 100nF 4.7k 47pF BC297 2.2k 4.7nF 6.8 k +5V 3.3k 11 25 1.5 k 5 8.2k 37 8.2k 39 8.2k 40 7 x 0.68k 14
27
V H (V) - 33V 1.6 k 1%
R1
33k
56k
82k
22 F 82 k BSX93 or 2N3903
+ 5V
5.6 k 1%
445 to 510MHz 3.9k 3 9 31 2
M708
TDA2320 or 8160
+ 12V 32 10 k BC177 BC177 BC177 10 k 10 k
TYPICAL APPLICATION Manual Search with Linear AFT (16 memory option)
+12V
0.33 k
M491B
38 17
I III UHF
28 29 30 33
34 35 36 15
26
0.68k +12V 16 5.6k +12V BC108 ON/OFF RELAY
LOCAL COMMANDS
20 19 18 24 23 22
21
7
8
10
1
500kHz
LINEAR AFT DEFEAT VOLUME 100 pF 100 pF 22k 10F
1 - Memory Up 2 - Memory Down 3 - Search Up 4 - Search Down 5 - Band Sequential 1 2 3 4
6789-
Power On/Off VolumeUp VolumeDown Store
5 6 7 8 9
M491B
15/16
491B-25.EPS
M491B
PACKAGE MECHANICAL DATA 40 PINS - PLASTIC DIP
a1
L
I
b1 b b2 e3 e E
D
40
21
F
1
20
Dimensions a1 b b1 b2 D E e e3 F i L
Min.
Millimeters Typ. 0.63 0.45 1.27
Max.
Min.
Inches Typ. 0.025 0.018 0.050
Max.
0.23
0.31 52.58 16.68 2.54 48.26 14.1 4.445 3.3
0.009
0.012 2.070 0.657 0.100 1.900 0.555 0.175 0.130
DIP40.TBL
15.2
0.598
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without noti ce. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
16/16
PM-DIP40.EPS

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