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Ordering number: EN 6158
CMOS IC
LC7940YD,7941YD Dot-matrix LCD Drivers
Overview
The LC7940YD and LC7941YD are segment driver ICs for driving large, dot-matrix LCD displays. They read 4- bit parallel or serial input, display data from a controller into an 80-bit latch, and then generate LCD drive signals corresponding to that data. The LC7940YD and LC7941YD feature mirror-image pin assignments, allowing them to be used together to increase component density. They are designed to be used with the LC7942YD common driver to drive large LCD panels.
Package Dimensions
unit: mm
3180-QIP100D [LC7940YD, LC7941YD]
23.2 20.0 0.825 0.575
80 81
1.6 0.3
51 50
0.65
0.15
17.2 14.0
2.15
* *
21.6
0.8
SANYO : QFP100D (QIP100D)
* *
Specifications
Absolute Maximum Ratings at Ta = 25 2C, VSS = 0 V
Parameter Logic supply voltge LCD supply voltage, See Note below. Input voltage Symbol VDD max VDD - VEE max VI max Ratings -0.3 to +7.0 0 to 22 -0.3 to VDD + 03 Unit V V V
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Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
s
SANYO Electric Co., Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
63099RM (ID) No. 6158--1/11
0.8
1
30
2.45max
* * * *
80 built-in LCD display drive circuits 1/8 to l/128display duty cycle Serial or 4-bit parallel data input Chip disable for low power dissipation for large-sized panels Bias supply voltags can be supplied externally Operating supply voltage and ambient temperature - 2.7 to 5.5 V logic supply ( VDD) at Ta = -20 to +85C - 8 to 20V LCD supply (VDD - VEE ) at Ta = -20 to +85 C CMOS process 100-pin flat plastic package
1.6
31 100
15.6
Features
0.65
LC7940YD, LC7941YD
Parameter Operating temperature range Storage temperature range
Symbol Topr Tstg
Ratings -20 to +85 -40 to +125
Unit C C
Note VDD V1> V3 > V4 > VEE
Recommended Operating Condltions at Ta = -20 to + 85C, VSS = 0V
Ratings Parameter Logic supply voltage LCD supply voltage HIGH-level input voltage Symbol VDD VDD - VEE VIH See Notes 1 and 2. CP, CDl, DI1 to DI3, M, SDl, P/S, DISPOFF and LOAD CP, CDI, Dl1 to DI3, M, SDl, P/S,DISPOFF and LOAD Conditions min 2.7 8 0.8VDD typ - - - max 5.5 20 - V V V Unit
LOW-level inpvt voltage CP shift clock frequency CP pulsewidth LOAD pulsewidth DIn and SDI to CP setup time DIn and SDI to CP hold time CP to LOAD time LOAD to CP time CP rise time CP fall time LOAD rise time LOAD fall time
VIL fCP tWC tWL tSETUP tHOLD tCL1 tCL2 tLC tR tF tRL tFL
-
- -
0.2VDD 3.3 - - - - - - - 50 50 50 50
V MHz ns ns ns ns ns ns ns ns ns ns ns
100 100 80 80 0 100 100 - - - -
- - - - - - - - - - -
Notes 1. VDD Vl > V3 > V4 > VEE 2. At turn ON, the LCD supply should be energized after or simultaneously with the logic supply. At turn OFF, the logic supply should be cut after or simultaneously with the LCD supply.
Electrlcai Characterfstlcs at Ta = 25 2C,VSS = 0V, VDD = 2.7 to 5.5 V
Ratings Parameter Symbol Conditions min HIGH-level input current IIH VIN =VDD; LOAD, CP, CDI, P/S, DI1 to DI3, SDl, M, and DISPOFF VIN = VSS; LOAD, CP, CDl, P/S, DI1 to DI3, SDI, M, and DISPOFF IOH = -400 A IOL = 400 A VDD - VEE = 18 V, |VDE - VO|= 0.25 V. See note - typ - max 1 A Unit
LOW-level input current CDO HIGH-level output voltage CDO LOW-levef output voltage O1 to O80 driver ON resistance
IIL VOH VOL RON
- VDD - 0.4 - -
- - - 2
-1 - 0.4 4
A V V k
No. 6158--2/11
LC7940YD, LC7941YD
Ratings Parameter Symbol Conditions min CDI = VDD, VDD - VEE = 18 V, fCP = 3.3 MHz, no output load ; VSS VDD - VEE = 18 V, fCP = 3.3 MHz, ILOAD= 5.156 kHz, fM = 52 Hz ;VSS VDD - VEE = 18V, fCP = 3.3 MHz, fLOAD = 5,156 kHz, fM = 52 Hz ; VEE fCP = 3.3 MHz ; CP typ max Unit
VDD to VSS standby supply current
IST
-
-
200
A
VDD to VSS operating supply current
ISS
-
-
1.0
mA
VDD to VEE operating supply current
IEE
-
-
0.1
mA
CP input capacitance
CI
-
5
-
pF
Note VDD = V1 or V3, or V4 or VEE, V1 = VDD, V3 = 9/11 x (VDD - VEE), V4 = 2/11 x (VDD - VEE)
Switching Characteristics at Ta = 25 2C,VSS = 0 V, VDD = 2.7 to 5.5 V
Ratings Parameter CDO output delay time Symbol tD Conditions min CL = 30 pF - typ - max 200 ns Unit
Switching Characteristics Waveform
tR CP
tWC
tF
tWC 0.8VDD 0.2VDD
tSET UP SDI DI1 to 3 tCL (1) LOAD tRL
tHOLD
tCL (2)
tFL tLC
tWL tD tD
CDO
No. 6158--3/11
LC7940YD, LC7941YD
Pad Layout (Top view)
080
079
078
077
076
075
074
073
072
071
070
069
068
067
066
065
064
063
062
061
060
059
058
057
056
055
054
053
052
NC CDO NC DISP OFF P/S VSS VEE V4 V3 NC VDD V1 M DI1 DI2 DI3 SDI LOAD CDI CP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 49 48 47 46 45 44 43 42
051
050 049 048 047 046 045 044 043 042 041 040 039 038 037 036 035 034 033 032 031
LC7940YD
41 40 39 38 37 36 35 34 33 32
31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 01 02 03 04 05 06 07 08 09 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024 025 026 027 028 028 029 029 030 030
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
CP CDI LOAD SDI DI3 DI2 DI1 M V1 VDD NC V3 V4 VEE VSS P/S DISP OFF NC CDO NC
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
027
01
02
03
04
05
06
07
08
09
031 032 033 034 035 036 037 038 039 040 041 042 043 044 045 046 047 048 049 050
LC7941YD
31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 080 079 078 077 076 075 074 073 072 071 070 069 068 067 066 065 064 063 062 061 060 059 058 057 056 055 054 053 052 051
No. 6158--4/11
LC7940YD, LC7941YD
Block Diagram
01 02 03 079 080
V1 V3 V4 VEE 80 Level Shifter (80 bits) M 80 2nd Latch (80 bits) 80 1st Latch (80 bits) 4 SDI DI3 DI2 DI1 4 bits Data Bus Interface CLK Address Counter (7 bits) 20 Address Decoder DISP OFF 4 Level LCD Drive Circuit (80 bits) VDD VSS
P/S CDI CP LOAD
SER/PAR Control
Chip Disable & Latch Control
CDO
Pin Functions
Pin No. Synbol LC7940YD 91 86 87 92 89 88 l00 99 98 97 LC7941YD 90 95 94 89 92 93 81 82 83 84 VDD VSS VEE V1 V3 V4 CP CDI LOAD SDI I I I I Supply LCD panel drive voltage supplies V1 and VEE are selected levels. V3 and V4 are not-selected levels. Display data Input clock (falling-edge trigger). Chip disable. Data is read in when LOW, and not road in when HIGH. Display data latch clock (falling-edge trigger). On the falling edge, the LCD drive signals set by the display data are output. Serial data input. Supply VDD - VSS is the logic supply. VDD - VEE is the LCD supply. I/O Functions
No. 6158--5/11
LC7940YD, LC7941YD
Pin No. Synbol LC7940YD 96 95 LC7941YD 85 86 DI3 DI2 4-bit parallel data input pins. Data input SDI I 94 87 D11 DI3 DI2 DI1 O4 O3 O2 O1 LCD driver outputs O8 O7 O6 O5 O80 O79 O78 O77 I/O Functions
In serial data input mode, DI1 to DI3 should all be tied HIGH or LOW. 93 85 82 88 96 99 M P/S CDO I I O LCD panel drive voltage output alternation control signal. Data input mode select. 4-bit parallel input when HIGH, and serial input when LOW Cascade connection pin for extension segment drivers. Data is read out when HIGH. Goes LOW after data is read out. Connected to the CDI input of the next chip. LCD drive outputs. The output drive level is determined by the display data, M signal and DISP OFF input as shown below. M LOW 1 to 80 80 to 1 Ol to O80 O LOW HIGH HIGH x Q LOW HIGH LOW HIGH x DISP OFF HIGH HIGH HIGH HIGH LOW Output V3 V1 V4 VEE V1
Note x = don't care (tied HIGH or LOW) 84 81 83 90 97 91 98 100 DISPOFF NC NC NC - No connection. I O1 to O80 output control input pin. When LOW, V1 is output on the O1 to 080 outputs, See the truth table.
No. 6158--6/11
2
OD1 ED1 CP LOAD
LCD Panel 1
4
CP SDI LOAD
M V4 VEE M V1 V3 V4 VEE CDI (LC7940YD) LC7941YD (LC7940YD) LC7941YD CDO CDI CDO VEE VEE CDI CDI (LC7940YD) LC7941YD CDO V4 V4 V1 V3 V1 V3 M M VEE VEE VEE M V1 V3 V4 VEE (LC7940YD) LC7941YD V4 V4 V4
Application Notes
V1
V3
CP SDI LOAD M V1 V3 M V1 V3 M V1 V3
CP SDI LOAD
CP SDI LOAD
OD1
ED1
FLM
controller 640 639 482 481 480 479 322 321 320 319 162 161 160 159
M
M
DI01
2
LC7942YD
CL1
CP
064
DI064 100
CL2
V1 V2 V5 VEE
OD2
4
LCD panel (640 x 200 pixels)
ED2
M 962 961 960 959 1280 1279 1122 1121 1120 1119
DI01
01 802 801 800 799 642 641
LC7940YD, LC7941YD
LC7942YD
VDD
CP
036
V1 LC7940YD LC7940YD
LA5311M
V1 V2 V5 VEE
LC7940YD
LC7940YD
R (LC7941YD) M LC7941YD V1 V3 V4 VEE 4 V1 V3 V4 VEE M LC7941YD V1 V3 V4 VEE (LC7941YD)
- +
V2 (LC7941YD) M LC7941YD V1 V3 V4 VEE M LC7941YD V1 V3 V4 VEE (LC7941YD)
6
4
R
- +
V3 CP SDI LOAD
7R
- +
V4
4
R
- +
V5
1
01
R
4 M LOAD CP OD2 ED2
VEE
No. 6158--7/11
-11 to -13V
LCD Panel 2
4
2 M V1 V3 V4 VEE CP LOAD 4bit Data CDO LC7941YD-#8 LC7941YD-#2 080 LC7941YD-#1 01 CDI
4
2
4
2
4
2
4
4bit Data
FLM 01
controller
M
M
DI01
LOAD
CP 064 LC7942YD-#1 100
CP
4bit Data 100 01
LCD panel (640 x 200 pixels)
LC7940YD, LC7941YD
M
DI01
VDD
CP 036 LC7942YD-#1
V1
LA5311M
V1 V2 V5 VEE
R
- +
V2 CDO 080 01 CDI 4bit Data CP LOAD LC7941YD-#8 V1 V3 V4 VEE 4 2 4 2 4 LC7941YD-#2 2 4 M LC7941YD-#1 V1 V3 V4 VEE 2 4 4
6
4
R
- +
V3
7R
- +
V4
4
R
- +
V5
R
VEE
No. 6158--8/11
-11 to -13V
4
LC7940YD, LC7941YD
100 x 240-pixel LCD Panel Application
A 100 x 240-pixel LCD panel requires the following drivers. * 3 x LC7940YD (or LC7941YD) drivers * 2 x LC7942YD drivers An example using l/l00 duty cycle is shown below.
1,79 Frame signel DI01 01 RS/LS 02 LC7942YD #1 CP M 063 1,1 2,1 1,2 2,2 1,79 1,80 1,81
(m,n) : pixel address Segment line (n) Common line (m)
---
1,82
---
1,160
1,161
---
1,240 2,240
LCD panel (100 x 240 pixels)
----64,80 65,80 64,81 65,81
63,1 64,1 65,1 66,1
---
63,2 64,2 65,2 66,2
---
---
---
DI064 064 DI01 01 RS/LS 02 LC7942YD #2 CP M 036 O37 to O64 are open.
-----
64,160 64,161 65,160 65,161
-----
64,240 65,240
100,1
---
100,2
----100,79 100,80 100,81 100,82
---
---
---
100,160 100,161
---
100,240
DI064
01
02 LC7940YD (LC7941YD) SDI DI1 DI2 DI3
079
080
01
02
080
01
080 LC7940YD #2 CDO (LC7941YD)
CDI P/S
#1 LOAD CP
CDO
CDI P/S
LC7940YD #2 CDO (LC7941YD) LOAD SDI DI1 DI2 DI3 CP M
CDI
Alternating signal
Data latch clock
Serial data
1. The LC7942YD chips are cascaded by connecting DIO64 on chip I to DIO1 on chip 2. For a 100-bit shift register, 037 to 064 on chip 2 are left open. 2. The LC7940YD (or LC7941YD) chips are cascaded by connecting CDO on chip I to CDI on chip 2, and CDO on chip 2 to CDI on chip 3. CDI on chip I is tied to GND, and CDO on chip 3 is not used. This configuration allows the input of 240-bit serial data.
Data shift clock
P/S DI1 DI2 DI3 SDI CP LOAD M
M
No. 6158--9/11
LC7940YD, LC7941YD
100 x 240-pixel LCD Panel Timing Diagram
M LOAD
CP
SDI
1,1
1,2
---
1,79
1,80
1,81
---
1,160
1,161
---
1,240
#1
SDO
#2
#3
Chip 1 data read 1 line (240 bits)
Chip 2 data read
Chip 3 data read
M LOAD
CP
SDI
1,1
1,2
---
1,239
1,240
2,1
---
2,240
3,1
---
100,240
1st line data read 1 frame (100 x 240 bits) M
2nd line data read
#1 DIO1 LOAD
01
1,1 1,2
2,1 2,2
-----
98,1 98,2
99,1 99,2
100,1 100,2
1,1 1,2
-----
99,1 99,2
100,1 100,2 LCD drive output data
#1
02
080
1,80
2,80
---
98,80
99,80
100,80
1,80
---
99,80
100,80
01 --080 #2
1,81 1,160
2,81 2,160
-----
98,81 98,160
99,81 99,160
100,81 100,160
1,81 1,160
-----
99,81 99,160
100,81 100,160
01 --080 #3
1,161 1,240
2,161 2,240
-----
98,161 98,240
99,161 99,240
100,161 100,240
1,161 1,240
-----
99,161 99,240
100,161 100,240
No. 6158--10/11
LC7940YD, LC7941YD
Segment Data Not Multiples of 4
Example.
LCD panel (100 x 230 pixels)
--01 080 01 080 01
--080
LC7940YD #1
LC7940YD #2
LC7940YD #3
LOAD
SDI
m,1
m,2
---
,228
m,229
m,230
m+1,1
m+1,2
,228 m+1,229 m+1,230
If this timing data is sent, data elements (m, 229), (m, 230), (m+1, 229), (m+1. 230)... will not appear in the output (O69 and O70 on chip 3). This is because the LC7940YD (or LC7941YD) converts serial/parallel data
LOAD
in 4-bit units, which also decreases power dissipation . For data that is not a multiple of 4, like 230, the following scheme is used.
SDI
m,1
m,2
---
,228
m,229
m,230
m,231
m,232
Vaild display data Multiple of 4
Dummy data
In this case, (m, 231) is output on O71 on chip 3, and (m, 232) on O72 on chip 3. However, these outputs are not
connected to the panel and are, therefore, invalid.
s
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co. , Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
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This catalog provides information as of June, 1999. Specifications and information herein are subject to change without notice.
No. 6158--11/11

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