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 DISCRETE SEMICONDUCTORS
DATA SHEET
BSP121 N-channel enhancement mode vertical D-MOS transistor
Product specification Supersedes data of April 1995 File under Discrete Semiconductors, SC13b 1998 Apr 01
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
DESCRIPTION N-channel enhancement mode vertical D-MOS transistor in a miniature SOT223 envelope and designed for use as a line current interrupter in telephone sets and for application in relay, high-speed and line-transformer drivers. FEATURES * Direct interface to C-MOS, TTL, etc. * High-speed switching * No secondary breakdown PINNING - SOT223 1 = gate 2 = drain 3 = source 4 = drain Marking code BSP121 Transfer admittance ID = 400 mA; VDS = 25 V Yfs min. typ. QUICK REFERENCE DATA Drain source voltage Gate-source voltage (open drain) Drain current (DC) Total power dissipation up to Tamb = 25 C Drain-source on-resistance ID = 400 mA; VGS = 10 V RDS(on) typ. max. Ptot max. VDS VGSO ID max. max. max.
BSP121
200 V 20 V 350 mA 1.5 W 4.5 6.0 200 mS 350 mS
PIN CONFIGURATION
handbook, halfpage
4
d
g
1 Top view
2
3
MAM054
s
Fig.1 Simplified outline and symbol.
1998 Apr 01
2
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Drain-source voltage Gate-source voltage (open drain) Drain current (DC) Drain current (peak) Total power dissipation up to Tamb = 25 C (note 1) Storage temperature range Junction temperature THERMAL RESISTANCE From junction to ambient (note 1) Note Rthj-a = Ptot Tstg Tj max. max. VDS VGSO ID IDM max. max. max. max.
BSP121
200 V 20 V 350 mA 1.2 A 1.5 W 150 C
-65 to + 150 C
83.3 K/W
1. Device mounted on an epoxy printed-circuit board 40 mm x 40 mm x 1.5 mm; mounting pad for the drain lead min. 6 cm2.
1998 Apr 01
3
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
CHARACTERISTICS Tj = 25 C unless otherwise specified Drain-source breakdown voltage ID = 10 A; VGS = 0 Drain-source leakage current VDS = 160 V; VGS = 0 VDS = 60 V; VGS = 0 Gate-source leakage current VGS = 20 V; VDS = 0 Gate threshold voltage ID = 1 mA; VDS = VGS Drain-source on-resistance ID = 400 mA; VGS = 10 V Transfer admittance ID = 400 mA; VDS = 25 V Input capacitance at f = 1 MHz VDS = 25 V; VGS = 0 Output capacitance at f = 1 MHz VDS = 25 V; VGS = 0 Feedback capacitance at f = 1 MHz VDS = 25 V; VGS = 0 Switching times (see Figs 2 and 3) ID = 250 mA; VDD = 50 V; VGS = 0 to 10 V ton typ. max. typ. max. Crss typ. max. Coss typ. max. Ciss typ. max. Yfs min. typ. RDS(on) typ. max. VGS(th) min. max. IGSS max. IDSS IDSS max. max. V(BR)DSS min.
BSP121
200 V 1.0 A 200 nA 100 nA 0.8 V 2.8 V 4.5 6.0 200 mS 350 mS
45 pF 60 pF
15 pF 25 pF
3.5 pF 10 pF
5 pF 10 pF 15 ns 20 ns
toff
1998 Apr 01
4
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
BSP121
handbook, halfpage handbook, halfpage
VDD = 50 V
90 %
INPUT 10 %
90 % 10 V 0V ID 50
MBB691
OUTPUT 10 % ton toff
MBB692
Fig.2 Switching time test circuit
Fig.3 Input and output waveforms.
handbook,
2
MBB693
Ptot (W) 1.6
handbook, halfpage
2
MDA745
ID (A) 1.6
VGS = 10 V 6V
1.2
1.2 5V
0.8
0.8 4V
0.4
0.4 3V
0 0 50 100 150 200 Tamb (C)
0 0 5 10 15 20 25 VDS (V)
Fig.4 Power derating curve.
Fig.5
Output characteristic; Tj = 25 C; typical value.
1998 Apr 01
5
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
BSP121
handbook, halfpage
1.6
MDA746
handbook, halfpage
160
MDA747
ID (A) 1.2
C (pF) 120
0.8
80
Ciss 0.4 40 Coss Crss 0 0 2 4 6 8 10 VGS (V) 0 0 5 10 15 20 25 VDS (V)
Fig.6
Transfer characteristic; VDS = 10 V; Tj = 25 C; typical values.
Fig.7
Capacitance as a function of drain-source voltage; VGS = 0; f = 1 MHz; Tj = 25 C; typical values.
104 handbook, halfpage ID (mA) 103 VGS = 10 V
MDA748
handbook, halfpage
1.4 k 1.2
MDA749
5V 4V 1
102 0.8
10
4
6
8
10
12 14 RDSon ()
0.6 -50
0
50
100
Tj (C)
150
Fig.9 V GS ( th ) at T j k = -------------------------------------------- ; V GS ( th ) at 25 C Fig.8 Tj = 25 C; typical values. VGS(th) at 1 mA; typical values.
1998 Apr 01
6
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
BSP121
handbook, halfpage
2.8 k 2.4
MDA750
2
1.6
1.2
0.8
0.4 -50
0
50
100
Tj (C)
150
Fig.10 R DS ( on ) at T j k = ---------------------------------------------- ; R DS ( on ) at 25 C at 400 mA/10 V; typical values.
1998 Apr 01
7
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
PACKAGE OUTLINE Plastic surface mounted package; collector pad for good heat transfer; 4 leads
BSP121
SOT223
D
B
E
A
X
c y HE b1 vMA
4
Q A A1
1
e1 e
2
bp
3
wM B detail X
Lp
0
2 scale
4 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.8 1.5 A1 0.10 0.01 bp 0.80 0.60 b1 3.1 2.9 c 0.32 0.22 D 6.7 6.3 E 3.7 3.3 e 4.6 e1 2.3 HE 7.3 6.7 Lp 1.1 0.7 Q 0.95 0.85 v 0.2 w 0.1 y 0.1
OUTLINE VERSION SOT223
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 96-11-11 97-02-28
1998 Apr 01
8
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS
BSP121
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1998 Apr 01
9
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
NOTES
BSP121
1998 Apr 01
10
Philips Semiconductors
Product specification
N-channel enhancement mode vertical D-MOS transistor
NOTES
BSP121
1998 Apr 01
11
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA59
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
135108/00/03/pp12
Date of release: 1998 Apr 01
Document order number:
9397 750 03676


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