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| Ordering number : ENN*6714 CMOS IC LC875064B/56B/48B 8-Bit Single Chip Microcontroller with 64/56/48K-Byte EPROM and 2048-Byte RAM On Chip Preliminary Overview The LC875064B/56B/48B microcontroller is 8-bit single chip microcontroller with the following on-chip functional blocks: - CPU: Operable at a minimum bus cycle time of 100ns - 64K/56K/48K bytes ROM - 2048 byte RAM - two high performance 16 bit timer/counters (can be divided into 8 bit units) - two 8 bit timers with prescalers - timer for use as date/time clock - one synchronous serial I/O ports (with automatic block transmit/receive function) - one asynchronous/synchronous serial I/O port - 12-bit PWM x 2 - 3-channel x 8-bit AD converter - high speed 8-bit parallel interface - 16-source 10-vectored interrupt system All of the above functions are fabricated on a single chip. Features (1) Read Only Memory (ROM) - 65535 x 8 bits (LC875064B) - 57343 x 8 bits (LC875056B) - 49151 x 8 bits (LC875048B) Ver.1.03 12500 91400 RM (IM) HK / SY No.6714-1/26 LC875064B/56B/48B (2) Random Access Memory (RAM) - 2048 x 8 bits (LC875064B/56B/48B) (3) Bus Cycle Time - 100ns (10MHz) Note: The bus cycle time indicates ROM read time. (4) Minimum Instruction Cycle Time : 300ns (10MHz) (5) Ports - Input/output ports Each bit data direction programmable Nibble data direction programmable - Input ports - PWM Output ports - Oscillator pins - Reset pin - Power supply 51 (P1n, P2n, P70 to P73, P80 to P82, PA2 to PA5, PBn, PCn) 8 (P0n) 2 (XT1,XT2) 2 (PWM0,PWM1) 2 (CF1,CF2) 1 ( RES ) 6 (VSS1 to 3,VDD1 to 3) (6) Timers - Timer0: 16 bit timer/counter with capture register Mode 0: 2 channel 8 bit timer with programmable 8 bit prescaler and 8 bit capture register Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with 8 bit capture register Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register Mode 3: 16 bit counter with 16 bit capture register - Timer1: PWM/16 bit timer/counter (with toggle output) Mode 0: 8 bit timer (with toggle output) + 8 bit timer counter (with toggle output) Mode 1: 2 channel 8 bit PWM Mode 2: 16 bit timer/counter (with toggle output) Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM output. - Base timer 1. The clock signal can be selected from any of the following: sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output for timer 0. 2. Interrupts can be selected to occur at one of five different times. (7) SIO - SIO0: 8 bit synchronous serial interface 1. LSB first/MSB first function available 2. Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 TCYC) 3. Continuous automatic data communications (1 - 256 bits) - SIO1: 8 bit asynchronous/synchronous serial interface Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 - 512 T CYC) Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 - 2048 TCYC) Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 - 512 TCYC) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection) (8) AD converter - 8-bits x 3-channels (9) PWM - 2 channel synchronous variable 12 bit PWM (10) Parallel interface - RS, RD , WR , CS0 - CS2 Outputs (reversible polarity) - read/write possible in 1 TCYC No.6714-2/26 LC875064B/56B/48B (11) Remote control receiver circuit (connected to P73/INT3/T0IN terminal) - Noise rejection function (noise rejection filter time constant can selected from 1/32/128 TCYC) (12) Watchdog timer - The watchdog timer period set by external RC. - Watchdog timer can be set to produce interrupt, system reset (13) Interrupts - 16-source, 10-vectored interrupts: 1. Three level (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower level interrupt request is refused. 2. If interrupt requests to two or more vector addresses occur at once, the higher level interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence. No. Vector Selectable Level Interrupt signal 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/INT5/Base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0 8 0003BH H or L SIO1 9 00043H H or L ADC 10 0004BH H or L Port 0/PWM0, 1 * Priority Level: X > H > L * For equal priority levels, vector with lowest address takes precedence. (14) Subroutine stack levels - 1024 levels max. Stack is located in RAM (15) Multiplication and division - 16 bit x 8 bit (executed in 5 cycles) - 24 bit x 16 bit (12 cycles ) - 16 bit / 8 bit (8 cycles) - 24 bit / 16 bit (12 cycles) (16) Oscillation circuits - On-chip RC oscillation circuit used for system clock - On-chip CF oscillation circuit used for system clock - On-chip Crystal oscillation circuit used for system clock and time-base clock (17) Standby function - HALT mode HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits still operate. 1. Oscillation circuits are not stopped automatically 2. Release on system reset - HOLD mode HOLD mode is used to reduce the power dissipation. Both program execution and peripheral circuits are stopped. 1. CF, RC and crystal oscillation circuits stop automatically 2. Release occurs on any of the following conditions *input to the reset pin goes low *a specified level is input to at least one of INT0, INT1, INT2, INT4, INT5 *an interrupt condition arises at port 0 No.6714-3/26 LC875064B/56B/48B - X'tal HOLD mode X'tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base timer are stopped. 1. CF and RC oscillation circuits stop automatically 2. Crystal oscillator is maintained in its state at HOLD mode inception. 3. Release occurs on any of the following conditions *input to the reset pin goes low *a specified level is input to at least one of INT0, INT1, INT2, INT4, INT5 *an interrupt condition arises at port 0 *an interrupt condition arises at the base-timer (18) Factory shipment - delivery form QIP64E - delivery form DIP64S (19) Development Tools - Evaluation chip - Emulator : LC876098 : EVA87000 + ECB875000 (Evaluation chip board) + POD875000 (POD) No.6714-4/26 LC875064B/56B/48B Pin Assignment PA2/CS0# PA3/WR# PA4/RD# PA5/RS PB0/D0 PB1/D1 32 31 30 29 28 27 26 PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 VDD3 VSS3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P70/INT0/T0LCP P71/INT1/T0HCP P72/INT2/T0IN P73/INT3/T0IN RES# XT1 XT2 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P10/SO0 P11/SI0/SB0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 P12/SCK0 2 P13/SO1 3 P14/SI1/SB1 4 P15/SCK1 5 P16/T1PWML 6 P17/T1PWMH/BUZ 7 PWM1 8 PWM0 9 10 11 12 13 14 15 16 P00 P01 P02 P03 P04 VDD2 VSS2 P05 PB2/D2 PB3/D3 PB4/D4 PB5/D5 PB6/D6 PB7/D7 P27/INT5/T1IN P26/INT5/T1IN P25/INT5/T1IN P24/INT5/T1IN P23/INT4/T1IN P22/INT4/T1IN P21/INT4/T1IN P20/INT4/T1IN P07 P06 LC875064B/56B/48B QIP 25 24 23 22 21 20 19 18 17 Package Dimension (unit : mm) 3159 SANYO : QIP-64E No.6714-5/26 LC875064B/56B/48B QIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ PWM1 PWM0 VDD2 VSS2 P00 P01 P02 P03 P04 P05 P06 P07 P20/INT4/T1IN P21/INT4/T1IN P22/INT4/T1IN P23/INT4/T1IN P24/INT5/T1IN P25/INT5/T1IN P26/INT5/T1IN P27/INT5/T1IN PB7/D7 PB6/D6 PB5/D5 PB4/D4 PB3/D3 PB2/D2 QIP 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME PB1/D1 PB0/D0 VSS3 VDD3 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PA2/CS0# PA3/WR# PA4/RD# PA5/RS P70/INT0/T0LCP P71/INT1/T0HCP P72/INT2/T0IN P73/INT3/T0IN RES# XT1 XT2 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P10/SO0 P11/SI0/SB0 No.6714-6/26 LC875064B/56B/48B System Block Diagram Interrupt control IR PLA ROM Standby control Clock Generator CF RC Xtal PC SIO0 Bus Interface ACC SIO1 Port 0 B Register Port 1 C Register Timer 0 ALU Timer 1 Port 7 Port 8 PSW ADC RAR PWM0 INT0-3 Noise Rejection Filter Port 2 INT4,,5 Stack Pointer Base Timer Parallel interface Port A Port B Port C RAM PWM1 Watch Dog Timer No.6714-7/26 LC875064B/56B/48B Pin Assignment Pin Name VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Port 0 P00 - P07 I/O Negative power supply Pin Function Option No - Positive power supply No I/O Port 1 P10 - P17 I/O Port 2 P20 - P27 I/O *8-bit Input/output port *Data direction can be specified in nibble units *Use of pull-up resistor can be specified in nibble units *HOLD-release input *Input for port 0 interrupt *8-bit Input/output port *Data direction can be specified for each bit *Use of pull-up resistor can be specified for each bit *Other functions P10: SIO0 data output P11: SIO0 data input/bus input/output P12: SIO0 clock input/output P13: SIO1 data output P14: SIO1 data input/bus input/output P15: SIO1 clock input/output P16: Timer 1 PWML output P17: Timer 1 PWMH output/Buzzer output *8-bit Input/output port *Data direction can be specified for each bit *Use of pull-up resistor can be specified for each bit *Other functions P20-P23: INT4 input/HOLD release input/timer 1 event input /Timer 0L capture input/Timer 0H capture input P24-P27: INT5 input/HOLD release input/timer 1 event input /Timer 0L capture input /Timer 0H capture input Interrupt receiver format Rising Falling Rising/ H level falling INT4 Yes Yes Yes No INT5 Yes Yes Yes No Yes Yes Yes L level No No (Continued) No.6714-8/26 LC875064B/56B/48B Name Port 7 P70 - P73 I/O I/O Function description *4-bit Input/output port *Data direction can be specified for each bit *Use of pull-up resistor can be specified for each bit *Other functions P70: INT0 input/HOLD release input/Timer0L capture input /Output for watchdog timer P71: INT1 input/HOLD release input/Timer0H capture input P72: INT2 input/HOLD release input/timer 0 event input /Timer0L capture input P73: INT3 input(noise rejection filter attached input) /timer 0 event input/Timer0H capture input Interrupt receiver format Rising Falling Rising/ H level falling Yes No Yes Yes INT0 Yes No Yes Yes INT1 No Yes Yes Yes INT2 No Yes Yes Yes INT3 *3-bit Input/output port *Data direction can be specified for each bit *Other functions P80-P82: AD input port *4-bit Input/output port *Data direction can be specified for each bit *Use of pull-up resistor can be specified for each bit *Other functions PA2: Parallel interface output CS0 PA3: Parallel interface output WR PA4: Parallel interface output RD PA5: Parallel interface output RS *8-bit Input/output port *Data direction can be specified for each bit *Use of pull-up resistor can be specified for each bit *Other functions PB0-PB7: Parallel interface data input/output; address output *8-bit Input/output port *Data direction can be specified for each bit *Use of pull-up resistor can be specified for each bit *Other functions PC0-PC7: Parallel interface address output PWM0 output port PWM1 output port Reset terminal *Input for 32.768kHz crystal oscillation *Other function Input port When not in use, connect to VDD1. *Output for 32.768kHz crystal oscillation *Other function General purpose input port When not in use, set to oscillation mode and leave open circuit Input terminal for ceramic oscillator Output terminal for ceramic oscillator Option No L level Yes Yes No No No Port 8 P80 - P82 I/O Port A PA2 - PA5 I/O Yes Port B PB0 - PB7 I/O Yes Port C PC0 - PC7 I/O Yes PWM0 PWM1 RES O O I I No No No No XT1 XT2 I/O No CF1 CF2 I O No No No.6714-9/26 LC875064B/56B/48B Port Output Configuration Output configuration and pull-up resistor options are shown in the following table. Input is possible even when port is set to output mode. Terminal P00-P07 P10-P17 P20-P27 PA2-PA5 PB0-PB7(*) PC0-PC7 P70 P71-P73 P80-P82 PWM0, PWM1 XT1 XT2 Option applies to: 1 bit units each bit each bit Option 1 2 1 2 1 2 None None None None None None CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS Nch-open drain CMOS Input only Output for 32.768kHz crystal oscillation Output Format Pull-up resistor Programmable (Note 1) None Programmable Programmable Programmable Programmable Programmable Programmable None None None None - Note 1 Programmable pull-up resisters of Port 0 can be attatched in nibble units (P00-03, P04-07). (*) When in parallel interface mode, PB0-PB7 output format is CMOS, regardless of any selected option. Note: Connect as follows to reduce noise on VDD and increase the back-up time. VSS1, VSS2 and VSS3 must be connected together and grounded. Example 1 : In hold mode, during backup, port output `H' level is supplied from the back-up capacitor. LSI Power Supply Back-up capacitor VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 Example 2 : During backup in hold mode output is not held high and its value in unsettled. LSI Power Supply Back-up capacitor VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 No.6714-10/26 LC875064B/56B/48B 1. Absolute Maximum Ratings at Ta=25C, VSS1=VSS2=VSS3=0V Parameter Supply voltage Input voltage Output voltage Input/output voltage Symbol VDDMAX VI(1) VO(1) VIO(1) Pins VDD1, VDD2, VDD3 XT1, XT2, CF1 PWM0, PWM1 Ports 0, 1, 2 Ports 7, 8 Ports A, B, C PWM0, PWM1 Ports 0, 1, 2 Ports A, B, C PWM0, PWM1 Port 7 Port 7 Port 8 Port 1 PWM0, PWM1 Port 0 Ports 2, B Ports A, C P02-P07 Ports 1, 2 Ports A, B, C PWM0, PWM1 P00, P01 Ports 7, 8 Port 7 Port 8 Port 1 PWM0, PWM1 Port 0 Ports 2, B Ports A, C QFP64E Conditions VDD1=VDD2 =VDD3 Ratings typ. unit V VDD[V] min. -0.3 -0.3 -0.3 -0.3 max. +7.0 VDD+0.3 VDD+0.3 VDD+0.3 High level output current Peak output current Total output current IOPH(1) *CMOS output *For each pin. For each pin. The total of all pins. The total of all pins. The total of all pins. The total of all pins. The total of all pins. The total of all pins. For each pin. -10 mA IOPH(2) IOAH(1) IOAH(2) IOAH(3) IOAH(4) IOAH(5) IOAH(6) IOPL(1) -5 -5 -5 -20 -20 -20 -20 20 Low level output current Peak output current Total output current IOPL(2) IOPL(3) IOAL(1) IOAL(2) IOAL(3) IOAL(4) IOAL(5) IOAL(6) Pdmax Topg For each pin. For each pin. The total of all pins. The total of all pins. The total of all pins. The total of all pins. The total of all pins. The total of all pins. Ta=-30 to +70C -20 30 15 5 5 40 70 40 40 430 70 Maximun power dissipation Operating temperature range Storage temperature range mW C Tstg -65 150 No.6714-11/26 LC875064B/56B/48B 2. Recommended Operating Range at Ta=-20C to +70C, VSS1=VSS2=VSS3=0V Parameter Operating supply voltage range HOLD voltage Symbol VDD(1) Pins VDD1=VDD2 =VDD3 Conditions 0.294s tCYC 200s 0.588s tCYC 200s RAM and the register data are kept in HOLD mode. 2.5 - 6.0 Ratings typ. unit V VDD[V] min. 4.5 2.5 2.0 max. 6.0 6.0 6.0 VHD VDD1=VDD2 =VDD3 *Ports 1, 2 *P71-P73 *P70 port input /interrupt *Ports 0, 8 *Ports A, B, C Port 70 Watchdog timer input XT1, XT2, CF1, RES *Ports 1, 2 *P71-P73 *P70 port input /interrupt *Ports 0, 8 *Ports A, B, C Port 70 Watchdog timer input XT1, XT2, CF1, RES Input high voltage VIH(1) 0.3VDD +0.7 VDD VIH(2) VIH(3) VIH(4) Input low voltage VIL(1) 2.5 - 6.0 0.3VDD +0.7 VDD VDD VDD 0.1VDD +0.4 2.5 - 6.0 0.9VDD 2.5 - 6.0 0.75VDD 2.5 - 6.0 VSS VIL(2) VIL(5) VIL(6) Operation cycle time External system clock frequency tCYC FEXCF(1) 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 VSS VSS VSS 0.294 0.588 0.1 0.1 0.2 0.1 0.15VDD +0.4 0.8VDD -1.0 0.25VDD CF1 *CF2 open circuit *system clock divider set to 1/1 *external clock DUTY=505% *CF2 open circuit *system clock divider set to 1/2 200 200 10 5 20.4 10 s MHz (Note 1) The oscillation constant is shown in Tables 1 and 2. No.6714-12/26 LC875064B/56B/48B 3. Electrical Characteristics at Ta=-20C to +70C, VSS1=VSS2=VSS3=0V Parameter Input high current Symbol IIH(1) Pins *Ports 0, 1, 2 *Ports 7, 8 *Ports A, B, C * RES *PWM0, PWM1 XT1, XT2 Conditions *Output disable *Pull-up resistor off *VIN=VDD (including off state leak current of output Tr.) When specified as an input port. VIN=VDD VIN=VDD *Output disable *Pull-up resistor off *VIN=VSS (including off state leak current of output Tr.) When specified as an input port VIN=VSS VIN=VSS IOH=-1.0mA IOH=-0.1mA IOH=-5.0mA IOH=-0.4mA IOH=-0.4mA Ratings typ. unit A VDD[V] 2.5 - 6.0 min. max. 1 IIH(2) 2.5 - 6.0 1 IIH(3) Input low current IIL(1) CF1 *Ports 0, 1, 2 *Ports 7, 8 *Ports A, B, C * RES *PWM0, PWM1 XT1, XT2 2.5 - 6.0 2.5 - 6.0 -1 15 IIL(2) 2.5 - 6.0 -1 IIL(3) Output high current VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) CF1 *Ports 0, 1, 2 *Ports B, C *PWM0, PWM1 Port A Port 7 2.5 - 6.0 -15 V 4.5 - 6.0 VDD-1 2.5 - 6.0 VDD-0.5 4.5 - 6.0 VDD-1 2.5 - 6.0 VDD-0.5 2.5 - 6.0 VDD-1 (Continued) No.6714-13/26 LC875064B/56B/48B Parameter Output low current Symbol VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) Port A Pins *Ports 0, 1, 2 *Ports B, C *PWM0, PWM1 Conditions IOL=10mA IOL=1.6mA IOL=1.0mA VDD[V] 4.5 - 6.0 2.5 - 6.0 2.5 - 6.0 4.5 - 6.0 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 2.5 - 6.0 min. Ratings typ. max. 1.5 0.4 0.3 1.5 0.4 0.3 1.5 0.4 unit V P00, P01 Ports 7, 8 IOL=30mA IOL=1mA IOL=0.5mA IOL=15mA IOL=2mA Pull-up resistor Rpu *Ports 0, 1, 2 *Port 7 *Ports A, B, C *Ports 1, 2 *Port 7 * RES All pins VOH=0.9VDD 15 40 70 k Hysteresis voltage Pin capacitance VHIS 2.5 - 6.0 0.1VDD V CP *Every other terminal connected to VSS. *f=1MHz *Ta=25C 2.5 - 6.0 10 pF No.6714-14/26 LC875064B/56B/48B 4. Serial Input/Output Characteristics at Ta=-20C to +70C, VSS1=VSS2=VSS3=0V Parameter Cycle Low level pulse width Input clock Symbol tSCK(1) tSCKL(1) tSCKLA(1) High level pulse width Cycle Low level pulse width High level pulse width Cycle Low level pulse width Output clock tSCKH(1) tSCKHA(1) tSCK(2) tSCKL(2) tSCKH(2) tSCK(3) tSCKL(3) tSCKLA(2) High level pulse width tSCKH(3) tSCKHA(2) Cycle Low level pulse width High level pulse width Data set-up time Data hold time Output delay time tSCK(4) tSCKL(4) tSCKH(4) tsDI SB0(P11), SB1(P14), SI0, SI1 *Data set-up to SI0CLK *Refer to figure 6 4.5 - 6.0 2.5 - 6.0 4.5 - 6.0 2.5 - 6.0 tdD0 SO0(P10), SO1(P13), SB0(O11), SB1(P14) *Data set-up to SI0CLK *When port is open drain: Time delay from SI0CLK trailing edge to the SO data change. *Refer to figure 6 4.5 - 6.0 0.03 0.03 0.03 0.03 1/3tCYC +0.05 1/3tCYC +0.05 Pins SCK0(P12) Conditions Refer to figure 6 VDD[V] 2.5 - 6.0 min. 2 1 1 1 3(SIO0) 2 1 1 Ratings typ. max. unit tCYC SCK1(P15) Refer to figure 6 2.5 - 6.0 Serial clock SCK0(P12) *Use pull-up resistor (1k) when output is open drain. *Refer to figure 6 SCK0(P12) SIO0 2.5 - 6.0 4/3 1/2 3/4 1/2 tSCK SCK1(P15) SCK0(P12) SIO0 *CMOS output option *Refer to figure 6 2 2.5 - 6.0 2 1/2 1/2 s tCYC tSCK Serial input thDI Serial output 2.5 - 6.0 No.6714-15/26 LC875064B/56B/48B 5. Parallel Input/Output Characteristics at Ta=-20C to +70C, VSS1=VSS2=VSS3=0V Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. Please refer to figures 8 and 9 for parallel output timing waveforms. Parameter Write cycle, Read cycle Address set-up time Symbol tC(1) tsA(1) tsA(2) Address hold time thA(1) thA(2) RS set-up tie tsRS(1) * WR (PA3), PB0-PB7 * RD (PA4), PC0-PC7 RD (PA4), PC0-PC7 RD (PA4), PC0-PC7 WR (PA3), PC0-PC7 WR (PA3), RS(PA5), Pins Conditions VDD[V] 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 min. Ratings typ. 1 max. unit tCYC tCYC & ns From address set-up until control signal changes 1/3tCYC -30ns 2/3tCYC -30ns 1/6tCYC 5 1/6tCYC -15ns 1/6tCYC -15ns 1/3tCYC -15ns 1/3tCYC -15ns 2/3tCYC -15ns 0 1/6tCYC 0 1/6tCYC 0 1/6tCYC -5ns 2/3tCYC -5ns 1/6tCYC -5ns 1/3tCYC -5ns 1/6 tCYC 2/3 tCYC 1/6 tCYC 1/3 tCYC From change of RD until address change From change of WR until address change From change of RS, CS until change in WR from change of RS until change in RD ns tCYC & ns CS (PAX) tsRS(2) tsRS(3) CS set-up time RD (PA4), RS(PA5) RD (PA4), RS(PA5) RD (PA4), CS (PAX) WR (PA3), CS (PAX) WR (PA3), RS(PA5) 2.5 - 6.0 2.5 - 6.0 tsCS(1) tsCS(2) From change in CS until change in RD From change in CS until change in WR From change in WR until change in RS From change in RD until change in RS, CS 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 RS hold time thRS(1) thRS(2) thRS(3) thCS(1) thCS(2) tWRH(1) tWRH(2) tWRL(1) tWRL(2) ns tCYC & ns ns tCYC & ns ns tCYC & ns RD (PA4), RS(PA5), CS (PAX) RD (PA4), RS(PA5), CS (PAX) RD (PA4), RS(PA5) WR (PA3), RS(PA5) CS hold time From change in RD until change in CS From change in WR until change in CS WR 'H' pulse width WR (PA3) WR (PA3) WR (PA3) WR (PA3) WR 'L' pulse width (Continued) No.6714-16/26 LC875064B/56B/48B Parameter RD 'H' pulse width Symbol tRDH(1) tRDH(2) Pins RD (PA4) RD (PA4) RD (PA4) RD (PA4) RD (PA4), PB0-PB7 RD (PA4), PB0-PB7 Conditions VDD[V] 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 RD 'L' pulse width Data write permission delay tRDL(1) tRDL(2) tdDT(1) tdDT(2) min. 1/6tCYC -5ns 1/3tCYC -5ns 1/3tCYC -5ns 1/2tCYC -5ns Ratings typ. 1/6 tCYC 1/3 tCYC 1/3 tCYC 1/2 tCYC max. unit tCYC & ns Input data set-up time tsDTR(1) RD (PA4), PB0-PB7 Time for permission, from RD leading edge until input data set-up (Note 1) From input data setup to RD leading edge. (Note 2) From RD leading edge until input data hold From output data setup until WR leading edge From WR leading edge until output data hold 2.5 - 6.0 2.5 - 6.0 1/6tCYC -15ns 1/3tCYC -15ns 40 ns 2.5 - 6.0 Input data hold time Output data set-up time Output data set-up time Output data hold time thDTR(1) RD (PA4), PB0-PB7 2.5 - 6.0 0 ns tsDTW(1) tsDTW(2) thDTW(1) thDTW(2) RD (PA4), PB0-PB7 RD (PA4), PB0-PB7 RD (PA4), PB0-PB7 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 2.5 - 6.0 1/3tCYC -30ns 1/3tCYC -30ns 0 0 tCYC & ns ns Note 1 : Time until incorrect data of Low is disappeared. Note 2 : Incorrect data of Low is not output in the period between tRDL(1) - tdDT(1). 6. Pulse Input Conditions at Ta=-20C to +70C, VSS1=VSS2=VSS3=0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pins INT0(P70), INT1(P71), INT2(P72) INT4(P20-P23) INT5(P24-P27) INT3(P73) (The noise rejection clock select to 1/1.) INT3(P73) (The noise rejection clock select to 1/32.) INT3(P73) (The noise rejection clock select to 1/128.) RES Conditions *Interrupt acceptable *Events to timer 0 and 1 can be input. *Interrupt acceptable *Events to timer 0 can be input. *Interrupt acceptable *Events to timer 0 can be input. *Interrupt acceptable *Events to timer 0 can be input. Reset acceptable VDD[V] 2.5 - 6.0 min. 1 Ratings typ. max. unit tCYC tPIH(2) tPIL(2) 2.5 - 6.0 2 tPIH(3) tPIL(3) 2.5 - 6.0 64 tPIH(4) tPIL(4) 2.5 - 6.0 256 tPIL(5) 2.5 - 6.0 200 s No.6714-17/26 LC875064B/56B/48B 7. AD Converter Characteristics at Ta=-20C to +70C, VSS1=VSS2=VSS3=0V Parameter Resolution Absolute precision Conversion time Symbol N ET TCAD Pins AN0(P80) - AN2(P82) Conditions Ratings typ. 8 unit bit LSB s (Note 2) AD conversion time =32 x tCYC (ADCR2=0) (Note 3) AD conversion time =64 x tCYC (ADCR2=1) (Note 3) VDD[V] 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 min. max. 1.5 15.10 (tCYC= 0.588s) 97.92 (tCYC= 3.06s) 4.5 - 5.5 15.10 (tCYC= 0.294s) 97.92 (tCYC= 1.53s) Analog input voltage range Analog port input current VAIN IAINH IAINL VAIN=VDD VAIN=VSS 4.5 - 5.5 4.5 - 5.5 4.5 - 5.5 VSS VDD 1 V A -1 (Note 2) Absolute precision not including quantizing error (1/2 LSB). (Note 3) Conversion time means time from executing AD conversion instruction to loading complete digital value to register. No.6714-18/26 LC875064B/56B/48B 8. Current Dissipation Characteristics atTa=-20C to +70C, VSS1=VSS2=VSS3=0V Parameter Current flow during basic operation (Note 4) Symbol IDDOP(1) Pins VDD Conditions *FmCF=10MHz for Ceramic resonator oscillation *FsX'tal=32.768kHz for crystal oscillation *System clock: CF oscillation *Internal RC oscillation stopped. *FmCF=5MHz for Ceramic resonator oscillation *FsX'tal=32.768kHz for crystal oscillation *System clock: CF oscillation *Internal RC oscillation stopped. *FmCF=0Hz (oscillation stops) *FsX'tal=32.768kHz for crystal oscillation *System clock: Internal RC oscillation *FmCF=0Hz (oscillation stops) *FsX'tal=32.768kHz for crystal oscillation *System clock: X'tal oscillation *Internal RC oscillation stopped. Ratings typ. 15 unit mA VDD[V] 4.5 - 6.0 min. max. 27 IDDOP(2) 4.5 - 6.0 6 11 IDDOP(3) 2.5 - 4.5 3 8 IDDOP(4) 4.5 - 6.0 1 2.5 IDDOP(5) 2.5 - 4.5 0.5 2 IDDOP(6) 4.5 - 6.0 35 70 A IDDOP(7) 2.5 - 4.5 15 45 (Continued) No.6714-19/26 LC875064B/56B/48B Parameter Symbol Pins Conditions *HALT mode *FmCF=10MHz for ceramic resonator oscillation *FsX'tal=32.768kHz for crystal oscillation *System clock: CF oscillation *Internal RC oscillation stopped. *HALT mode *FmCF=5MHz for Ceramic resonator oscillation *FsX'tal=32.768kHz for crystal oscillation *System clock: CF oscillation *Internal RC oscillation stopped. *HALT mode *FmCF=0Hz (oscillation stops) *FsX'tal=32.768kHz for crystal oscillation *System clock: Internal RC oscillation *HALT mode *FmCF=0Hz (oscillation stops) *FsX'tal=32.768kHz for crystal oscillation *System clock: X'tal oscillation *Internal RC oscillation stopped. HOLD mode Current flow: IDDHALT(1) VDD HALT mode (Note 4) VDD[V] 4.5 - 6.0 min. Ratings typ. 5 max. 11 unit mA IDDHALT(2) IDDHALT(3) 4.5 - 6.0 2.5 - 4.5 3 1.0 5 2.5 IDDHALT(4) IDDHALT(5) 4.5 - 6.0 2.5 - 4.5 400 250 1300 800 A IDDHALT(6) IDDHALT(7) 4.5 - 6.0 2.5 - 4.5 23 8 60 30 Current flow: IDDHOLD(1) VDD1 HOLD mode IDDHOLD(2) (Note 4) IDDHOLD(2) VDD1 Current flow: Date/time clock HOLD mode 4.5 - 6.0 2.5 - 4.5 4.5 - 6.0 2.5 - 4.5 0.01 0.01 45 6 30 30 100 36 A A Date/time clock HOLD mode *CF1=VDD or open circuit (when using external clock) *FmX'tal=32.768kHz for crystal oscillation (Note 4) The currents of output transistors and pull-up MOS transistors are ignored. No.6714-20/26 LC875064B/56B/48B Main system clock oscillation circuit characteristics The characteristics in the table bellow is based on the following conditions: 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer. Table 1. Main system clock oscillation circuit characteristics using ceramic resonator Circuit Parameters Frequency Manufacturer Murata Kyocera 5MHz Murata Oscillator C1 C2 Rd1 0 0 0 0 0 Operating supply voltage range 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V Oscillation stabilizing time typ 0.05ms 0.05ms 0.05ms 0.05ms 0.05ms 0.05ms 0.05ms 0.05ms max 0.50ms 0.50ms 0.50ms 0.50ms 0.50ms 0.50ms 0.50ms 0.50ms Notes 10MHz CSA10.0MTZ 33pF 33pF CST10.0MTW (30pF) (30pF) KBR-10.0M 33pF 33pF CSA5.00MG 33pF 33pF CST5.00MGW (30pF) (30pF) Built in C1,C2 Built in C1,C2 4MHz Murata Kyocera CSA4.00MG 33pF 33pF 0 CST4.00MGW (30pF) (30pF) 0 KBR-4.0MSA 33pF 33pF 0 Built in C1,C2 *The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (Refer to Figure4) Subsystem clock oscillation circuit characteristics The characteristics in the table bellow is based on the following conditions: 1. Use the standard evaluation board SANYO has provided. 2. Use the peripheral parts with indicated value externally. 3. The peripheral parts value is a recommended value of oscillator manufacturer. Table 2. Subsystem clock oscillation circuit characteristics using crystal oscillator Frequency 32.768kHz Manufacturer Seiko EPSON Oscillator C-002Rx Circuit Parameters Operating supply voltage range C3 C4 Rf Rd2 12pF 15pF OPEN 300k 4.5 - 6.0V Oscillation stabilizing time typ max Notes *The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure4) (Notes) *Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. CF1 CF2 Rd1 XT1 XT2 Rf Rd2 C1 CF C2 C3 X'tal C4 Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit 0.5VDD Figure 3 AC timing measurement point No.6714-21/26 LC875064B/56B/48B VDD Power Supply VDD limit GND Reset time RES# Internal RC Resonator oscillation tmsCF CF1,CF2 tmsXtal XT1,XT2 Operation mode Unfixed Reset Instruction execution mode Reset time and oscillation stable time HOLD release signal Without HOLD Release signal HOLD release signal VALID Internal RC Resonator oscillation tmsCF CF1,CF2 tmsXtal XT1,XT2 Operation mode HOLD HALT HOLD release signal and oscillation stable time Figure 4 Oscillation stabilizing time No.6714-22/26 LC875064B/56B/48B VDD RRES (Note) RES CRES Set CRES, RRES values such that reset time exceeds 200s. Figure 5 Reset circuit SI0CLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 Data RAM transmission period (only SIO0,2) DO8 tSCK tSCKL SI0CLK: tsDI DATAIN: tdDO DATAOUT: Data RAM transmission period (only SIO0,2) tSCKH thDI tSCKLA SI0CLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA Figure 6 Serial input/output test condition tPIL tPIH Figure 7 Pulse input timing condition No.6714-23/26 LC875064B/56B/48B * Parallel Input/Output timing waveform : Indirect Setting, Read Mode tC(1) read cycle ADR/DATA: addr tsA(1) CS#: tsRS(1) RS: tWRH(1) WR#: tRDH(1) RD#: tdDT(1) DATAin: H thDTR(1) data tsDTR(1) tWRL(1) tsRS(2) tRDL(1) thRS(2) thRS(1) Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. * Parallel Input/Output timing waveform : Indirect Setting, Write Mode tC(1) write cycle ADR/DATA: tsA(1) CS#: tsRS(1) RS: tWRH(1) WR#: tWRL(2) RD#: tWRL(1) tsRS(3) tsDTW(1) thRS(1) thRS(3) addr data thDTW(1) DATAin: Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. Figure 8 Indirect mode: Parallel Timing Waveforms No.6714-24/26 LC875064B/56B/48B * Parallel Input/Output timing waveform : Direct Setting, Read Mode tC(1) read cycle ADR: tsA(1) CS#: tsCS(1) DATA: tRDL(2) WR#: tRDH(2) RD#: tdDT(2) DATAin: H thDTR(1) data tsDTR(1) thCS(1) addr thA(1) Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. * Parallel Input/Output timing waveform : Direct Setting, Write Mode tC(1) write cycle ADR: tsA(2) CS#: tsCS(2) DATA: data tsDTW(2) WR#: tWRH(2) RD#: tWRL(2) thDTW(2) thCS(2) addr thA(2) DATAin: Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. Figure 9 Direct Mode: Parallel Input/Output Timing Diagrams No.6714-25/26 LC875064B/56B/48B memo: PS No.6714-26/26 |
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