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| HV6810 10-Channel Serial-Input Latched Display Driver Ordering Information Package Options Device HV6810 18-Pin Plastic DIP HV6810P 20-Pin Small Outline Package HV6810WG 20-Pin Plastic Chip Carrier HV6810PJ Die HV6810X *For Hi-Rel process flow, refer to page 5-3 of the Databook. Features s High output voltage 80V s High speed 5MHz @ 5VDD s Low power IBB 0.1mA (All high) s Active pull down 100A min s Output source current 100mA at 60V VPP s Each device drives 10 lines s High-speed serially-shifted data input s 5V CMOS-compatible inputs s Latches on all driver outputs s Pin-compatible improved replacement for UCN5810A and TL4810A, TL4810B General Description The HV6810 is a monolithic integrated circuit designed to drive a dot matrix or segmented vacuum fluorescent display (VFD). These devices feature a serial data output to cascade additional devices for large displays. A 10-bit data word is serially loaded into the shift register on the positive-going transition of the clock. Parallel data is transferred to the output buffers through a 10-bit D-type latch while the latch enable input is high and is latched when the latch enable is low. When the blanking input is high, all outputs are low. Outputs are structures formed by double-diffused MOS (DMOS) transistors with output voltage ratings of 80 volts and 25 milliampere source-current capability. All inputs are compatible with CMOS levels. Absolute Maximum Ratings1 Logic supply voltage, VDD2 Driver supply voltage, VBB2 Output voltage2 Input voltage2 Continuous total power dissipation at 25C free-air temperature 3 Operating Temperature Range 7.5V 90V 90V -0.3V to VDD + 0.3V 18-Pin P-DIP3 900mW 20-Pin SOIC4 1000mW 20-Pin PLCC4 1000mW -40 to +85*C Notes: 1. Over operating free-air temperature. 2. All voltages are referenced to VSS. 3. For operation above 25C ambient derate linearly to 85C at 15mW/C. 4. For operation above 25C ambient derate linearly to 85C at 16.7mW/C. 12-142 HV6810 Electrical Characteristics DC Characteristics (VDD = 5V 10%, VBB = 60V, VSS = 0, TA = 25C unless otherwise noted) Symbol VOH VOL IOL IO(OFF) IH IDD IBB Parameter High-level output voltage Q outputs Serial output Low-level output voltage Q outputs Serial output Low-level Q output current (pull-down current) Off-state output current High-level input current Supply current from VDD (standby) Supply current from VBB 10 10 0.05 0.05 * All typical values are at TA = 25C, except for IO. 60 Min 57.5 4 Typ 58 4.5 0.15 0.05 80 -1 -15 1 50 50 0.1 0.1 1 0.1 Max Units V V V V A A A A A mA mA Conditions IOH = 25mA VDD = 4.5V, IOH = -100A IOH = 100A, Blanking input at VDD VDD = 4.5V, IOL = 100A TA = Max, VOL = 0.7V VO = 0, Blanking input TA = Max at VDD VI = VDD All inputs at 0V, one Q output high All inputs at 0V, all Q outputs low All outputs low, all Q outputs open All outputs high, all Q outputs open AC Characteristics (Timing requirements over recommended operating conditions) Symbol tW(CKH) tW(LEH) tSU(D) tH(D) tCKH-LEH tpd* Parameter Pulse duration, clock high Pulse duration, latch enable high Setup time, data before clock Hold time, data after clock Delay time, clock to latch enable high Propagation delay time, latch enable to output Min 100 100 50 50 50 0.3 Typ Max Units ns ns ns ns ns s Conditions * Switching characteristics, VBB = 60V, TA = 25C. Recommended Operating Conditions Symbol VDD VBB VSS VIH VIL IOH fCLK TA Supply voltage Supply voltage Supply voltage High-level input voltage (for VDD = 5V) Low-level input voltage Continuous high-level Q output current Clock frequency Operating free-air temperature Plastic -40 3.5 -0.3 -25 5 +85 Parameter Min 4.5 20 0 5.3 0.8 Nom Max 5.5 80 Units V V V V V mA MHz C Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. Power-down sequence should be the reverse of the above. 12-143 HV6810 Input and Output Equivalent Circuits VDD VBB Input Output VSS Input Equivalent Circuit Logic Data Output VSS Timing Diagram Clock Data In VALID IRRELEVANT SR Contents INVALID VALID Latch Enable Latch Contents PREVIOUSLY STORED DATA NEW DATA VALID Blanking Q Outputs VALID 12-144 HV6810 Functional Block Diagram Logic Diagram (positive logic) Blanking Latch Enable Shift Register Data Input Clock 1D C1 R1 Latches C2 2D LC1 Q1 1D C1 R2 C2 2D LC2 Q2 6 Stages (Q3 thru Q8) not shown Q9 * * * * * * 1D C1 R9 * * * C2 2D LC9 * * * 1D C1 R10 C2 2D LC10 Q10 Serial Out Function Table Serial Data Input H L X Clock Input Shift Register Contents I1 I2 I3 ... IN-1 IN Serial Data Output RN-1 RN-1 RN X PN L H R1 R2 R3 ... RN-1 RN P1 P2 P3 ... PN-1 PN X X X ...X L = Low logic level H = High logic level X = Irrelevant P = Present state R = Previous state Strobe Input Latch Contents I1 I2 I3 ... IN-1 IN Blanking Input Output Contents I1 I2 I3 ... IN-1 IN H R1 R2 ... RN-2 RN-1 L R1 R2 ... RN-2 RN-1 R1 R2 R3 ... RN-1 RN X X X ...X X P1 P2 P3 ... PN-1 PN L H P1 P2 P3 ... PN-1 PN L L L ...L L X Switching Waveforms t w(CKH) V IH Clock 50% 50% V IL t su(D) Valid Data 50% 50% V IL t h(D) V IH Output Clock Input 50% Valid t CKH-LEH Latch Enable 50% t pd 90% Valid t w(LEH) 50% V IH V IL V IH V IL Input Timing 12-145 Output Switching Times HV6810 Pin Configurations HV6810 18-Pin DIP Pin Function 1 Q8 2 Q7 3 Q6 4 Clock 5 VSS 6 VDD 7 LE (strobe) 8 Q5 9 Q4 Package Outlines 1 18 17 16 15 14 13 12 11 10 Pin 10 11 12 13 14 15 16 17 18 Function Q3 Q2 Q1 Blanking Data in VBB Serial data out Q10 Q9 2 3 4 5 6 7 8 9 top view 18-pin DIP HV6810 20-Pin SOW Pin Function 1 Q8 2 Q7 3 Q6 4 Clock 5 VSS 6 N/C 7 VDD 8 LE (strobe) 9 Q5 10 Q4 1 20 19 18 17 16 15 14 13 12 11 Pin 11 12 13 14 15 16 17 18 19 20 Function Q3 Q2 Q1 Blanking Data in VBB Serial data out N/C Q10 Q9 2 3 4 5 6 7 8 9 10 top view SOW-20 HV6810 20-Pin Plastic PLCC Pin Function 1 Q8 2 Q7 3 Q6 4 Clock 5 N/C 6 VSS 7 VDD 8 LE(Strobe) 9 Q5 10 Q4 18 17 16 15 14 Pin 11 12 13 14 15 16 17 18 19 20 Function Q3 Q2 Q1 Blanking Data In N/C VBB Serial data out Q10 Q9 19 13 20 12 1 * 11 2 10 3 9 4 5 6 7 8 top view 20-pin PLCC 12-146 |
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