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Description Features
HM5117805 Series
16 M EDO DRAM (2-Mword x 8-bit) 2 k Refresh
E0156H10 (Ver. 1.0) (Previous ADE-203-630D (Z)) Jun. 27, 2001
The HM5117805 is a C MOS dynamic R AM orga nize d 2, 097,152-w ord x 8-bit. It employs the most adva nce d C MOS tec hnology for high per forma nce and low powe r. The HM5117805 off ers Extende d Da ta Out (ED O) P age Mode as a high spee d ac ce ss mode. Multiplexe d addr ess input per mits the HM5117805 to be packaged in standard 28-pin plastic SOJ and 28-pin TSOP.
* Single 5 V (10%) * Access time: 50 ns/60 ns/70 ns (max) * Power dissipation Active mode: 605 mW/550 mW/495 mW (max) Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) * EDO page mode capability * Long refresh period 2048 refresh cycles : 32 ms : 128 ms (L-version) * 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) * Battery backup operation (L-version)
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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HM5117805 Series
Ordering Information
Type No. Access time 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 400-mil 28-pin plastic TSOP II (TTP-28DA) 300-mil 28-pin plastic SOJ (CP-28DNA) Package 400-mil 28-pin plastic SOJ (CP-28DA) HM5117805J-5 HM5117805J-6 HM5117805J-7
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HM5117805LJ-5 HM5117805LJ -6 HM5117805LJ -7 HM5117805S-5 HM5117805S-6 HM5117805S-7 HM5117805LS-5 HM5117805LS-6 HM5117805LS-7 HM5117805TT-5 HM5117805TT-6 HM5117805TT-7 HM5117805LTT-5 HM5117805LTT-6 HM5117805LTT-7 HM5117805TS-5 HM5117805TS-6 HM5117805TS-7 HM5117805LTS-5 HM5117805LTS-6 HM5117805LTS-7 2
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50 ns 60 ns 70 ns 50 ns 60 ns 70 ns
Data Sheet E0156H10
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300-mil 28-pin plastic TSOP II (TTP-28DB)
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HM5117805 Series
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VCC I/O0 I/O1 I/O2 I/O3 WE RAS NC A10 A0 A1 A2 A3 VCC
Pin Arrangement
HM5117805J/LJ Series HM5117805S/LS Series
1 2 3 4 5 6 7 8 9 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS I/O7 I/O6 I/O5 I/O4
HM5117805TT/LTT Series HM5117805TS/LTS Series VCC I/O0 I/O1 I/O2 I/O3 WE RAS NC A10 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top view) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS I/O7 I/O6 I/O5 I/O4 CAS OE A9 A8 A7 A6 A5 A4 VSS
Pin Description
Pin name A0 to A10 Function Address input -- Row/Refresh address A0 to A10 -- Column address A0 to A9 Data input/Data output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground No connection
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CAS OE A9 A8 A7 A6 A5 A4 10 11 12 13 14 VSS
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VCC
(Top view)
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3
I/O0 to I/O7 RAS CAS WE OE VCC VSS NC
Data Sheet E0156H10
HM5117805 Series
Block Diagram
Row decoder
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A0 A1 to A9 * * * * * * A10 4
RAS
CAS
WE
OE
Timing and control
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Column buffers address Row address buffers
Column decoder 2M array 2M array 2M array 2M array 2M array 2M array 2M array 2M array I/O buffers I/O0 to I/O7
Data Sheet E0156H10
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HM5117805 Series
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Parameter Power dissipation Parameter Supply voltage Input high voltage Input low voltage Note:
Absolute Maximum Ratings
Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current
Operating temperature Storage temperature
Recommended DC Operating Conditions (Ta = 0 to +70C)
Symbol Min 4.5 2.4 -1.0 Typ 5.0 -- -- Max 5.5 6.5 0.8 Unit V V V Note 1 1 1 VCC VIH VIL
1. All voltage referred to VSS .
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Data Sheet E0156H10 5
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HM5117805 Series
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)
HM5117805 -5 Symbol
2
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Parameter
1,
-6
-7 Test conditions t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH CAS = VIL Dout = enable t RC = min t HPC = min CMOS interface Dout = High-Z CBR refresh: t RC = 62.5 s t RAS 0.3 s CMOS interface RAS, CAS 0.2V Dout = High-Z 0 V Vin 7 V 0 V Vout 7 V Dout = disable High Iout = -2 mA Low Iout = 2 mA
Min Max Min Max Min Max Unit -- -- 110 -- 2 -- 100 -- 2 -- 90 2 mA mA
Operating current* * Standby current
I CC1 I CC2
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-- I CC2 -- I CC3 I CC5 -- -- I CC6 I CC7 I CC10 -- -- -- I CC11 -- I LI I LO VOH VOL 2.4 0
1
--
1
--
1
mA
Standby current (L-version)
150 --
150 --
150 A
RAS-only refresh current* 2 Standby current*
1
110 -- 5 --
100 -- 5 --
90 5
mA mA
CAS-before-RAS refresh current EDO page mode current* 1, * 3
110 -- 100 -- 500 --
100 -- 90 --
90 85
mA mA
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300 -- -10 10 -10 10 VCC 2.4 0.4 0 0.4
Battery backup current* 4 (Standby with CBR refresh) (L-version)
500 --
500 A
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300 A -10 10 -10 10 A A VCC 0.4 V 0 V
Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage
300 --
-10 10 -10 10
VCC 2.4
Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L ( 0.2 V) while RAS = L ( 0.2 V).
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Data Sheet E0156H10 6
HM5117805 Series
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Parameter
Capacitance (Ta = 25C, VCC = 5 V 10%)
Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2 Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out)
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1, *2, *18
Test Conditions * * * * *
Input rise and fall time: 2 ns Input levels: VIL = 0 V, VIH = 3 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
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Data Sheet E0156H10 7
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HM5117805 Series
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5117805 -5 Symbol t RC t RP t CP t RAS t CAS t ASR Min 84 30 7 50 7 0 7 0 7 11 9 10 35 5 Max -- -- -- -6 Min 104 40 10 Max -- -- -- -7 Min 124 50 13 Max -- -- -- Unit ns ns ns Notes
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Parameter RAS pulse width CAS pulse width RAS hold time CAS hold time 8
Random read or write cycle time RAS precharge time CAS precharge time
Row address setup time Row address hold time
Column address setup time Column address hold time RAS to CAS delay time
RAS to column address delay time t RAD t RSH t CSH
CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall)
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t RAH t ASC t CAH t RCD t CRP t OED t DZO t DZC tT
10000 60 10000 10 -- -- -- -- 37 25 -- -- 0 10 0 10 14 12 13 40 5 15 0 0 2
10000 70 10000 13 -- -- -- -- 45 30 -- -- -- -- -- -- 50 0 10 0 13 14 12 13 45 5 18 0 0 2
10000 ns 10000 ns -- -- -- -- 52 35 -- -- -- -- -- -- 50 ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 7 3 4
Data Sheet E0156H10
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-- 13 0 0 2 -- -- -- 50
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HM5117805 Series
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Read Cycle
Parameter
HM5117805 -5 Symbol t RAC t CAC t AA t OEA t RCS Min -- -- -- -- 0 0 50 0 25 15 0 3 3 Max 50 13 25 13 -- -- -- -- -- -- -- -- -- -6 Min -- -- -- -- 0 0 60 0 30 18 0 3 3 -- -- 15 3 -- -- 15 15 60 Max 60 15 30 15 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- -- -7 Min -- -- -- -- 0 0 70 0 35 23 0 3 3 -- -- 18 3 -- -- 18 18 70 Max 70 18 35 18 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 20 13 5 20 20 20 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9
Access time from RAS Access time from CAS Access time from address Access time from OE
Read command setup time
Read command hold time to CAS Read command hold time to RAS
Read command hold time from RAS t RCHR t RRH Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time
Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time
Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time RAS next CAS delay time
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t RCH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR t OFR t WEZ t WED t RDD t RNCD
Data Sheet E0156H10 9
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-- -- 13 13 -- 13 3 -- -- -- 13 13 -- -- -- 13 13 50
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HM5117805 Series
Write Cycle
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Parameter Data-in setup time Data-in hold time Parameter
HM5117805 -5 Symbol t WCS t WCH t WP t RWL t CWL t DS Min 0 7 7 7 7 0 7 Max -- -- -- -- -- -- -- -6 Min 0 10 10 10 10 0 10 Max -- -- -- -- -- -- -- -7 Min 0 13 10 13 13 0 13 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 15 15 Notes 14
Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time
Read-Modify-Write Cycle
Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE
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t DH Symbol t RWC t RWD t CWD t AWD t OEH Symbol t WRH t RPC
HM5117805 -5 Min Max -6 Min 135 79 34 49 15 Max -- -- -- -- -- -7 Min 161 92 40 57 18 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes
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111 67 30 42 13 -- -- -- -- -- HM5117805 -5 Min 5 7 0 7 5 Max -- -- -- -- --
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-6 -7 Min Max Min 5 -- 5 10 -- 10 0 10 5 -- -- -- 0 10 5
Refresh Cycle
Parameter
Max -- -- --
Unit ns ns ns
Notes
CAS setup time (CBR refresh cycle) t CSR CAS hold time (CBR refresh cycle) t CHR WE setup time (CBR refresh cycle) t WRP WE hold time (CBR refresh cycle) RAS precharge to CAS hold time
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-- ns -- ns
Data Sheet E0156H10 10
HM5117805 Series
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Parameter Parameter
EDO Page Mode Cycle
HM5117805 -5 Symbol t HPC t RASP t CPA Min Max 20 -- -- 28 3 7 5 28 -- -6 Min Max 25 -- -7 Min Max 30 -- Unit ns Notes 19 16 9, 17
EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge
100000 -- 28 -- -- -- -- -- -- 35 3 10 5 35
100000 -- 35 -- -- -- -- -- -- 40 3 13 5 40
100000 ns 40 -- -- -- -- -- ns ns ns ns ns ns
RAS hold time from CAS precharge t CPRH Output data hold time from CAS low t DOH CAS hold time referred OE CAS to OE setup time t COL
Read command hold time from CAS t RCHC precharge
EDO Page Mode Read-Modify-Write Cycle
HM5117805 -5 -6 Min 68 54 Max -- -- -7 Min 79 62 Max Unit ns ns 14 Notes
EDO page mode read- modify-write t HPRWC cycle time WE delay time from CAS precharge t CPW
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t COP Symbol t REF t REF
9, 17
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Min Max 57 45 -- -- 32
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Max Unit ms ms 128
Refresh
Parameter Refresh period Refresh period (L-version) Symbol
Note 2048 cycles 2048 cycles
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Data Sheet E0156H10 11
HM5117805 Series
Self Refresh Mode (L-version)
HM5117805L -5 Symbol t RASS t RPS t CHS Min 100 90 -50 Max -- -- -- -6 Min 100 110 -50 Max -- -- -- -7 Min 100 130 -50 Max -- -- -- Unit s ns ns Notes
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Parameter 12
RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh)
Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the t RCD (max) limit insures that t RAC (max) can be met, t RCD (max) is specified as a reference point only; if t RCD is greater than the specified t RCD (max) limit, then access time is controlled exclusively by t CAC . 4. Operation with the t RAD (max) limit insures that t RAC (max) can be met, t RAD (max) is specified as a reference point only; if t RAD is greater than the specified t RAD (max) limit, then access time is controlled exclusively by t AA . 5. Either t OED or t CDD must be satisfied. 6. Either t DZO or t DZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that t RCD t RCD (max) and t RAD t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD t RCD (max) and t RAD t RAD (max). 11. Assumes that t RCD t RCD (max) and t RAD t RAD (max). 12. Either t RCH or t RRH must be satisfied for a read cycles. 13. t OFF (max) and t OEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS t WCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD t RWD (min), t CWD t CWD (min), and t AWD t AWD (min), or t CWD t CWD (min), t AWD t AWD (min) and t CPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + t CP + 2 t T) becomes greater than the specified t HPC (min) value.The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2).
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Data Sheet E0156H10
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HM5117805 Series
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20. Data output turns off and becomes high impedance from later rising edge of RAS and CAS . Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH and between t OFR and t OFF. 21. Please do not use t RASS timing, 10 s t RASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS 100 s, then RAS precharge time should use t RPS instead of t RP. 22. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycles, 2048 cycles of distributed CBR refresh with 15.6 s interval should be executed within 32 ms immediately after exiting from and before entering into the self refresh mode. 23. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 24. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 25. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL.
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Data Sheet E0156H10 13
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HM5117805 Series
Timing Waveforms*25
Read Cycle
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RAS
t RC t RAS t RP
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t RCD tT t RAD t ASR t RAH Row t RCS t RAC
t CSH t RSH t CAS
t CRP
CAS
t RAL t CAL t CAH
t ASC
Address
Column t RRH t RCH
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t RCHR High-Z t OEA t CAC t CLZ
WE
t WED t CDD t RDD
t DZC
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t OED Dout
Din
t DZO
OE
t AA
t OEZ t OHO t OFF
t OH t OFR t OHR
ct
t WEZ
Dout
Data Sheet E0156H10 14
HM5117805 Series
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Early Write Cycle
RAS tT CAS tASR tRAH Address Row WE Din Dout
tRC tRAS tRP
tCSH tRCD tRSH tCAS
tCRP
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tASC tWCS tDS
tCAH
Column
Data Sheet E0156H10 15
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tWCH
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High-Z*
tDH
Din
ct
* t WCS
t WCS (min)
HM5117805 Series
Delayed Write Cycle*18
t RC t RAS

t OEZ t CLZ Dout High-Z Invalid Dout Data Sheet E0156H10 16
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RAS CAS Address WE Din OE
t RP
t CSH t RCD tT t RSH t CAS
t CRP
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t ASR t RAH t ASC Row t RCS t DZC t DZO
t CAH
Column t CWL t RWL t WP
High-Z
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t OED
t DS
t DH
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Din t OEH
ct
HM5117805 Series
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RAS CAS Address WE Din OE Dout
Read-Modify-Write Cycle*18
t RWC t RAS
t RP
tT t RCD t CAS t CRP
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t RAD t ASR tRAH Row t RCS
t ASC
t CAH
Column t CWD t AWD t RWD tCWL t RWL t WP
Data Sheet E0156H10 17
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t DZC
High-Z
t DH t DS
Din
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t OED t OEH t OEZ
t DZO
t OEA
t CAC t AA t RAC
ct
High-Z
t OHO
Dout
t CLZ
HM5117805 Series
RAS-Only Refresh Cycle
t RC t RAS t RP
!
18
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RAS CAS Address Dout
tT t CRP t RPC t CRP
t OFF
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t ASR Row t OFR
t RAH
High-Z
Data Sheet E0156H10
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HM5117805 Series
,
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tT t CP t WRP t OFR t OFF CAS t WRH t CP WE Address
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RAS Dout
CAS-Before-RAS Refresh Cycle
t RC t RP t RAS t RP
t RPC
t CSR
t CHR
t RPC
t CRP
Data Sheet E0156H10 19
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High-Z
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HM5117805 Series
Hidden Refresh Cycle
t RC t RAS t RP t RC t RAS t RP t RAS t RC t RP

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WE t DZC High-Z Din
EO
RAS tT
CAS
t RSH
t CHR
t CRP
t ASR t RAH Address Row
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t RCD t RAD t RAL t ASC t CAH Column t RCS t DZO t CAC t AA t RAC t CLZ
t RRH
t WRH t WRP
t WRP
tWRH
t RRH t RCH
t WED t CDD t RDD
du
Dout
t OED
t OEA
OE
t OFF t OH
t OEZ t WEZ t OHO
ct
t OFR t OHR
Dout
Data Sheet E0156H10 20
HM5117805 Series

OE
EO
RAS
EDO Page Mode Read Cycle
t RP t RASP t CP t CAS t RCHR t RCH t RCS t HPC t CAS t CP t HPC tCAS t RCHC t HPC t CPRH t CP t t CRP
t RNCD
tT
t CSH
RSH
CAS
tCAS t RRH t RCH
t RCS
LP
tCAH Column 1 t CAL High-Z tOEA tCPA tCAC tAA tWEZ tRAC Dout 1
WE
tASR
Address
tRAH tASC Row
t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
t CAL tRDD tCDD
tDZC
Din
tDZO
tCOL
tCOP tOED
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tAA tCAC tOEZ tOHO tOEA Dout 2
tCPA
tCPA tAA tCAC
tAA
tOEZ
tOFR tOHR tOEZ
tCAC
tDOH
tOHO
tOEA
tOHO tOFF tOH
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Dout 2 Dout 3
Dout
Dout 4
ct
Data Sheet E0156H10 21
HM5117805 Series
EDO Page Mode Early Write Cycle
tRASP tRP
EO
RAS tT CAS tASR Address WE Din Dout 22
tCSH tRCD tCAS tCP
tHPC tCAS tCP
tRSH tCAS tCRP
Row
LP
tRAH tASC tCAH Column 1 tWCS tWCH tDS tDH Din 1
tASC
tCAH
tASC
tCAH
Column 2
Column N
Data Sheet E0156H10
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tWCS tDS Din 2 High-Z*
tWCH
tWCS
tWCH
tDH
tDS
tDH
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Din N
ct
* t WCS
t WCS (min)
HM5117805 Series

t OED t OED t OED t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z
EO
RAS tT
CAS
EDO Page Mode Delayed Write Cycle*18
t RASP t RP
t CP t CSH t RCD t CAS t HPC t CAS
t CP t RSH t CAS
t CRP
LP
t RAD t ASC t RAH t CAH Column 1 t RCS t WP t DZC t DS Din 1 t DZO
Invalid Dout
t ASR
t ASC t CAH Column 2 t CWL t RCS
t ASC t CAH Column N t CWL t RWL
Address
Row
t CWL t RCS
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t DH t DZO
Invalid Dout
WE
t WP t DH Din 2 t DZO
t WP t DZC t DS t DH Din N
t DZC t DS
Din
du
Invalid Dout
ct
Data Sheet E0156H10
23
HM5117805 Series
EDO Page Mode Read-Modify-Write Cycle*18
t RASP t RP
*
OE t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ
EO
RAS tT
CAS
t HPRWC t CP t CAS t CP t RCD t CAS
t RSH t CAS
t CRP
LP
t RAD t ASC t RAH t CAH Column 1 t RWD t AWD t CWD t RCS t WP t DZC t DS Din 1 t DZO
t OED
t ASR
t ASC t CAH Column 2 t CPW t AWD t CWD t RCS t CWL
t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
Row
t CWL t RCS
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t DH t DZO t OED Dout 2
WE
t WP t DH Din 2
t WP t DZC t DS t DH Din N
t DZC t DS
Din
du
t DZO t OEH
t OED t OEH
t OEH
ct
High-Z
Dout
Dout 1
Dout N
Data Sheet E0156H10 24
HM5117805 Series

OE
EO
RAS
EDO Page Mode Mix Cycle (1)
t RP t RASP t CRP tCAS tRSH t RCS tCPW tAWD tASC t CAH Column 3 t CAL t CAL t DS High-Z tOED t DH Din 3 tWED tWP t RAL t CAH Column 4 t CAL tRDD tCDD t RRH t RCH
tT
t CP t CAS t CSH t WCH t RCS t CAS
t CP tCAS
t CP
CAS
t RCD
LP
t WCS tCAH Column 1 t CAL t DH Din 1
WE
tASR
Address
t ASC tRAH Row
t ASC t CAH Column 2
tASC
t DS
Din
ro
tCPA tAA tOEA tCAC Dout 2
tCPA
tCPA tAA
t OEZ
tAA
tOFR tWEZ tOEZ
tCAC
tOHO tOFF tOH
t DOH
tCAC t OHO
tOEA
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Dout 3
Dout
Dout 4
ct
Data Sheet E0156H10 25
HM5117805 Series
EDO Page Mode Mix Cycle (2)
t RNCD t RASP
EO
RAS
t RP
tT
t CSH t CAS t RCHR t CAS
t CP tCAS
t CP tCAS t RCS tCPW tWP t RAL tASC t CAH Column 4 t CAL t DS t DH Din 3 tOED tCOP tRSH
t CRP
CAS
t RCD
t RCS
WE
tASR
Address
t ASC tRAH Row
LP
t RCH tCAH Column 1 t CAL t DS High-Z tOED tAA tOEA tCAC tOEZ t OHO Dout 1
tWCS t WCH
t RCS
t RRH t RCH
t ASC t CAH Column 2 t CAL t DH
t ASC t CAH Column 3 t CAL
tRDD tCDD
Din
Din 2
ro
tCOL
tWED
OE
t OEA tCPA tAA tCAC tOEZ t OHO
tCPA tAA tCAC tOEA
tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4
tRAC
du
Dout 3
Dout
ct
Data Sheet E0156H10 26
HM5117805 Series
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Data Sheet E0156H10 27
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RAS
Self Refresh Cycle (L-version) *21, 22, 23, 24
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HM5117805 Series
Package Dimensions
HM5117805J/LJ Series (CP-28DA)
Unit: mm
18.17 18.54 Max
10.16 0.13
3.50 0.26
1
0.74
14
11.18 0.13
1.30 Max
0.80 +0.25 -0.17
0.43 0.10 0.41 0.08
1.27
9.40 0.25
Hitachi Code JEDEC EIAJ Weight (reference value) CP-28DA Conforms Conforms 1.16 g
0.10
Dimension including the plating thickness Base material dimension
Data Sheet E0156H10 28
2.85 0.12
EO
28
15
LP
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HM5117805 Series
1
0.74
14
3.50 0.26
7.62 0.12
8.51 0.12
1.165 Max
0.90 0.26
0.43 0.10 0.41 0.08
6.79 0.18
1.27
0.10
Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
0.25 2.45 + 0.36 -
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HM5117805S/LS Series (CP-28DNA)
Unit: mm
18.41 18.84 Max
28
15
LP
Data Sheet E0156H10 29
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CP-28DNA -- -- 0.95 g
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HM5117805 Series
HM5117805TT/LTT Series (TTP-28DA)
Unit: mm 18.41 18.81 Max 15
1 0.42 0.08 0.40 0.06
1.27
M
14
10.16
0.10
0.145 0.05 0.125 0.04
0.13 0.05
1.20 Max
Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TTP-28DA Conforms -- 0.43 g
Data Sheet E0156H10 30
0.68
EO
28
LP
0.21 1.15 Max
0.80 11.76 0.20 0 - 5 0.50 0.10
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HM5117805 Series
1
1.27
14
0.42 0.08 0.40 0.06
0.21 M
7.62
0.50 0.10 0.145 0.05 0.125 0.04 0.13 0.05
1.20 Max
0.10
Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TTP-28DB -- -- 0.35 g
Data Sheet E0156H10 31
0.63
EO
HM5117805TS/LTS Series (TTP-28DB)
Unit: mm 18.41 18.81 Max 15
28
LP
1.15 Max
0.80 9.22 0.2 0 - 5
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HM5117805 Series
Cautions
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32
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products.
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Data Sheet E0156H10
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