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HI-8588-10
January 2001
ARINC 429 LINE RECEIVER
PIN CONFIGURATION
VCC 1 TESTA 2 RINB 3 RINA 4
DESCRIPTION
The HI-8588-10 ARINC 429 bus interface receiver is similar to the HI-8588 with the exception that it allows an external 10 Kohm resistor in series with each ARINC input without affecting the ARINC input thresholds. The product is especially useful in applications where lightning protection circuitry is also required. In addition, the test inputs force both of the outputs to zero instead open circuit. The analog/digital CMOS product requires only a 5 volt supply and is available in a SO 8 pin package. Each side of the ARINC bus must be connected through a 10 Kohm series resistor in order for the chip to detect the correct ARINC levels. The typical 10 volt differential signal is translated and input to a window comparator and latch. The comparator levels are set so that with the external 10 Kohm resistors they are just below the standard 6.5 volt minimum ARINC data threshold and just above the standard 2.5 voltmaximum ARINC null threshold. The TESTA and TESTB inputs bypass the analog inputs for testing purposes. Also if TESTA and TESTB are both taken high, the digital outputs are forced to zero.
8 TESTB 7 ROUTB 6 ROUTA 5 GND
SUPPLY VOLTAGES
vcc = 5.0V 5%
FUNCTION TABLE
FEATURES
PIN DESCRIPTION TABLE
PIN SYMBOL VCC TESTA RINB RINA GND ROUTA ROUTB TESTB FUNCTION SUPPLY LOGIC INPUT ARINC INPUT ARINC INPUT POWER LOGIC OUTPUT LOGIC OUTPUT LOGIC INPUT CMOS RECEIVER B INPUT RECEIVER A INPUT GROUND RECEIVER CMOS OUTPUT A RECEIVER CMOS OUTPUT B CMOS DESCRIPTION 5 VOLT SUPPLY
(DS8588-10 Rev. A)
HOLT INTEGRATED CIRCUITS 1
01/01
HI-8588-10
FUNCTIONAL DESCRIPTION
RECEIVER Figure 1 shows the general architecture of the ARINC 429 receiver. The receiver operates off the VCC supply only. The inputs RINA and RINB each require 35KW of resistance of which 25KW is internal to the chip. The series resistance is connected to level translators whose resistance to Ground is typically 10KW. In order for the voltage translation not to be adversely affected, an external 10KW series resister must be added to each ARINC input. The HI-8588-10 device is typically chosen for applications where external series resistors are required in its lightning protection circuitry. After level translation, the inputs are buffered and become inputs to a differential amplifier. The amplitude of the differential signal is compared to levels derived from a divider between VCC and Ground. The nominal settings correspond to a One/Zero amplitude of 6.0V and a Null amplitude of 3.3V. The status of the ARINC receiver input is latched. A Null input resets the latches and a One or Zero input sets the latches. The logic at the output is controlled by the test signal which is generated by the logical OR of the TestA and TestB pins. Unlike the HI-8588, if TestA and TestB are both One, the HI-8588-10 outputs are pulled low instead of being tri-stated. This allows the digital outputs of a transmitter to be connected to the test inputs through control logic for self-test purposes.
ONE
S R Q LATCH
TEST
ROUTA TESTA TESTB
RINA
RINB
ESD PROTECTION AND TRANSLATION
NULL TEST S R Q ROUTB TESTA TESTB NULL
ZERO
LATCH
FIGURE 1 - RECEIVER BLOCK DIAGRAM
APPLICATION INFORMATION
1
Figure 2 shows a possible application of the HI-8588 interfacing an ARINC receive channel to the HI-6010 which in turn interfaces to an 8-bit bus.
HARDWIRE OR DRIVE FROM LOGIC
{
10K 10K
2 8 4 3
VCC
TESTA TESTB
ROUTA ROUTB
6 7
RXD1 RXD0
HI-8588-10
RINA RINB GND
ARINC Channel
HI-6010
5
15V
1 6
ARINC Channel
SLP1.5 TXAOUT V+ TX0IN
8 BIT BUS
8 2 3
TXD0 TXD1
7
HI-8586
TXBOUT GND VTX1IN
4
5
-15V
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS 2
HI-8588-10 ABSOLUTE MAXIMUM RATINGS
Voltages referenced to Ground Supply voltages VCC...................................................7V ARINC input - pins 3 & 4 Voltage at either pin......+29V to -29V DC current per input pin................ 10mA Power dissipation at 25C plastic DIL............0.7W ceramic DIL..........0.5W Solder Temperature ........275C for 10 sec Storage Temperature........-65C to +150C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. Supply Voltages VCC........................................5V... 5% Temperature Range Industrial Screening........-40C to +85C Hi-Temp Screening.......-55C to +125C Military Screening.........-55C to +125C
RECOMMENDED OPERATING CONDITIONS
DC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE RANGE, VCC = 5.0V UNLESS OTHERWISE STATED PARAMETERS ARINC input voltage one or zero null common mode logic input voltage high low ARINC input resistance RINA to RINB RINA or RINB to Gnd or VCC logic input current source sink logic output drive current one zero Current drain operating SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
V DIN V NIN VCOM V IH V IL R DIFF R SUP I IH I IL I OH I OL I CC1
diff. volt. thru 10KW, pins 3 & 4 " " " with respect to Ground
6.5 -
10 -
13 2.5 5.0
volts volts volts
3.5 -
-
1.5
volts volts
supplies floating & series 10KW " V IN = 0 V V IN = 5 V V = 4.6V OH VOL = 0.4V pins 2, 8 = 0V; pins 3, 4 open " "
30 19
75 40
-
Kohm Kohm A A
-
-
0.1 0.1
3.6
-1.6 5.6
-0.8 -
mA mA
-
2.3
6.3
mA
HOLT INTEGRATED CIRCUITS 3
HI-8588-10 AC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE RANGE, VCC = 5.0V UNLESS OTHERWISE STATED PARAMETERS Receiver propagation delay Output high to low Output low to high Receiver output transition times Output high to low Output low to high Input capacitance (1) ARINC differential ARINC single ended to Ground Logic 1. Guaranteed but not tested SYMBOL TEST CONDITIONS defined in Figure 3, C L= 50pF t phlr t plhr t fr t rr CAD CAS C IN ns ns MIN TYP MAX UNITS
ns ns pF pF pF
VDIFF pin 4 - pin 3 t plhr t phlr
90%
10V 0V -10V t rr 5V 0V t fr 5V 0V
pin 6 t plhr
10%
t phlr
pin 7 FIGURE 3 - RECEIVER TIMING
ORDERING INFORMATION
PART PACKAGE TEMPERATURE BURN LEAD
NUMBER HI-8588PDI-10 HI-8588PDT-10 HI-8588PSI-10 HI-8588PST-10 HI-8588CDI-10 HI-8588CDT-10 HI-8588CDM-10 HI-8588CRI-10 HI-8588CRT-10 HI-8588CRM-10
DESCRIPTION 8 PIN PLASTIC DIP 8 PIN PLASTIC DIP 8 PIN PLASTIC NARROW BODY SOIC 8 PIN PLASTIC NARROW BODY SOIC 8 PIN CERAMIC SIDE BRAZED DIP 8 PIN CERAMIC SIDE BRAZED DIP 8 PIN CERAMIC SIDE BRAZED DIP 8 PIN CERDIP 8 PIN CERDIP 8 PIN CERDIP
RANGE -40C TO +85C -55C TO +125C -40C TO +85C -55C TO +125C -40C TO +85C -55C TO +125C -55C TO +125C -40C TO +85C -55C TO +125C -55C TO +125C
FLOW I T I T I T M I T M
IN NO NO NO NO NO NO YES NO NO YES
FINISH SOLDER SOLDER SOLDER SOLDER GOLD GOLD SOLDER SOLDER SOLDER SOLDER
HOLT INTEGRATED CIRCUITS 4
HI-8588-10 PACKAGE DIMENSIONS
inches (millimeters)
8-PIN PLASTIC DIP
Package Type: 8P
.385 .015 (4.699 .381)
.250 .010 (6.350 .254) .100 .010 (3.540 .254) .300 .010 (7.620 .254) 7 TYP. .135 .015 (3.429 .381) .1375 .0125 (3.493 .318) .019 .002 (.483 .102) .025 .010 (.635 .254) .0115 .0035 (.292 .089) .055 .010 (1.397 .254) .335 .035 (8.509 .889)
8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB (Narrow Body)
.1935 .0035 (4.915 .085)
Package Type: 8HN
.0086 .0012 (.2184 .0305) .236 .008 (5.994 .203)
PIN 1
.1535 .0035 (3.90 .09)
.0165 .0035 (.4191 .0889)
Detail A
.055 .005 (1.397 .127)
0 to 8
.050 .010 (1.27 .254) .033 .017 (.8382 .4318)
.0069 .0029 (.1753 .0737)
Detail A
HOLT INTEGRATED CIRCUITS 5
HI-8588-10 PACKAGE DIMENSIONS
inches (millimeters)
8-PIN CERAMIC SIDE-BRAZED DIP
Package Type: 8C
.405 MAX (10.287 MAX) .050 .007 (1.270 .178) .250 .008 (7.366 .203) PIN 1 .050 .005 (1.270 .127) .035 .010 (.889 .254) BASE PLANE .163 .037 (4.140 .940) .018 .002 (.457 .051)
.200 MAX (5.080 MAX)
.0105 .0015 (.267 .038)
SEATING PLANE .100 .003 (2.540 .076) .300 .010 (7.620 .254)
8-PIN CERDIP
Package Type: 8D
.380 .004 (9.652 .102) .005 MIN. (.127 MIN.) .248 .003 (6.299 .076) .039 .006 (.991 .154)
.100 .008 (2.540 .203) .015 MIN. (.381 MIN.)
.314 .003 (7.976 .076)
.200 MAX. (5.080 MAX.) .163 .037 (4.140 .940)
Base Plane Seating Plane
.056 .006 (1.422 .152) .018 .006 (.457 .152) .350 .030 (8.890 .762)
.010 .006 (.254 .152)
HOLT INTEGRATED CIRCUITS 6

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