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HI-8010/HI-8110 Series
January 2001
GENERAL DESCRIPTION
The HI-8010 & HI-8110 high voltage display drivers are constructed of MOS P Channel and N Channel enhancement mode devices in a single monolithic structure. They are designed to drive high voltage liquid crystal displays by converting low level input signals (TTL on the HI-8010 and CMOS on the HI-8110) to high voltage drive signals. Both devices can drive up to 38 segments and require minimal display-to-data source interfacing. Serial data is loaded and held in internal latches until new display data is received. The HI-8010 & HI-8110 are available in a variety of ceramic and plastic packaging including DIP; leaded and leadless chip carriers; and J-lead and gull-wing quad flat packs.
PIN CONFIGURATION (Top View)
LD DIN LCDO LCDOOPT VDD S37 S38 S1 S2 S3 S4 S5 S6
2 3 4 5 6 7 8 9 10 11 12
HI-8010PQI HI-8110PQI HI-8010PQT & HI-8110PQT
52 - PIN PLASTIC QFP
39 38 37 36 35 34 33 32 31 30 29 28
S26 S25 S24 S23 S22 S21 S20 DOUT 38 N/C N/C N/C BP S19
FEATURES
! 5 volt input translated to 30 volts or less ! Pin-out adaptable to drive 30, 32 or 38 LCD segments ! RC oscillator or high voltage (BP) clock input ! TTL compatible inputs (HI-8010 only) ! CMOS compatible inputs (HI-8110 only) ! Low power consumption ! Industrial (-40C to +85C) & Military (-55C to +125C) temperature ranges ! Pin for pin compatible with the Micrel MIC8010/8011 series and the AMI S4520 series drivers ! Cascadable ! Military level processing available
DIN CL CS
LE DATA IN
(See page 3-6 for additional package pin configurations)
FUNCTIONAL BLOCK DIAGRAM
DOUT 38 DOUT 32 DOUT 30
38 Stage Shift Register
CLK
LD LCDO OPT LCDO
Oscillator Divider Voltage Translator
38 Bit Latch
Voltage Translators High Voltage Drivers
! Dichroic Liquid Crystal Displays ! Standard Liquid Crystal Displays ! Vacuum Fluorescent Displays
H i g h Voltage Buffer
BP
SEGMENTS
(DS8010, Rev. C)
HOLT INTEGRATED CIRCUITS 3-3
01/01
HI-8010/HI-8110 Series
FUNCTIONAL DESCRIPTION
Whenever a Logic "0" is applied to the Chip Select (CS) input, one bit of data is clocked into the shift register from the serial data input (DIN) with each negative transition of the Clock (CL) input. CS is internally tied to VSS on some versions. A Logic "1" present at the Load (LD) input will cause a parallel transfer of data from the shift register to the data latch. If the Load (LD) input is held high while data is clocked into the shift register, the latch will be transparent. All four logic inputs are TTL compatible on the HI-8010 and CMOS compatible on the HI-8110. To display segments, a Logic "1" is stored in the appropriate shift register bit position, and the segment output is out-ofphase with the backplane. The backplane output functions in 1 of 2 modes; externally driven or self-oscillating. When the LCDO input is externally driven with the LCDOOPT input open circuit (Figure 2), the backplane output will be in-phase with LCDO. Utilizing the self-oscillating mode, inputs LCDO and LCDOOPT are tied together and connected to an RC circuit (Figure 3). A 150KW resistor with a 470pF capacitor generates an approximate backplane frequency of 100Hz. The LCDO/LCDOOPT oscillator frequency is divided by 256 to determine the backplane output frequency. The resistor value (R) must be at least 30KW for proper self-oscillator operation. For displays having a number of segments greater than 38, two or more of the display drivers may be cascaded together by connecting the serial data output (DOUT) from the first driver, to the serial data input (DIN) of the following driver, etc. (See Figures 2 & 3). Data out (DOUT) will change state on the rising edge of the Clock (CL). Clock (CL), Load (LD) and Chip Select (CS) should be tied in common with each other, respectively, between all cascaded display drivers.
INTERNAL OSCILLATOR CIRCUIT
/ 256
Q
LCDO LCDO OPT
TO BACKPLANE TRANSLATOR AND DRIVER
Figure 1
TIMING DIAGRAM
CL INPUT
tCL
DIN INPUT
VALID
tDS tDH
CS INPUT
tCSS
tCSH
LD INPUT
tLCS tCSL
tCDO
DOUT OUTPUT
tLS
VALID
tLW
HOLT INTEGRATED CIRCUITS 3-4
HI-8010/HI-8110 Series
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to VSS = 0V VDD........................ 0V to 7V VEE................VDD-35V to 0V Voltage at any input, except LCDO..-0.3 to VDD+0.3V Voltage at LCDO input...............VDD-35 to VDD+0.3V DC Current any input pin...................................10 mA Supply Voltage Power Dissipation......................................................300 mW Operating Temperature Range - Industrial........-40 to +85C Operating Temperature Range - Hi-Temp/Mil..-55 to +125C Storage Temperature Range...........................-65 to +150C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER Operating Voltage Supply Current
SYMBOL VDD IDD IEE
CONDITION
MIN 3.0
TYP
MAX 7.0 200 150
UNITS V A A V V V V V V A pF W W mA mA
Static, No Load Static, No Load fBP=100Hz 0 2 0 0.7 VDD VEE 3.5 VIN = 0 to 5V
Input Low Voltage, HI-8010 (except LCDO) Input High Voltage, HI-8010 (except LCDO) Input Low Voltage, HI-8110 (except LCDO) Input High Voltage, HI-8110 (except LCDO) Input Low Voltage (LCDO) Input High Voltage (LCDO) Input Current Input Capacitance (not tested) Segment Output Impedance Backplane Output Impedance Data Out Current:
VILTTL VIHTTL VILCMOS VIHCMOS VILX VIHX IIN CI RSEG RBP IDOH IDOL IL = 10A IL = 10A Source Current, VOH = 4.5V Sink Current, VOL = 0.5V
0.8 VDD 0.3 VDD VDD 3 VDD 1 5 10,000 450 -0.6
0.6
AC ELECTRICAL CHARACTERISTICS
VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER Clock Period Clock Pulse Width Data In - Setup Data In - Hold Chip Select - Setup to Clock Chip Select - Hold to Clock Load - Setup to Clock Chip Select - Setup to Load Load Pulse Width Chip Select - Hold to Load Data Out Valid, from Clock
SYMBOL tCL tCW tDS tDH tCSS tCSH tLS tCSL tLW tLCS tCDO
VDD 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V
MIN 1200 520 50 400 200 450 500 300 500 300
TYP
MAX
UNITS ns ns ns ns ns ns ns ns ns ns
800
ns
HOLT INTEGRATED CIRCUITS 3-5
HI-8010/HI-8110 Series
CASCADING - EXT. OSCILLATOR
LD CL CS
CS DIN CL LD DOUT CS DIN CL LD DOUT CS DIN CL LD DOUT
CASCADING - RC OSCILLATOR
LD CL CS
CS DIN
150KW
CL
LD DOUT
CS DIN
CL
LD DOUT
CS DIN
CL
LD DOUT
HI-8010J-85
LCDO BP
HI-8010J-85
LCDO BP
HI-8010J-85
LCDO BP
HI-8110PQI
LCDO LCDO OPT BP
HI-8110PQI
LCDO LCDO OPT BP
HI-8110PQI
LCDO LCDO OPT BP
470pf
SEGMENTS 1 - 32
SEGMENTS BACK 33 - 64 PLANE
SEGMENTS 65 - 96
SEGMENTS 1 - 38
SEGMENTS BACK 39 - 76 PLANE
SEGMENTS 77 - 114
Figure 2
Figure 3
ADDITIONAL HI-8010/HI-8110 PIN CONFIGURATIONS
(See page 3-3 for 52-Pin Plastic QFP)
S27 S28 S29 S30 S31 S32 N/C VSS CS CL LD
7 8 9 10 11 12 13 14 15 16 17
39 38
HI-8010J-85 & HI-8110J-85
44 - PIN PLASTIC PLCC
37 36 35 34 33 32 31 30 29
S17 S16 S15 VEE S14 S13 S12 S11 S10 S9 S8
LCDOOPT VDD S1 S2 S3 S4 S5 S6 S7 S8
6 7 8 9 10 11 12 13 14 15
35 34
HI-8010SM-36 & HI-8110SM-36
40 - PIN CERAMIC LCC
33 32 31 30 29 28 27 26
S25 S24 S23 S22 S21 S20 DOUT 30 BP S19 S18
LCDO LCDOOPT VDD S37 S38 S1 S2 S3 S4 S5 S6 S7
7 8 9 10 11 12 13 14 15 16 17 18
42 41 40 39 38 37 36 35 34 33 32
HI-8010SM-32 & HI-8110SM-32
48 - PIN CERAMIC LCC
S28 S27 S26 S25 S24 S23 S22 S21 S20 DOUT 38 BP S19
HOLT INTEGRATED CIRCUITS 3-6
HI-8010/HI-8110 Series
ORDERING INFORMATION
PART NUMBER HI-8010J-85 HI-8010PQI HI-8010PQT HI-8010SM-32 HI-8010SM-36 CMOS Logic Inputs HI-8110J-85 HI-8110PQI HI-8110PQT HI-8110SM-32 HI-8110SM-36 32 38 38 38 30 BOTH BOTH BOTH BOTH BOTH 44 PIN PLASTIC J LEAD 52 PIN PLASTIC QUAD FLAT PACK (PQFP) 52 PIN PLASTIC QUAD FLAT PACK (PQFP) 48 PIN CERAMIC LEADLESS CHIP CARRIER 40 PIN CERAMIC LEADLESS CHIP CARRIER -40C TO +85C -40C TO +85C -55C TO +125C -55C TO +125C -55C TO +125C I I T M M NO NO NO YES YES SOLDER SOLDER SOLDER SOLDER SOLDER NUMBER OF SEGMENTS 32 38 38 38 30 MASTER /SLAVE BOTH BOTH BOTH BOTH BOTH PACKAGE DESCRIPTION 44 PIN PLASTIC J LEAD 52 PIN PLASTIC QUAD FLAT PACK (PQFP) 52 PIN PLASTIC QUAD FLAT PACK (PQFP) TEMPERATURE BURN LEAD RANGE FLOW IN FINISH -40C TO +85C -40C TO +85C -55C TO +125C I I T M M NO NO NO SOLDER SOLDER SOLDER TTL Logic Inputs
48 PIN CERAMIC LEADLESS CHIP CARRIER -55C TO +125C 40 PIN CERAMIC LEADLESS CHIP CARRIER -55C TO +125C
YES SOLDER YES SOLDER
SEMI-CUSTOM PACKAGING
The above part numbers represent some of the typical configurations of the HI-8010 & HI-8110 products. They can also be provided with a varied number of output segments (30, 32 and 38), with either industrial or military screening and in a wide variety of packages. Listed below are currently available packages. Please contact the Holt Sales Department for your specific requirements.
PACKAGE DESCRIPTION PLASTIC DUAL-IN-LINE (PDIP)
# LEADS 40 48
PLASTIC QUAD FLAT PACK (PQFP) PLASTIC J-LEAD CHIP CARRIER (PLCC) CERAMIC DUAL-IN-LINE (CDIP)
52 44 40 48
CERAMIC LEADLESS CHIP CARRIER (LCC)
40 48
CERAMIC J-LEAD CHIP CARRIER
44 48
CERAMIC LEADED CHIP CARRIER
40 48
HOLT INTEGRATED CIRCUITS 3-7
HI-8010/HI-8110 Series
SYMBOL
VSS CS CL LD DIN LCD0 LCD0OPT VDD VEE DOUT BP Segments
FUNCTION
POWER INPUT INPUT INPUT INPUT INPUT OUTPUT POWER POWER OUTPUT OUTPUT OUTPUT 0 Volts Logic input Logic input Logic input Logic input Analog input Analog output 5 Volts O Volts to -30 Volts Logic output Display drive output Display drive output
DESCRIPTION
Chip select Clocks shift register on negative edge and DOUT pins on positive edge Segment outputs equal shift register data if Load is high Shift register data input Display clock input and is always bonded out. Can swing from VEE to VDD Bonded out only if an RC oscillator is required
Selected pinout can provide shift register taps at positions 30, 32, 34, or 38 Low resistance drive for the backplane and swings from VDD to VEE High resistance drive for each segment and swings from VDD to VEE
HOLT INTEGRATED CIRCUITS 3-8
HI-8010/HI-8110 PACKAGE DIMENSIONS
inches (millimeters)
44-PIN PLASTIC PLCC
Package Type: 44J
PIN NO. 1 .045 x 45 PIN NO. 1 IDENT .045 x 45 .050 .005 (1.27 .127) .690 .005 (17.526 .127) SQ. .653 .004 (16.586 .102) SQ. .031 .005 (.787 .127) .017 .004 (.432 .102)
SEE DETAIL A
.009 .011
.172 .008 (4.369 .203) .610 .020 (15.494 .508) DETAIL A
.015 .002 (.381 .051) .020 MIN (.508 ) R .025 .045
52-PIN PLASTIC QUAD FLAT PACK
Package Type: 52PQS
.0256 BSC (0.65 BSC) .520 .010 (13.2 .25) SQ. .394 .004 (10.00 .10) SQ. .012 .003 (.30 .08) .035 .006 (.88 .15) .088 .032 (1.6 .175) Typ.
.008 (0.20) Min. .009 .003R (.225 .075R)
See Detail A
.092 .004 (2.32 .12) .079 .002 (2.00 .05) .009 R typ (0.23 R typ)
0 7
DETAIL A
HOLT INTEGRATED CIRCUITS 1
HI-8010/HI-8110 PACKAGE DIMENSIONS
inches (millimeters)
40-PIN CERAMIC LEADLESS CHIP CARRIER
PACKAGE TYPE: 40S
PIN 1 IDENT.
.085 MAX. (2.159 MAX.)
.044 .011 (1.118 .280)
PIN 1 IDENT.
.484 .009 (12.294 .228) SQ.
.020 .003 (.508 .076)
.040 .003 (1.016 .076)
48-PIN CERAMIC LEADLESS CHIP CARRIER
Package Type: 48S
PIN 1 IDENT.
.090 MAX. (2.286 MAX.)
.040 .007 (1.016 .178)
PIN 1 IDENT.
.563 .009 (14.300 .228) SQ.
.020 TYP. (.508 TYP.)
.040 TYP. (1.016 TYP.)
HOLT INTEGRATED CIRCUITS 2

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