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DISCRETE SEMICONDUCTORS DATA SHEET BSP126 N-channel enhancement mode vertical D-MOS transistor Product specification File under Discrete Semiconductors, SC13b April 1995 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor DESCRIPTION N-channel enhancement mode vertical D-MOS transistor in a miniature SOT223 envelope and designed for use as a line interrupter in telephone sets and for application in relay, high-speed and line-transformer drivers. FEATURES * Direct interface to C-MOS, TTL, etc. * High-speed switching. * No secondary breakdown. PINNING - SOT223 1 = gate 2 = drain 3 = source 4 = drain Marking code BSP126 QUICK REFERENCE DATA Drain-source voltage Drain current (DC) Total power dissipation up to Tamb = 25 C Drain-source on-resistance ID = 300 mA; VGS = 10 V Gate-source threshold voltage RDS(on) VGS(th) VDS ID Ptot BSP126 max. max. max. typ. max. max. 250 V 350 mA 1.5 W 5.0 7.0 2V PIN CONFIGURATION handbook, halfpage 4 d g 1 Top view 2 3 MAM054 s Fig.1 Simplified outline and symbol. April 1995 2 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Drain-source voltage Gate-source voltage (open drain) Drain current (DC) Drain current (peak) Total power dissipation up to Tamb = 25 C (note 1) Storage temperature range Junction temperature THERMAL RESISTANCE From junction to ambient (note 1) Note Rth j-a = VDS VGSO ID IDM Ptot Tstg Tj max. max. max. max. max. max. BSP126 250 V 20 V 350 mA 1.2 A 1.5 W -65 to + 150 C 150 C 83.3 K/W 1. Device mounted on an epoxy printed-circuit board 40 mm x 40 mm x 1.5 mm; mounting pad for the drain lead min. 6 cm2. CHARACTERISTICS Tj = 25 C unless otherwise specified Drain-source breakdown voltage ID = 10 A; VGS = 0 Drain-source leakage current VDS = 200 V; VGS = 0 Gate-source leakage current VGS = 20 V; VDS = 0 Gate threshold voltage ID = 1 mA; VDS = VGS Drain-source on-resistance ID = 300 mA; VGS = 10 V ID = 20 mA; VGS = 2.4 V Transfer admittance ID = 300 mA; VDS = 25 V Input capacitance at f = 1 MHz; VDS = 25 V; VGS = 0 Output capacitance at f = 1 MHz; VDS = 25 V; VGS = 0 Coss typ. max. 20 pF 30 pF Ciss typ. max. 65 pF 90 pF Yfs min. typ. 200 mS 400 mS RDS(on) RDS(on) typ. max. max. VGS(th) min. max. 0.8 V 2.0 V 5.0 7.0 10 IGSS max. 100 nA IDSS max. 1.0 A V(BR)DSS min. 250 V April 1995 3 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor Feedback capacitance at f = 1 MHz; VDS = 25 V; VGS = 0 Switching times (see Figs 2 and 3) ID = 250 mA; VDD = 50 V; VGS = 0 to 10 V ton typ. max. typ. max. Crss typ. max. BSP126 5 pF 15 pF 5 ns 10 ns 20 ns 30 ns toff handbook, halfpage VDD = 50 V handbook, halfpage 90 % INPUT 10 % 10 V 0V ID 50 MSA631 90 % OUTPUT 10 % ton toff MBB692 Fig.2 Switching time test circuit. Fig.3 Input and output waveforms. April 1995 4 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BSP126 handbook, 2 MBB693 Ptot (W) 1.6 handbook, halfpage 2 MDA712 ID (A) 1.6 VGS = 10 V 6V 5V 1.2 1.2 4V 0.8 0.8 0.4 0.4 3V 2V 0 0 50 100 150 200 Tamb (C) 0 0 2 4 6 8 10 VDS (V) Fig.5 Fig.4 Power derating curve. Output characteristics; Tj = 25 C; typical values. handbook, halfpage 2 MDA713 ID (A) 1.6 104 handbook, halfpage ID (mA) 103 VGS = 10 V 5V 4V 3V MDA714 1.2 0.8 102 0.4 0 0 2 4 6 8 10 VGS (V) 10 0 4 8 12 16 RDSon () Fig.6 Transfer characteristic; VDS = 10 V; Tj = 25 C; typical value. Fig.7 On-resistance as a function of drain current; Tj = 25 C; typical values. April 1995 5 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor handbook, half age BSP126 2.8 k 2.4 MDA717 handbook, halfpage 1.4 k 1.2 MDA716 2 (1) (2) 1.6 1 1.2 0.8 0.8 0.4 -50 0 50 100 Tj (C) 150 0.6 -50 0 50 100 Tj (C) 150 Fig.8 R DS ( on ) at T j k = ---------------------------------------------- ; typical values. R DS ( on ) at 25 C Fig.9 V GS ( th ) at T j k = -------------------------------------------- ; VGS(th) at 1 mA; V GS ( th ) at 25 C typical values. handbook, halfpage 200 C (pF) MDA715 160 120 80 Ciss 40 Coss Crss 0 0 5 10 15 20 25 VDS (V) Fig.10 Capacitances as a function of drain-source voltage; VGS = 0; f = 1 MHz; Tj = 25 C; typical values. April 1995 6 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor PACKAGE OUTLINE Plastic surface mounted package; collector pad for good heat transfer; 4 leads BSP126 SOT223 D B E A X c y HE b1 vMA 4 Q A A1 1 e1 e 2 bp 3 wM B detail X Lp 0 2 scale 4 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.8 1.5 A1 0.10 0.01 bp 0.80 0.60 b1 3.1 2.9 c 0.32 0.22 D 6.7 6.3 E 3.7 3.3 e 4.6 e1 2.3 HE 7.3 6.7 Lp 1.1 0.7 Q 0.95 0.85 v 0.2 w 0.1 y 0.1 OUTLINE VERSION SOT223 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 96-11-11 97-02-28 April 1995 7 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS BSP126 This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. April 1995 8 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor NOTES BSP126 April 1995 9 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor NOTES BSP126 April 1995 10 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor NOTES BSP126 April 1995 11 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997 Internet: http://www.semiconductors.philips.com SCA54 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 137107/1200/01/pp12 Date of release: April 1995 Document order number: 9397 750 02474 |
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