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PA7540 PEEL ArrayTM
Programmable Electrically Erasable Logic Array
Most Powerful 24-pin PLD Available - 20 I/Os, 2 inputs/clocks, 40 registers/latches - 40 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications - Integration of multiple PLDs and random logic - Buried counters, complex state-machines - Comparators, decoders, multiplexers and other widegate functions High-Speed Commercial and Industrial Versions - As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX) - Industrial grade available for 4.5 to 5.5V VCC and -40 to +85 C temperatures CMOS Electrically Erasable Technology - Reprogrammable in 24-pin DIP, SOIC and 28-pin PLCC packages - Optional JN package for 22V10 power/ground compatibility Flexible Logic Cell - 2 output functions per logic cell - D,T and JK registers with special features - Independent or global clocks, resets, presets, clock polarity and output enables - Sum-of-products logic for output enables Development and Programmer Support - Anachip's WinPLACE Development Software - Fitters for ABEL, CUPL and other software - Programming support by popular third-party programmers presets, clock polarity, and other features, making the PA7540 suitable for a variety of combinatorial, synchronous and asynchronous logic applications. With pin compatibility and super-set functionality to most 24-pin PLDs, (22V10, EP610/630, GAL6002), the PA7540 can implement designs that exceed the architectures of such devices. The PA7540 supports speeds as fast as 10ns/15ns (tpdi/tpdx) and 71.46MHz (fMAX) at moderate power consumption 80mA (55mA typical). Packaging includes 24-pin DIP, SOIC and 28-pin PLCC (see Figure 1). Anachip and popular third-party development tool manufacturers provide development and programming support for the PA7540.
General Description
The PA7540 is a member of the Programmable Electrically Erasable Logic (PEELTM) Array family based on ICT's CMOS EEPROM technology. PEELTM Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today's programmable logic designs. The PA7540 is by far the most powerful 24-pin PLD available today with 20 I/O pins, 2 input/global-clocks and 40 registers/latches (20 buried logic cells and 20 I/O registers/latches). Its logic array implements 84 sum-of-products logic functions. The PA7540's logic and I/O cells (LCCs, IOCs) are extremely flexible offering two output functions per cell (a total of 40 for all 20 logic cells). Logic cells are configurable as D, T, and JK registers with independent or global clocks, resets,
Figure 1. Pin Configuration
I/C LK1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VC C I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/C LK2 I/C LK1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VC C I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/C LK2
Figure 2. Block Diagram
2 Input/ G lobal C lock P ins G lobal C ells 84 (42X2) A rray Inputs true and com plem ent 20 B uried logic Logic functions to I/O cells
2
I/C L K 1 I/O I/O I/O I/O I/O G lo b a l C e lls I/O C e lls VC C I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O L o g ic Arr ay
I/O C ells (IO C )
20 I/O P ins
SO IC
I/CLK1
20 Logic C ontrol C ells (LC C )
I/CLK1
DIP
I/O I/O
I/O I/O I/O 25 24 23 22 21 20 19 I/O I/O I/O NC I/O I/O I/O L o g ic C o n tro l C e lls I/O I/O G ND
A B C D
VCC
VCC
VCC
NC
I/O
I/O
I/O
I/O
I/O
I/O
20 20
4 I/O I/O I/O NC I/O I/O I/O 5 6 7 8 9 10 11
3
2
1
28 27 26 25 24 23 22 21 20 19 I/O I/O I/O NC I/O I/O I/O I/O I/O I/O NC I/O I/O I/O 5 6 7 8 9 10 11
4
3
2
1 28 27 26
PA7540
I/C L K 2
4 sum term s 4 product term s for G lobal C ells
80 sum term s (four per LC C )
20 Logic C ontrol Cells 2 output functions per cell (40 total output functions possible)
0 8 -1 4 -0 02 A
1 2 1 3 1 4 1 5 1 6 1 71 8
12 13 14 15 16 17 18
GND
GND
GND
I/CLK2
NC
I/CLK2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PLCC -J
I/O
PLCC -JN
08-14-001B
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Inside the Logic Array
The heart of the PEELTM Array architecture is based on a logic array structure similar to that of a PLA (programmable AND, programmable OR). The logic array implements all logic functions and provides interconnection and control of the cells. In the PA7540 PEELTM Array, 42 inputs are available into the array from the I/O cells and input/globalclock pins. All inputs provide both true and complement signals, which can be programmed to any product term in the array. The PA7540 PEELTM Arrays contains 84 product terms. All product terms (with the exception of certain ones fed to the global cells) can be programmably connected to any of the sum-terms of the logic control cells (four sum-terms per logic control cell). Product-terms and sum-terms are also routed to the global cells for control purposes. Figure 3 shows a detailed view of the logic array structure. needed and not left unutilized or duplicated. Secondly, the sum-of-products functions provided to the logic cells can be used for clocks, resets, presets and output enables instead of just simple product-term control. The PEELTM logic array can also implement logic functions with many product terms within a single-level delay. For example a 16-bit comparator needs 32 shared product terms to implement 16 exclusive-OR functions. The PEELTM logic array easily handles this in a single level delay. Other PLDs/CPLDs either run out of product-terms or require expanders or additional logic levels that often slow performance and skew timing.
Logic Control Cell (LCC)
Logic Control Cells (LCC) are used to allocate and control the logic functions created in the logic array. Each LCC has four primary inputs and three outputs. The inputs to each LCC are complete sum-of-product logic functions from the array, which can be used to implement combinatorial and sequential logic functions, and to control LCC registers and I/O cell output enables.
From G lobal C ell S ys tem C lock P res et R egType R es et
From IO C ells (IO C) and I/CLKs
42 Array Inputs
O n /O ff
From Logic Control Cells (LCC)
MUX
P D ,T,J Q
To A rray
MUX
K
R EG
R
To G lobal Cells
84 Product Term s
From A rray
A B C D
MUX
To I/O C ell
To Logic C ontrol Cells (LCC)
08 -14 -0 04 A
PA 7540 Logic Array
84 Sum Term s
08-14-003A
Figure 4. Logic Control Cell Block Diagram
As shown in Figure 4, the LCC is made up of three signal routing multiplexers and a versatile register with synchronous or asynchronous D, T, or JK registers (clocked-SR registers, which are a subset of JK, are also possible). See Figure 5. EEPROM memory cells are used for programming the desired configuration. Four sum-of-product logic functions (SUM terms A, B, C and D) are fed into each LCC from the logic array. Each SUM term can be selectively used for multiple functions as listed below.
Figure 3 PA7540 Logic Array True Product-Term Sharing
The PEELTM logic array provides several advantages over common PLD logic arrays. First, it allows for true productterm sharing, not simply product-term steering, as commonly found in other CPLDs. Product term sharing ensures that product-terms are used where they are
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Sum-A = D, T, J or Sum-A Sum-B = Preset, K or Sum-B Sum-C = Reset, Clock, Sum-C Sum-D = Clock, Output Enable
D P
D R e g is te r Q = D after clocked
can be registered, one output can be combinatorial and the third, an output enable. The multi-function PEELTM Array logic cells are equivalent to two or three macrocells of other PLDs, which have only one output per cell. They also allow registers to be truly buried from I/O pins without limiting them to inputonly (see Figure 8 ).
From Global Cell I/O Cell Clock
Q Best for storage, simple coun ters, shifters and state machines with few hold (loop) conditions.
R
T
P
Q
T R e g is te r Q toggles when T = 1 Q holds when T = 0
REG / Latch Q
R
Best for wide binary counters (saves product terms) and state machines with many hold (loop) conditio ns.
To Array
Input
MUX
J K
P
Q
J K R e g is te r Q toggles when J/K = 1/1 Q holds when J/K = 0/0 Q=1 when J/K = 1/0 Q=0 when J/K = 0/1
R Combines features of both D and T registers. 08-14-005A
From Logic Control Cell
A,B,C or Q
MUX
I/O Pin
MUX
Figure 5. LCC Register Types
SUM-A can serve as the D, T, or J input of the register or a combinatorial path. SUM-B can serve as the K input, or the preset to the register, or a combinatorial path. SUM-C can be the clock, the reset to the register, or a combinatorial path. SUM-D can be the clock to the register or the output enable for the connected I/O cell. Note that the sums controlling clocks, resets, presets and output enables are complete sum-of-product functions, not just product terms as with most other PLDs. This also means that any input or I/O pin can be used as a clock or other control function. Several signals from the global cell are provided primarily for synchronous (global) register control. The global cell signals are routed to all LCCs. These signals include a high-speed clock of positive or negative polarity, global preset and reset, and a special register-type control that selectively allows dynamic switching of register type. This last feature is especially useful for saving product terms when implementing loadable counters and state machines by dynamically switching from D-type registers to load and T-type registers to count (see Figure 10).
D
10 7540 /O Cell (IOC)
08-14-006A
Figure 6. I/O Cell Block Diagram
D Q
IO C R e g is te r
Q = D after rising edge of clo ck holds until next rising ed ge
L
Q
IO C L a tc h Q = L when clock is high holds value when clock is low
08-14-007A
Figure 7. IOC Register Configurations I/O Cell (IOC)
All PEELTM Arrays have I/O cells (IOC) as shown above in Figure 6. Inputs to the IOCs can be fed from any of the LCCs in the array. Each IOC consists of routing and control multiplexers, an input register/transparent latch, a three-state buffer and an output polarity control. The register/ latch can be clocked from a variety of sources determined by the global cell. It can also be bypassed for a non-registered input. The combination of LCC and IOC allows for multiple buried registers and logic paths. (See Figure 8).
Multiple Outputs Per Logic Cell
An important feature of the logic control cell is its capability to have multiple output functions per cell, each operating independently. As shown in Figure 4, two of the three outputs can select the Q output from the register or the Sum A, B or C combinatorial paths. Thus, one LCC output
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G roup A & B
Q
D
Input with optional register/latch
CL K1
MUX
LCC Clocks
I/O
CLK 2 MUX PCL K IO C Clocks
I/O with independent output enable
A B C D
DQ
Reg-Type Preset Reset
LCC Reg-Type LCC Presets LCC Resets
1 2 OE 08-14 -008A
G lobal C ell: LC C & IO C
08-14-009A
Figure 9. Global Cells Figure 8. LCC & IOC With Two Outputs Global Cells
The global cells, shown in Figure 9, are used to direct global clock signals and/or control terms to the LCCs and IOCs. The global cells allow a clock to be selected from the CLK1 pin, CLK2 pin, or a product term from the logic array (PCLK). They also provide polarity control for IOC clocks enabling rising or falling clock edges for input registers/latches. Note that each individual LCC clock has its own polarity control. The global cell includes sum-ofproducts control terms for global reset and preset, and a fast product term control for LCC register-type, used to save product terms for loadable counters and state machines (see Figure 10). The PA7540 provides two global cells that divides the LCC and IOCs into two groups, A and B. Half of the LCCs and IOCs use global cell A, half use global cell B. This means, for instance, two high-speed global clocks can be used among the LCCs.
R e g is te r T yp e C h a ng e F e a tu re
Reg-T ype from G lobal Cell
D
P
Q
R
G lobal Cell can dynamica lly change userse lected LCC registers fro m D to T or from D to JK. This saves product terms for loadable co unters or state machine s. Use as D register to load, use as T or JK to count. Timing allows dynamic operation.
T
P
E x a m p le : Product terms for 10 bit lo adable binary counter
Q D uses 57 product terms (47 count, 10 load) T uses 30 product terms (10 count, 20 load) D/T uses 20 product terms (10 count, 10 load)
R
08-14-010A
Figure 10. Register Type Change Feature
internal signals to be simulated and analyzed via a waveform display.(See Figures 10a-c) PEELTM Array development is also supported by popular development tools, such as ABEL via Anachip's PEELTM Array fitters. A special smart translator utility adds the capability to directly convert JEDEC files for other devices into equivalent JEDEC files for pin-compatible PEELTM Arrays.
PEELTM Array Development Support
Development support for PEELTM Arrays is provided by Anachip and manufacturers of popular development tools. Anachip offers the powerful WinPLACE Development Software (free to qualified PLD designers). The PLACE software includes an architectural editor, logic compiler, waveform simulator, documentation utility and a programmer interface. The PLACE editor graphically illustrates and controls the PEELTM Array's architecture, making the overall design easy to understand, while allowing the effectiveness of boolean logic equations, state machine design and truth table entry. The PLACE compiler performs logic transformation and reduction, making it possible to specify equations in almost any fashion and fit the most logic possible in every design. PLACE also provides a multi-level logic simulator allowing external and
Programming
PEELTM Arrays are EE-reprogrammable in all package types, plastic-DIP, PLCC and SOIC. This makes them an ideal development vehicle for the lab. EE reprogrammability is also useful for production, allowing unexpected changes to be made quickly and without
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waste. Programming of PEELTM Arrays is supported by many popular third party programmers.
Design Security and Signature Word
The PEELTM Arrays provide a special EEPROM security bit that prevents unauthorized reading or copying of designs. Once set, the programmed bits of the PEELTM Arrays cannot be accessed until the entire chip has been electrically erased. Another programming feature, signature word, allows a user-definable code to be programmed into the PEELTM Array. The code can be read back even after the security bit has been set. The signature word can be used to identify the pattern programmed in the device or to record the design revision.
Figure 12 - WinPLACE LCC and IOC screen
Figure 11 - WinPLACE Architectural Editor for PA7540
Figure 13 - WinPLACE waveform and simulator screen
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Table 1. Absolute Maximum Ratings
Symbol
VCC VI, VO IO TST TLT
Parameter
Supply Voltage Voltage Applied to Any Pin Output Current Storage Temperature Lead Temperature
Conditions
Relative to Ground Relative to Ground Per pin (IOL, IOH) Soldering 10 seconds
1
Ratings
-0.5 to + 7.0 -0.5 to VCC + 0.6 25 -65 to + 150 +300
Unit
V V mA C C
Table 2. Operating Ranges
Symbol
VCC TA TR TF TRVCC
Parameter
Supply Voltage Ambient Temperature Clock Rise Time Clock Fall Time VCC Rise Time
Conditions
Commercial Industrial Commercial Industrial See Note 2 See Note 2 See Note 2
Min
4.75 4.5 0 -40
Max
5.25 5.5 +70 +85 20 20 250
Unit
V C ns ns ms
Table 3. D.C. Electrical Characteristics
Symbol
VOH VOHC VOL VOLC VIH VIL IIL IOZ ISC ICC11 CIN7 COUT7
Over the Operating Range
Conditions Min
2.4 VCC - 0.3 0.5 0.15 2.0 -0.3 VCC + 0.3 0.8 10 10 -30 -15 I-15 55 (typ.)18 -120 80 mA 90 6 pF pF
Parameter
Output HIGH Voltage - TTL Output HIGH Voltage CMOS Output LOW Voltage - TTL Output LOW Voltage CMOS Input HIGH Level Input LOW Level Input Leakage Current Output Leakage Current Output Short Circuit Current4 VCC Current Input Capacitance5 Output Capacitance5
Max
Unit
V V V V V V A A mA
VCC = Min, IOH = -4.0mA VCC = Min, IOH = -10A VCC = Min, IOL = 16mA VCC = Min, IOL = -10A
VCC = Max, GND VIN VCC I/O = High-Z, GND VO VCC VCC = 5V, VO = 0.5V, TA= 25C VIN = 0V or VCC3,11 f = 25MHz All outputs disabled4
TA = 25C, VCC = 5.0V @ f = 1 MHz 12
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Table 4. A.C Electrical Characteristics Combinatorial
Symbol
tPDI tPDX tIA tAL tLC tLO tOD, tOE tOX
Over the Operating Range
-15/I-15 Min Max
10 15 2 9 1 3 3 15
Parameter
Propagation delay Internal (tAL + tLC) Propagation delay External (tIA + tAL +tLC + tLO) Input or I/O pin to array input Array input to LCC LCC input to LCC output10 LCC output to output pin Output Disable, Enable from LCC output7 Output Disable, Enable from input pin7
6,12
Unit
ns ns ns ns ns ns ns ns
This device has been designed and tested for the recommended operating conditions. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage
Figure 14. Combinatorial Timing - Waveforms and Block Diagram
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Table 5. A.C. Electrical Characteristics Sequential
Symbol
tSCI tSCX tCOI tCOX tHX tSK tAK tHK tSI tHI tPK tSPI tHPI tCK tCW fMAX1 fMAX2 fMAX3 fMAX4 fTGL tPR tST tAW tRT tRTV tRTC tRW tRESET
Parameter
8 14
6,1
-15/I-15 Min
6 8 8 12 0 3 1 4 0 4 6 0 5 7 7 71.4 62.5 55.5 50.0 71.4 1 12 8 6 1 7 10
2
Max
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns s
Internal set-up to system clock - LCC (tAL + tSK + tLC - tCK) Input16 (EXT.) set-up to system clock, - LCC (tIA + tSCI) System-clock to Array Int. - LCC/IOC/INC14 (tCK +tLC) System-clock to Output Ext. - LCC (tCOI + tLO) Input hold time from system clock - LCC LCC Input set-up to async. clock - LCC Clock at LCC or IOC - LCC output LCC input hold time from system clock - LCC Input set-up to system clock - IOC/INC (tSK - tCK) Input hold time from system clock - IOC/INC (tSK - tCK) Array input to IOC PCLK clock Input set-up to PCLK clock - IOC/INC (tSK-tPK-tIA) Input hold from PCLK clock17 - IOC/INC (tPK+tIA-tSK) System-clock delay to LCC/IOC/INC System-clock low or high pulse width Max. system-clock frequency Int/Int 1/(tSCI + tCOI) Max. system-clock frequency Ext/Int 1/(tSCX + tCOI) Max. system-clock frequency Int/Ext 1/(tSCI + tCOX) Max. system-clock frequency Ext/Ext 1/(tSCX + tCOX) Max. system-clock toggle frequency 1/(tCW + tCW) LCC presents/reset to LCC output Input to Global Cell present/reset (tIA + tAL + tPR) Asynch. preset/reset pulse width Input to LCC Reg-Type (RT) LCC Reg-Type to LCC output register change Input to Global Cell register-type change (tRT + tRTV) Asynch. Reg-Type pulse width Power-on reset time for registers in clear state
9 17 14 13
5
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Figure 15. Sequential Timing - Waveforms and Block Diagram
Notes
1. Minimum DC input is -0.5V, however inputs may under-shoot to -2.0V for periods less than 20ns. 2.Test points for Clock and VCC in tR,tF,tCL,tCH, and tRESET are referenced at 10% and 90% levels. 3. I/O pins are 0V or VCC. 4. Test one output at a time for a duration of less than 1 sec. 5. Capacitances are tested on a sample basis. 6. Test conditions assume: signal transition times of 5ns or less from the 10% and 90% points, timing reference levels of 1.5V (unless otherwise specified). 7. tOE is measured from input transition to VREF 0.1V (See test loads at end of Section 6 for VREF value). tOD is measured from input transition to VOH -0.1V or VOL +0.1V. 8. DIP: "System-clock" refers to pin 1/13 high speed clocks. PLCC: "System-clock" refers to pin 2/16 high speed clocks. 9. For T or JK registers in toggle (divide by 2) operation only. 10. For combinatorial and async-clock to LCC output delay. 11. ICC for a typical application: This parameter is tested with the device programmed as a 10-bit D-type counter. 12. Test loads are specified in Section 5 of the Data Book. 13. "Async. Clock" refers to the clock from the Sum term (OR gate). 14. The "LCC" term indicates that the timing parameter is applied to the LCC register. The "LCC/IOC" term indicates that the timing parameter is applied to both the LCC and IOC registers. 16. The term "input" without any reference to another term refers to an (external) input pin. 17. The parameter tSPI indicates that the PCLK signal to the IOC register is always slower than the data from the pin or input by the absolute value of (tSK -tPK -tIA). This means that no set-up time for the data from the pin or input is required, i.e. the external data and clock can be sent to the device simultaneously. Additionally, the data from the pin must remain stable for tHPI time, i.e. to wait for the PCLK signal to arrive at the IOC register. 18. Typical (typ) ICC is measured at TA = 25 C, freq = 25MHZ, VCC = 5V
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Table 6. Ordering Information
Part Number
PA7540P-15 PA7540J-15 PA7540JN-15 PA7540S-15 PA7540PI-15 PA7540JI-15 PA7540JNI-15 PA7540SI-15
Speed
10/15ns
Temperature
C
Package
P24 J28 JN28 S24 P24 J28 JN28 S24
10/15ns
I
Figure 16. Part Number
Device Suffix
P A7540J-15
P ackag e
P = 300m il DIP J = Plastic (J) Leaded Chip Carrier (PLCC) JN = PLCC Alternate Pin Out S = SOIC 300 m il Gullwing
S peed
-15 = 10ns/15ns tpd/tpdx
Tem perature R ange
(Blank) = Com m ercial 0 to 70 C I = Industrial -40 to +85 C
08-14--016A
Anachip USA, Inc. 780 Montague Expressway, #201 San Jose, CA 95131 TEL (408) 321-9600 FAX (408) 321-9696 (c)2002 Anachip Corp. Anachip reserves the right to make changes in specifications at any time and without notice. The information furnished by Anachip in this publication is believed to be accurate and reliable. However, there is no responsibility assumed by Anachip for its use nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Anachip. Anachip's products are not authorized for use as critical components in life support devices or systems. (c) Marks bearing or TM are registered trademarks and trademarks of Anachip Corp. Email: Sales_usa@anachip.com Website: http://www.anachip.com
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