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| E2G1049-18-33 Semiconductor MSM56V16160D/DH Semiconductor ThisMSM56V16160D/DH version: Mar. 1998 Pr el im in ar y 2-Bank 524,288-Word 16-Bit SYNCHRONOUS DYNAMIC RAM DESCRIPTION The MSM56V16160D/DH is a 2-bank 524,288-word 16-bit synchronous dynamic RAM, fabricated in Oki's CMOS silicon-gate process technology. The device operates at 3.3 V. The inputs and outputs are LVTTL compatible. FEATURES * * * * * * * Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell 2-bank 524,288-word 16-bit configuration 3.3 V power supply, 0.3 V tolerance Input : LVTTL compatible Output : LVTTL compatible Refresh : 4096 cycles/64 ms Programmable data transfer mode - CAS latency (1, 2, 3) - CAS latency (2, 3)*1 - Burst length (1, 2, 4, 8, full page) - Burst length (1, 2, 4, 8)*1 - Data scramble (sequential, interleave) *1 : H version only. * CBR auto-refresh, Self-refresh capability * Package: 50-pin 400 mil plastic TSOP (Type II) (TSOPII50-P-400-0.80-K) (Product : MSM56V16160D/DH-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family MSM56V16160D-10 MSM56V16160D-12 MSM56V16160DH-15 Max. Frequency 100 MHz 83 MHz 66 MHz Access Time (Max.) tAC2 9 ns 14 ns 9 ns tAC3 9 ns 10 ns 9 ns 1/30 Semiconductor PIN CONFIGURATION (TOP VIEW) VCC DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 DQ8 VCCQ LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 MSM56V16160D/DH 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 VSS 49 DQ16 48 DQ15 47 VSSQ 46 DQ14 45 DQ13 44 VCCQ 43 DQ12 42 DQ11 41 VSSQ 40 DQ10 39 DQ9 38 VCCQ 37 NC 36 UDQM 35 CLK 34 CKE 33 NC 32 A9 31 A8 30 A7 29 A6 28 A5 27 A4 26 VSS 50-Pin Plastic TSOP (II) (K Type) Pin Name CLK CS CKE A0 - A10 A11 RAS CAS WE Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Pin Name DQi VCC VSS VCCQ VSSQ NC Function Data Input/Output Power Supply (3.3 V) Ground (0 V) Data Output Power Supply (3.3 V) Data Output Ground (0 V) No Connection UDQM, LDQM Data Input/Output Mask Note: The same power supply voltage must be provided to every VCC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin. 2/30 Semiconductor MSM56V16160D/DH PIN DESCRIPTION CLK CS CKE Fetches all inputs at the "H" edge. Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, UDQM and LDQM. Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Address Row & column multiplexed. Row address: RA0 - RA10 Column address: CA0 - CA7 A11 RAS CAS WE UDQM, LDQM Masks the read data of two clocks later when UDQM and LDQM are set "H" at the "H" edge of the clock signal. Masks the write data of the same clock when UDQM and LDQM are set "H" at the "H" edge of the clock signal. UDQM controls upper byte and LDQM controls lower byte. DQi Data inputs/outputs are multiplexed on the same pin. Functionality depends on the combination. For details, see the function truth table. Selects bank to be activated during row address latch time and selects bank for precharge and read/ write during column address latch time. A11 = "L" : Bank A, A11 = "H" : Bank B 3/30 Semiconductor BLOCK DIAGRAM CKE CLK CS RAS CAS WE UDQM LDQM MSM56V16160D/DH Timing Register Programing Register Latency & Burst Controller I/O Controller Bank Controller A11 A0 A11 Internal Col. Address Counter Input Data Register 8 Input Buffers 16 16 8 Column Address Buffers Column Decoders Sense Amplifier Internal Row Address Counter 16 Read Data Register 16 16 Output Buffers DQ1 DQ16 Row Decoders Word Drivers 8Mb Memory Cells 8Mb Memory Cells 12 Row Address Buffers 12 Row Decoders Word Drivers Sense Amplifier Column Decoders 4/30 Semiconductor MSM56V16160D/DH ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS VCC Supply Voltage Storage Temperature Power Dissipation Short Circuit Current Operating Temperature Symbol VIN, VOUT VCC, VCCQ Tstg PD* IOS Topr Rating -0.5 to VCC + 0.5 -0.5 to 4.6 -55 to 150 600 50 0 to 70 (Voltages referenced to VSS) Unit V V C mW mA C *: Ta = 25C Recommended Operating Conditions Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC, VCCQ VIH VIL Min. 3.0 2.0 -0.3 Typ. 3.3 -- -- (Voltages referenced to VSS = 0 V) Max. 3.6 VCC + 0.2 0.8 Unit V V V Capacitance (VCC = 3.3 V 0.3 V, Ta = 25C, f = 1 MHz) Parameter Input Capacitance (A0 - A11) Input Capacitance (CLK, CKE, CS, RAS, CAS, WE, UDQM, LDQM) Input/Output Capacitance (DQ1 - DQ16) Symbol CIN1 CIN2 COUT Min. 2 2 2 Max. 5 5 7 Unit pF pF pF 5/30 Semiconductor DC Characteristics Condition Parameter Symbol Bank -- -- -- -- One Bank Active CKE -- -- -- -- Others IOH = -2 mA IOL = 2 mA -- -- MSM56V16160D/DH Output High Voltage VOH Output Low Voltage Input Leakage Current Output Leakage Current VOL ILI ILO ICC1 Average Power Supply Current (Operating) Version D-10 D-12 DH-15 Unit Note Min. Max. Min. Max. Min. Max. 2.4 -- 2.4 -- 2.4 -- V -- 0.4 -- 0.4 -- 0.4 V mA mA -10 10 -10 10 -10 10 -10 10 -10 10 -10 10 -- 80 -- 70 -- CKE VIH tCC = min tRC = min No Burst CKE VIH tCC = min tRC = min tRRD = min No Burst CKE VIH tCC = min CKE VIL tCC = min 60 mA 1, 2 ICC1D Both Banks Active -- 115 -- 95 -- 80 mA 1, 2 Power Supply Current (Stand by) ICC2 Both Banks Precharge -- 35 -- 30 -- 25 mA 3 Average Power ICC3S Both Banks Active Supply Current (Clock Suspension) Average Power Supply Current (Active Stand by) Power Supply Current (Burst) Power Supply Current (Auto-Refresh) Average Power Supply Current (Self-Refresh) Average Power Supply Current (Power down) ICC3 One Bank Active Both Banks Active One Bank Active Both Banks Precharge Both Banks Precharge -- CKE VIH tCC = min -- CKE VIH tCC = min CKE VIH tCC = min tRC = min CKE VIL tCC = min -- CKE VIL tCC = min -- 3 -- 3 -- 3 mA 2 40 -- 35 -- 30 mA 3 ICC4 ICC5 -- 100 -- 85 -- 70 mA 1, 2 -- 80 -- 70 -- 60 mA 2 ICC6 2 -- 2 -- 2 mA ICC7 2 -- 2 -- 2 mA Notes: 1. Measured with outputs open. 2. The address and data can be changed once or left unchanged during one cycle. 3. The address and data can be changed once or left unchanged during two cycles. 6/30 Semiconductor MSM56V16160D/DH Mode Set Address Keys CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CL Reserved 1*2 2 3 Reserved Reserved Reserved Reserved 0 1 Burst Type A3 BT Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 0 1 0 1 0 1 0 1 BT = 0 1 2 4 8 BT = 1 1 2 4 8 Reserved Reserved Reserved Reserved Reserved Reserved Full Page*2 Reserved *2 : Not applicable to H version. Note: A7, A8, A9, A10 and A11 should stay "L" during mode set cycle. POWER ON SEQUENCE 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200 ms or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply a CBR auto-refresh eight or more times. 5. Enter the mode register setting command. 7/30 Semiconductor AC Characteristics Parameter CL = 3 Clock Cycles Time CL = 2 CL = 1 CL = 3 Access Time from CL = 2 Clock CL = 1 Clock "H" Pulse Time Clock "L" Pulse Time Input Setup Time Input Hold Time Output Low Impedance Time from Clock Output High Impedance Time from Clock Output Hold from Clock RAS Cycle Time RAS Precharge Time RAS Active Time RAS to CAS Delay Time Write Recovery Time RAS to RAS Bank Active Delay Time Refresh Time Power-down Exit Set-up Time Input Level Transition Time CAS to CAS Delay Time (Min.) Clock Disable Time from CKE Data Output High Impedance Time from UDQM, LDQM Data Input Mask Time from UDQM, LDQM Data Input Time from Write Command Data Output High Impedance Time from Precharge Command MSM56V16160D/DH Note 1, 2 Symbol MSM56V16160D-10 MSM56V16160D-12 MSM56V16160DH-15 Min. 10 tCC 15 30 -- tAC tCH tCL tSI tHI tOLZ tOHZ tOH tRC tRP tRAS tRCD tWR tRRD tREF tT lCCD lCKE lDOZ lDOD lDWD lROH lMRD lOWD -- -- 3 3 3 1 3 -- 3 100 30 60 30 15 20 -- -- 1 1 2 0 0 1 2 3 2 Max. -- -- -- 9 9 27 -- -- -- -- -- 8 -- -- -- 105 -- -- -- 64 -- 3 Min. 12 17.5 35 -- -- -- 3 3 3 1 3 -- 3 115 35 70 35 24 24 -- tSI + 1 CLK -- 1 1 2 0 0 1 2 3 2 Max. -- -- -- 10 14 30 -- -- -- -- -- 10 -- -- -- 105 -- -- -- 64 -- 3 Min. 15 15 -- -- -- -- 3 3 3 1 3 -- 3 105 30 70 30 15 24 -- tSI + 1 CLK -- 1 1 2 0 0 -- 2 3 2 Max. -- -- -- 9 9 -- -- -- -- -- -- 8 -- -- -- 105 -- -- -- 64 -- 3 Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle 3 3, 4 3, 4 3, 4 tPDE tSI + 1 CLK CL = 1 CL > 1 Active Command Input Time from Mode Register Set Command Input (Min.) Write Command Input Time from Output 8/30 Semiconductor MSM56V16160D/DH Notes : 1. AC measurements assume that tT = 1 ns and VIH/VIL = 2.0 V/0.8 V. 2. The reference level for timing of input signals is 1.4 V. 3. Output load. 1.4 V Z = 50 W Output 50 pF 50 W 4. The access time is defined at 1.4 V. 5. If tT is longer than 1 ns, then the reference level for timing of input signals is VIH and VIL. 9/30 Semiconductor TIMING WAVEFORM Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM, LDQM , , ,, , MSM56V16160D/DH 16 17 18 19 tRC tRP tRCD Ra Ca0 Rb Cb0 Ra Rb tOH Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 tAC tOHZ tWR Row Active Read Command Row Active Write Command Precharge Command Precharge Command 10/30 Semiconductor MSM56V16160D/DH Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 2, Burst Length = 4 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK ,,, ,, tCC tCL CKE CS High tHI tSI RAS tSI tHI lCCD CAS tSI tSI tSI ADDR Ra Ca Cb Cc tHI tHI A11 BS BS BS BS BS A10 DQ Ra tAC tHI Qa Db Qc tOLZ tSI tOH tHI tOHZ lOWD WE tSI UDQM, LDQM Row Active Write Command Precharge Command Read Command Read Command 11/30 Semiconductor *Notes: MSM56V16160D/DH 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CKE, UDQM, and LDQM are invalid. 2. When issuing an active, read or write command, the bank is selected by A11. A11 0 1 Active, read or write Bank A Bank B 3. The auto precharge function is enabled or disabled by the A10 input when the read or write command is issued. A10 0 1 0 1 A11 0 0 1 1 Operation After the end of burst, bank A holds the idle status. After the end of burst, bank A is precharged automatically. After the end of burst, bank B holds the idle status. After the end of burst, bank B is precharged automatically. 4. When issuing a precharge command, the bank to be precharged is selected by the A10 and A11 inputs. A10 0 0 1 A11 0 1 X Operation Bank A is precharged. Bank B is precharged. Both banks A and B are precharged. 5. The input data and the write command are latched by the same clock (Write latency = 0). 6. The output is forced to high impedance by (1 CLK + tOHZ) after UDQM, LDQM entry. 12/30 Semiconductor MSM56V16160D/DH Page Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM, LDQM *Notes: , , , , ,, ,, , , , 17 18 19 High Bank A Active lCCD Ca0 Cb0 Cc0 Cd0 Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 lOWD tWR *Note2 *Note1 Read Command Read Command Write Command Write Command Precharge Command 1. To write data before a burst read ends, UDQM and LDQM should be asserted three cycles prior to the write command to avoid bus contention. 2. To assert row precharge before a burst write ends, wait tWR after the last write data input. Input data during the precharge input cycle will be masked internally. 13/30 ,,,, , , ,, , , Semiconductor MSM56V16160D/DH Read & Write Cycle with Auto Precharge @ Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS High RAS tRRD CAS ADDR Ra Rb Ca Cb A11 A10 WE Ra Rb CAS Latency = 1 *Note1 DQ Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 UDQM, LDQM A-Bank Precharge Start CAS Latency = 2 DQ Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 UDQM, LDQM A-Bank Precharge Start CAS Latency = 3 DQ Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 A-Bank Precharge Start tWR UDQM, LDQM Row Active (A-Bank) A Bank Read with Auto Precharge Row Active (B-Bank) B Bank Write with Auto Precharge B Bank Precharge Start Point *Note: 1. Not applicable to H version. 14/30 Semiconductor Bank Interleave Random Row Read Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM, LDQM , , , , , ,, MSM56V16160D/DH 18 19 High tRC tRRD RAa CAa RBb CBb RAc CAc RAa RBb RAc QAa0 QAa1 QAa2 QAa3 QBb1 QBb2 QBb3 QBb4 QAc0 QAc1 QAc2 QAc3 Row Active (A-Bank) Read Command (A-Bank) Read Command (B-Bank) Read Command (A-Bank) Row Active (B-Bank) Precharge Command (A-Bank) Precharge Command (B-Bank) Row Active (A-Bank) 15/30 Semiconductor MSM56V16160D/DH ,, , , ,, ,, , 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Bank Interleave Random Row Write Cycle @ CAS Latency = 2, Burst Length = 4 CLK CKE CS High RAS CAS ADDR RAa CAa RBb CBb RAc CA A11 A10 DQ RAa RBb RAc DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 WE UDQM, LDQM Row Active (A-Bank) Row Active (B-Bank) Write Command (A-Bank) Precharge Command (A-Bank) Write Command (B-Bank) Write Command (A-Bank) Row Active (A-Bank) Precharge Command (A-Bank) Precharge Command (B-Bank) 16/30 Semiconductor Bank Interleave Page Read Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM, LDQM *Note: , ,,, , , MSM56V16160D/DH 16 17 18 19 High *Note1 RAa CAa RBb CBb CAc CBd CAe RAa RAa QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 lROH Row Active (A-Bank) Row Active (B-Bank) Read Command (B-Bank) Precharge Command (A-Bank) Read Command (A-Bank) Read Command (B-Bank) Read Command (A-Bank) Read Command (A-Bank) 1. CS is ignored when RAS, CAS and WE are high at the same cycle. 17/30 , ,, , , , , ,, , Semiconductor MSM56V16160D/DH Bank Interleave Page Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS High RAS CAS ADDR RAa CAa RBb CBb CAc CBd A11 A10 DQ RAa RAb DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 WE UDQM, LDQM Row Active (A-Bank) Row Active (B-Bank) Write Command (B-Bank) Write Command (A-Bank) Write Command (B-Bank) Write Command (A-Bank) Precharge Command (Both Bank) 18/30 Semiconductor MSM56V16160D/DH ,,, , , Bank Interleave Random Row Read/Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS High RAS CAS ADDR RAa CAa RBb CBb RAc CAc A11 A10 DQ RAa RBb RAc QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2 QAc3 WE UDQM, LDQM Row Active (A-Bank) Row Active (B-Bank) Write Command (B-Bank) Read Command (A-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Row Active (A-Bank) 19/30 Semiconductor MSM56V16160D/DH Bank Interleave Page Read/Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM, LDQM ,, , ,, , , High CAa0 CBb0 CAc0 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2 QAc3 Read Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank) 20/30 Semiconductor MSM56V16160D/DH Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 *Note1 *Note1 CKE CS RAS CAS ADDR Ra Ca Cb Cc A11 A10 DQ0 - 7 Ra Qa0 Qa1 Qa2 Qb0 Qb1 Dc0 Dc2 *Note4 DQ8 - 15 tOHZ tOHZ *Note3 Dc1 Qa0 Qa2 Qa3 Qb0 Qb1 Dc0 *Note2 WE LDQM *Note4 UDQM Row Active Read Command Read DQM CLOCK Suspension Read Command Read DQM Read DQM Write Command Write DQM CLK *Notes: , , ,, , ,, CLOCK Suspension Write DQM 1. 2. 3. 4. When Clock Suspension is asserted, the next clock cycle is ignored. When LDQM and UDQM are asserted, the read data after two clock cycles is masked. When LDQM and UDQM are asserted, the write data in the same clock cycle is masked. When LDQM is set High, the input/output data of DQ0 - DQ7 is masked. When UDQM is set High, the input/output data of DQ8 - DQ15 is masked. 21/30 Semiconductor Read to Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM, LDQM *Note: ,, , , ,, MSM56V16160D/DH 16 17 18 19 *Note1 tRCD Ra Ca0 Ca0 Ra Da0 Da1 Da2 Da3 tWR Row Active Read Command Precharge Command Write Command 1. In case CAS latency is 3, READ can be interrupted by WRITE. The minimum command interval is [burst length + 1] cycles. UDQM, LDQM must be high at least 3 clocks prior to the write command. 22/30 Semiconductor Read Interruption by Precharge Command @ Burst Length = 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 MSM56V16160D/DH CLK CKE CS RAS CAS ADDR A11 A10 WE CAS Latency = 1 *Note3 DQ UDQM, LDQM CAS Latency = 2 DQ UDQM, LDQM CAS Latency = 3 DQ UDQM, LDQM *Notes: ,, ,,, ,, , ,, , ,, 14 15 16 17 18 19 High Ra Ca Ra *Note1 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 *Note2 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 *Note2 Qa0 Qa1 Qa2 Qa3 Qa4 Row Active Read Command Precharge Command 1. When the CAS latency = 1, and if row precharge is asserted before a burst read ends, then the read data will not output after the next clock cycle of the precharge command. 2. When the CAS latency = 2 or 3, and if row precharge is asserted before burst read ends, then the read data will not output after the second clock cycle of the precharge command. 3. Not applicable to H version. 23/30 , ,, , , , Semiconductor MSM56V16160D/DH Power Down Mode @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tSI *Note1 tPDE *Note2 tSI CKE CS tSI RAS CAS ADDR Ra Ca A11 A10 DQ Ra Qa0 Qa1 Qa2 WE UDQM, LDQM Row Active Power-down Entry Power-down Exit Clock Suspention Entry Clock Suspention Exit Read Command Precharge Command *Notes: 1. When both banks are in precharge state, and if CKE is set low, then the MSM56V16160D/DH enters power-down mode and maintains the mode while CKE is low. 2. To release the circuit from power-down mode, CKE has to be set high for longer than tPDE (tSI + 1 CLK). 24/30 Semiconductor Self Refresh Cycle 0 1 2 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM, LDQM , , ,,, , MSM56V16160D/DH tRC tSI Ra BS Ra Hi - Z Hi - Z Self Refresh Entry Self Refresh Exit Row Active 25/30 Semiconductor Mode Register Set Cycle 0 1 2 3 4 5 6 MSM56V16160D/DH Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 CLK CKE CS RAS CAS ADDR DQ WE UDQM, LDQM ,, , ,, , High High lMRD tRC key Ra Hi - Z Hi - Z MRS New Command Auto Refresh Auto Refresh 26/30 Semiconductor MSM56V16160D/DH FUNCTION TRUTH TABLE (Table 1) (1/2) Current State1 CS RAS CAS WE BA Idle H L L L L L L L Row Active H L L L L L L Read H L L L L L L L Write H L L L L L L L Read with Auto Precharge H L L L L L L Write with Auto Precharge H L L L L L L X H H H L L L L X H H H L L L X H H H H L L L X H H H H L L L X H H H H L L X H H H H L L X H H L H H L L X H L L H H L X H H L L H H L X H H L L H H L X H H L L H L X H H L L H L X H L X H L H L X X H L H L X X H L H L H L X X H L H L H L X X H L H L X X X H L H L X X X X BA BA BA BA X L X X BA BA BA BA X X X BA BA BA BA BA X X X BA BA BA BA BA X X X BA BA X BA X X X BA BA X BA X ADDR X X X CA RA A10 X OP Code X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 X RA, A10 X X X X CA, A10 X RA, A10 X NOP NOP ILLEGAL 2 ILLEGAL 2 Row Active NOP 4 Auto-Refresh or Self-Refresh 5 Mode Register Write NOP NOP Read Write ILLEGAL 2 Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Reserved Term Burst, start new Burst Read Term Burst, start new Burst Write ILLEGAL 2 Term Burst, execute Row Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) ILLEGAL 2 Term Burst, start new Burst Read Term Burst, start new Burst Write ILLEGAL 2 Term Burst, execute Row Precharge ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL Action 27/30 Semiconductor MSM56V16160D/DH FUNCTION TRUTH TABLE (Table 1) (2/2) Current State1 CS RAS CAS WE BA Precharge H L L L L L L Write Recovery H L L L L L L Row Active H L L L L L L Refresh H L L L L Mode Register Access H L L L L ABBREVIATIONS RA = Row Address CA = Column Address Notes: X H H H L L L X H H H L L L X H H H L L L X H H L L X H H H L X H H L H H L X H H L H H L X H H L H H L X H L H L X H H L X X H L X H L X X H L X H L X X H L X H L X X X X X X X H L X X X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X X X X X X X X X X ADDR X X X CA RA A10 X X X X CA RA A10 X X X X CA RA A10 X X X X X X X X X X X NOP --> Idle after tRP NOP --> Idle after tRP ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 NOP 4 ILLEGAL NOP NOP ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL NOP --> Row Active after tRCD NOP --> Row Active after tRCD ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL NOP --> Idle after tRC NOP --> Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL Action BA = Bank Address AP = Auto Precharge NOP = No OPeration command 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of tCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle. 28/30 Semiconductor MSM56V16160D/DH FUNCTION TRUTH TABLE for CKE (Table 2) Current State (n) CKEn-1 Self Refresh H L L L L L L Power Down H L L L L L L All Banks Idle (ABI) 6 CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L CS RAS CAS WE X H L L L L X X H L L L L X X H L L L L L L X X X X X X X H H H L X X X H H H L X X X H H H L L L X X X X X X X H H L X X X X H H L X X X X H H L H L L X X X X X X X H L X X X X X H L X X X X X H L X L H L X X X X X ADDR X X X X X X X X X X X X X X X X X X X X X X X X X X X INVALID Action Exit Self Refresh --> ABI Exit Self Refresh --> ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down --> ABI Exit Power Down --> ABI ILLEGAL ILLEGAL ILLEGAL 6 NOP (Continue power down mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table 1 Begin Clock Suspend Next Cycle Enable Clock of Next Cycle Continue Clock Suspension H H H H H H H H L Any State Other than Listed Above H H L L Note: 6. Power-down and self refresh can be entered only when all the banks are in an idle state. 29/30 Semiconductor MSM56V16160D/DH PACKAGE DIMENSIONS (Unit : mm) TSOPII50-P-400-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.61 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 30/30 |
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