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| ina elim Pr c. Spe ry MITSUBISHI LSIs Rev. 1.0 Oct./4/95 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM MH1M144CXTJ-6 DESCRIPTION The MH1M144CXTJ is 1048576-word by 144-bit dynamic RAM module. This consists of nine industry standard 1Mx16 dynamic RAMs in TSOP and one industry standard input buffer in T-SSOP. The mounting of TSOP on a card edge Dual Read Out package provides any application where high densities and large quantities of memory are required. This is a socket type - memory modules, suitable for easy interchange or addition of modules. 2pin 100pin 102pin FEATURES access access time time (max.ns) (max.ns) RAS CAS Address Cycle access time (max.ns) time (min.ns) -6 65 20 35 110 single 5V5% supply All input, output TTL compatible and low capacitance 1024 refresh cycle every 16.4ms(A0~A9) Includes decoupling capacitor(0.22Fx19) 99pin APPLICATION Main memory unit for computer,Microcomputer memory MITSUBISHI ELECTRIC ( 1 /14 ) 200pin 199pin 101pin 1pin ina elim Pr c. Spe ry MITSUBISHI LSIs Rev. 1.0 Oct./4/95 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM MH1M144CXTJ-6 BLOCK DIAGRAM 10 ohm /WE /CAS1 Input Buffer : ABT16244 OR SAME EQUIPMENT /CAS0 /RAS0 D0 D1 D2 D3 D32 D33 D34 D35 D8 D9 D10 D11 D40 D41 D42 D43 D7 D6 D5 D4 D39 D38 D37 D36 D15 D14 D13 D12 D47 D46 D45 D44 D16 D17 D18 D19 D48 D49 D50 D51 D24 D25 D26 D27 D56 D57 D58 D59 D23 D22 D21 D20 D55 D54 D53 D52 D31 D30 D29 D28 D63 D62 D61 D60 CBW0 CBW1 CBW2 CBW3 CBW4 CBW5 CBW6 CBW7 A0-A9 VCC /RAS /UCAS /WE /OE & /LCAS /OE /WE /UCAS /RAS & /LCAS M5M418160CTP IC1 M5M418160CTP IC6 D64 D65 D66 D67 D96 D97 D98 D99 D72 D73 D74 D75 D104 D105 D106 D107 D71 D70 D69 D68 D103 D102 D101 D100 D79 D78 D77 D76 D111 D110 D109 D108 D80 D81 D82 D83 D112 D113 D114 D115 D88 D89 D90 D91 D120 D121 D122 D123 D87 D86 D85 D84 D119 D118 D117 D116 D95 D94 D93 D92 D127 D126 D125 D124 CBW8 CBW9 CBW10 CBW11 CBW12 CBW13 CBW14 CBW15 /RAS /UCAS /WE /OE & /LCAS /OE /WE /UCAS /RAS & /LCAS M5M418160CTP IC2 M5M418160CTP IC7 /RAS /UCAS /WE /OE & /LCAS /OE /WE /UCAS /RAS & /LCAS M5M418160CTP IC3 M5M418160CTP IC8 /RAS /UCAS /WE /OE & /LCAS /OE /WE /UCAS /RAS & /LCAS M5M418160CTP IC4 M5M418160CTP IC9 /RAS /LCAS /WE /OE DQ1 - DQ8 /UCAS M5M418160CTP IC5 DQ9 - DQ16 IC1 to IC9 IC1 to IC9 VSS BUffer 0.22uF x2 per each IC 0.22uF MITSUBISHI ELECTRIC ( 2 /14 ) ina elim Pr c. Spe ry MITSUBISHI LSIs Rev. 1.0 Oct./4/95 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM MH1M144CXTJ-6 PIN NAME VSS VSS A6 A7 A8 A9 NC NC NC WE NC NC VSS VSS VSS VSS CBW8 CBW15 VCC VCC CBW9 CBW14 CBW10 CBW13 CBW11 CBW12 D64 D71 D65 D70 D66 D69 D67 D68 VSS VSS D96 D103 D97 D102 D98 D101 D99 D100 D72 D79 D73 D78 D74 D77 PIN NO. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PIN NAME VCC VCC D75 D76 D104 D111 D105 D110 D106 D109 D107 D108 D80 D87 D81 D86 VSS VSS D82 D85 D83 D84 D112 D119 D113 D118 D114 D117 D115 D116 D88 D95 VCC VCC D89 D94 D90 D93 D91 D92 D120 D127 D121 D126 D122 D125 D123 D124 VSS VSS PIN CONFIGURATION PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PIN NAME VSS VSS D0 D7 D1 D6 D2 D5 D3 D4 D32 D39 D33 D38 D34 D37 VCC VCC D35 D36 D8 D15 D9 D14 D10 D13 D11 D12 D40 D47 D41 D46 VSS VSS D42 D45 D43 D44 D16 D23 D17 D22 D18 D21 D19 D20 D48 D55 VCC VCC PIN NO. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PIN NAME D49 D54 D50 D53 D51 D52 D24 D31 D25 D30 D26 D29 D27 D28 VSS VSS D56 D63 D57 D62 D58 D61 D59 D60 CBW0 CBW7 CBW1 CBW6 CBW2 CBW5 VCC VCC CBW3 CBW4 CAS0 CAS1 RAS0 NC NC NC NC NC A0 A1 A2 A3 A4 A5 VSS VSS PIN NO. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 MITSUBISHI ELECTRIC ( 3 /14 ) ina elim Pr c. Spe FUNCTION ry MITSUBISHI LSIs Rev. 1.0 Oct./4/95 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM MH1M144CXTJ-6 The MH1M144CXTJ provide, in addition to normal read, write operation, a number of other functions, e.g., fast page mode, RASonly refresh.The input conditions for each are shown in Table 1. Table 1. Input conditions for each mode Inputs Operation RAS Read Write (Early write) RAS-only refresh Hidden refresh CAS before RAS refresh Standby ACT ACT ACT ACT ACT NAC CAS ACT ACT NAC ACT ACT DNC W NAC ACT DNC NAC DNC DNC Row address APD APD APD DNC DNC DNC Column address APD APD DNC DNC DNC DNC Input/Output Refresh Input OPN APD DNC OPN DNC DNC Output VLD OPN OPN VLD OPN OPN YES YES YES YES YES NO Fast page mode identical Remark Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid,APD : applied, OPN : open MITSUBISHI ELECTRIC ( 4 /14 ) ina elim Pr c. Spe Symbol Vcc VI V0 I0 Pd Topr Tstg ry MITSUBISHI LSIs Rev. 1.0 Oct./4/95 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM MH1M144CXTJ-6 Ratings -1 ~ 7 -1 ~ 7 -1 ~ 7 50 21.6 0 ~ 70 -40 ~ 100 Unit V V V mA W C C ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Ta=25C With respect to Vss Conditions RECOMMENDED OPERATING CONDITIONS Symbol Vcc Vss VIH VIH VIL VIL Supply voltage Supply voltage High-level input voltage, I/O pins High-level input voltage, non I/O pins Low-level input voltage, I/O pins Low-level input voltage, non I/O pins Parameter (Ta=0 ~ 70C, unless otherwise noted) (Note 1) Limits Unit V V V V V V Min 4.75 0 2.4 2.0 -1.0 -0.5 Nom 5 0 Max 5.25 0 5.5 5.5 0.8 0.8 Note 1 : All voltage values are with respect to Vss ELECTRICAL CHARACTERISTICS Symbol VOH VOL IOZ Parameter High-level output voltage Low-level output voltage Off-state output current (Ta=0 ~ 70C , Vcc=5.0V 5%, Vss=0V, unless otherwise noted) (Note 2) Test conditions IOH=-5.0mA IOL=4.2mA Q floating 0V VOUT 5.5V 0V VIN 6.5V, Other inputs pins=0V 13%Fase Page mode and 87% CBR Refresh mode Limits Min 2.4 0 -10 -10 Typ Max Vcc 0.4 10 10 3.3 Unit V V A A A Input current II Icc(note 3) Operating Current Average Note 2: Current flowing into an IC is positive, out is negative. 3: tRC = tRC(min.) Icc is depend on cycle rate. CAPACITANCE Symbol CI1 CI2 CI3 (Ta=0 ~ 70 C, Vcc=5.0V 5%, Vss=0V, unless otherwise noted) Limits Min Typ Max 17 15 17 Unit pF pF pF Parameter Input capacitance, address inputs Input capacitance, clocks inputs Input/Output capacitance VI=Vss Test conditions f=1MHZ Vi=25mVrms MITSUBISHI ELECTRIC ( 5 /14 ) ina elim Pr c. Spe Symbol tRC tPC tRAC tCAC tAA tCPA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tCAL tRCS tRCH tRRH tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tREF tCSR tCHR tRPC tCPN tWRP tWRH tRHP ry MITSUBISHI LSIs Rev. 1.0 Oct./4/95 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM (Ta=0 ~70 C, Vcc=5.0V 5%, Vss=0V, unless otherwise noted , see notes 4,5,6) Parameter Min 110 40 65 20 35 40 5 1 3 40 60 18 60 20 20 15 10 10 0 10 0 15 50 30 30 0 0 10 0 15 45 15 15 15 0 20 45 16.4 10 20 10 10 10 10 35 10K 43 30 10K 20 12 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns 15 13 13 12 12 14 8 9 11 10 4 7 7 7 Notes MH1M144CXTJ-6 AC CHARACTERISTICS Random Read or Write Cycle Time Fast Page Mode Cycle Time Access time from /RAS Access time from /CAS Access Time from Column Address Access time from /CAS precharge CAS to Output in Low Z Output Buffer Turn-Off Delay time Transition Time(Rise And Fall) /RAS Precharge Time /RAS Pulse Width /RAS Hold Time /CAS Hold Time /CAS Pulse Width /RAS to /CAS Delay Time /RAS to Column Address Delay Time /CAS to /RAS Precharge Time /CAS Precharge Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time Column Address Hold Time Ref to /RAS Column Address Lead Time Ref to /RAS Column Address Lead Time Ref to /CAS Read Command Setup Time Read Command Hold Time Ref to /CAS Read Command Hold Time Ref to /RAS Write Command Setup Time Write Command Hold Time Write Command Hold Time Ref to /RAS Write Commnad Pulse Width Write Command to /RAS Lead Time Write Command to /CAS Lead Time Data Setup Time Data Hold Time Data Hold Time Ref to /RAS Refresh Period /CAS Setup Time(CBR) /CAS Hold Time(CBR) /RAS to /CAS Precharge Time /CAS Precharge Time(Non Page Mode) /WE Setup(CBR Refresh) /WE Hold(CBR Refresh) Write to RAS Hold Time Note 4: VIH Min and VIL Max are reference levels for measuring timing of inputs signals.Also,transition times are measured between VIH and VIL 5: An initial pause of 500us is required after power-up followed by 8 CBR cycles before proper device operation is achived. 6: AC measurements assume tT = 5ns. 7: Load = 2TTL loads and 100pF. 8: Operation within the tRCD Max limit insures that tRAC Max can be met.tRCD Max is specified as a reference point only.If tRCD is greater than the specified tRCD Max limit,then access time is controlled by tCAC. 9: Operation within the tRAD Max limit insures that tRAC Max can be met.tRAD Max is specified as a reference point only.If tRAD is greater than the specified tRAD Max limit,then access time is controlled by tAA. 10: tOFF Max defines the time at which the output achieves the open circuit conditon and is not referenced to VOH or VOL. 11: The tCRP requirement should be applicable for /RAS-/CAS cycles preceeded by any cycle. 12: Either tRRH or tRCH must be satisfied for a read cycle. 13: These parameters are referenced to the falling edge of /CAS for early write cycles. MITSUBISHI ELECTRIC ( 6 /14 ) ina elim Pr c. Spe ry MITSUBISHI LSIs Rev. 1.0 Oct./4/95 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM MH1M144CXTJ-6 Note 14 : If tWCS tWCS Min,the cycle is an early write cycle and dataout pin will remain open circuit(high impedance). 15 : 1024 refresh cycle for 16M. MITSUBISHI ELECTRIC ( 7 /14 ) ina elim Pr c. Spe ry MITSUBISHI LSIs Rev. 1.0 Oct./4/95 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM (Note 16) MH1M144CXTJ-6 Timing Diagrams Read Cycle tRC tRAS VIH VIL tCSH tCRP VIH VIL tASR VIH A0~A9 VIL tRAD tRAH tASC tCAH tRAL tCPN ROW ADDRESS tRP RAS tRCD tRSH tCAS tRPC tCRP CAS tASR ROW ADDRESS COLUMN ADDRESS tRRH tRCS W VIH VIL tRCH tCAC tAA tCLZ VOH tOFF DQ Hi-Z VOL tRAC DATA VALID Hi-Z Note 16 Indicates the don't care input. VIH(min)VINVIH(max) or VIL(min)VINVIL(max) Indicates the invalid output. MITSUBISHI ELECTRIC ( 8 /14 ) ina elim Pr c. Spe ry MITSUBISHI LSIs Rev. 1.0 Oct./4/95 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM MH1M144CXTJ-6 Write Cycle (Early write) tWC tRAS VIH VIL tCSH tCRP VIH VIL tASR VIH A0~A9 VIL tASR tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRP RAS tRCD tRSH tCAS tRPC tCRP CAS ROW ADDRESS tWCS W VIH VIL tDS VIH VIL tWCH tDH DQ DATA VALID MITSUBISHI ELECTRIC ( 9 /14 ) ina elim Pr c. Spe ry MITSUBISHI LSIs Rev. 1.0 Oct./4/95 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM MH1M144CXTJ-6 RAS-only Refresh Cycle tRC tRAS RAS VIH VIL tRPC tCRP VIH CAS VIL tASR tRAH tASR tCRP tRP VIH A0~A9 VIL ROW ADDRESS ROW ADDRESS W VIH VIL DQ VOH VOL Hi-Z MITSUBISHI ELECTRIC (10 /14 ) ina elim Pr c. Spe ry MITSUBISHI LSIs Rev. 1.0 Oct./4/95 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM MH1M144CXTJ-6 CAS before RAS Refresh Cycle tRC tRP RAS VIH VIL tRAS tRAS tRC tRP tRPC VIH CAS VIL tCSR tCHR tRPC tCSR tCHR tRPC tCRP tCPN tASR VIH A0~A9 VIL tRCH VIH W VIL ROW ADDRESS COLUMN ADDRESS tOFF VOH DQ Hi-Z VOL MITSUBISHI ELECTRIC (11 /14 ) ina elim Pr c. Spe ry MITSUBISHI LSIs Rev. 1.0 Oct./4/95 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM MH1M144CXTJ-6 Hidden Refresh Cycle (Read) (Note 17) tRC tRAS RAS VIH VIL tCRP VIH VIL tRAD tASR VIH A0~A9 VIL tRAH ROW ADDRESS tRC tRP tRAS tRP tRCD tRSH tCHR CAS tASC tCAH COLUMN ADDRESS tASR ROW ADDRESS tRCS tRAL VIH VIL tCAC tAA tCLZ tRRH W tOFF DQ VOH Hi-Z VOL tRAC DATA VALID Hi-Z Note 17: Early write is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above. MITSUBISHI ELECTRIC (12 /14 ) ina elim Pr c. Spe ry MITSUBISHI LSIs Rev. 1.0 Oct./4/95 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM MH1M144CXTJ-6 Fast Page Mode Read Cycle tRAS VIH VIL tCSH tCRP VIH VIL tASR VIH VIL tRAD tRAH tCPRH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tCP tPC tCAS tCP tRSH tCAS tRP RAS CAS tASR ROW ADDRESS A0~A9 ROW ADDRESS COLUMN-1 COLUMN-2 COLUMN-3 tRAL tRCS VIH VIL tCAC tAA tCAC tAA tCAC tAA tRCH tRCS tRCH tRCS tRRH tRCH W tCLZ tOFF DATA VALID-1 tCLZ tOFF DATA VALID-2 tCLZ tOFF DATA VALID-3 DQ VOH VOL Hi-Z tRAC tCPA tCPA MITSUBISHI ELECTRIC (13 /14 ) ina elim Pr c. Spe ry MITSUBISHI LSIs Rev. 1.0 Oct./4/95 FAST PAGE MODE 150994944-BIT (1048576-WORD BY 144-BIT)DYNAMIC RAM MH1M144CXTJ-6 Fast Page Mode Write Cycle (Early Write) tRAS VIH VIL tCSH tCRP VIH CAS VIL tASR tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tCP tPC tCAS tCP tRSH tCAS tRP RAS tASR ROW ADDRESS VIH A0~A9 VIL ROW ADDRESS COLUMN-1 COLUMN-2 COLUMN-3 tWCS W VIH VIL tDS VIH VIL tWCH tWCS tWCH tWCS tWCH tDH DATA VALID-1 tDS tDH tDS tDH DATA VALID-3 DQ DATA VALID-2 MITSUBISHI ELECTRIC (14 /14 ) |
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