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INTEGRATED CIRCUITS
DATA SHEET
SAA4974H Besic without ADC
Product specification File under Integrated Circuits, IC02 1998 Apr 21
Philips Semiconductors
Product specification
Besic without ADC
CONTENTS 1 2 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description FUNCTIONAL DESCRIPTION Digital processing at 2fH level 4 : 1 : 1 to 4 : 2 : 2 up-conversion DCTI Y-peaking Y-delay Sidepanels and blanking Digital-to-analog conversion Microprocessor I2C-bus SNERT-bus I/O-ports Watchdog timer 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.5 7.6 7.7 7.8 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 16
SAA4974H
Memory controller WE RSTW RE IE2 HDFL VDFL BLND Clock and sync interfacing 4 : 1 : 1 digital input interfacing Test mode operation I2C-bus control registers LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS APPLICATION PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1998 Apr 21
2
Philips Semiconductors
Product specification
Besic without ADC
1 FEATURES
SAA4974H
* Field rate up-conversion (50 to 100 Hz or 60 to 120 Hz) * 4 : 1 : 1 digital input * Digital Colour Transient Improvement (DCTI) * Digital luminance peaking * Triple 10-bit Digital-to-Analog Converter (DAC) * Memory controller * Embedded microprocessor * 16 kbyte ROM * 256 byte RAM * I2C-bus interface * Synchronous No parity Eight bit Reception and Transmission (SNERT) interface. 2 GENERAL DESCRIPTION The SAA4974H is a video processing IC providing a digital YUV 4 : 1 : 1 input interface, analog YUV output, video enhancing features, memory controlling and an embedded 80C51 microprocessor core. It is applicable especially for field rate up-conversion (50 to 100 Hz or 60 to 120 Hz) in cooperation with a 2.9 Mbit field memory. It is designed for applications together with: SAA7111A, VPC3200 (video decoder) SAA4955/56TJ, TMS4C2972/73 (serial field memories) SAA4990H (PROZONIC) SAA4991WP (MELZONIC). 3 QUICK REFERENCE DATA SYMBOL VDDA(1,2) VDDD(1,2,3) VDDIO(1,2,3) IDDA(1,2) IDDD(1,2,3) IDDIO(1,2,3) Ptot Tamb 4 PARAMETER analog supply voltage digital supply voltage I/O supply voltage analog supply current digital supply current I/O supply current total power dissipation operating ambient temperature MIN. 3.15 3.0 4.5 - - - - -20 TYP. 3.3 3.3 5.0 25 50 10 - - MAX. 3.45 3.6 5.5 40 70 20 0.5 +70 V V V mA mA mA W C UNIT
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm VERSION SOT318-2
SAA4974H
QFP80
1998 Apr 21
3
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ook, full pagewidth
1998 Apr 21
8 YI7 to YI0 51 to 58 VARIABLE Y-DELAY 4 UVI7 to UVI4 59 to 62 REFORMATTER UP-CONVERSION 4:1:1 TO 4:2:2
5
Philips Semiconductors
Besic without ADC
BLOCK DIAGRAM
Y-PEAKING BLANKING DCTI UP-CONVERSION 4:2:2 TO 4:4:4 SIDEPANELS OVERLAY TRIPLE 10-BIT DAC
79
YOUT
76
UOUT
74
VOUT
SAA4974H
ROM TMS TRST ANATEST 30 15 49 TEST CONTROL BLOCK CONTROL INTERFACE MEMORY CONTROL (ACQUISITION) 47 33 22 20 32 24 70 CONTROL INTERFACE MEMORY CONTROL (DISPLAY) 63 64 66 71 72 68 9 RAM
4
MICROPROCESSOR I/O PORT SNERTBUS 13 10 I2CBUS 1 2
3 to 7 12 5
SWC LLA
HA VA
WE RSTW
LLD RE
IE2
HDFL BLND
HRD RST
VDFL
P1.5 to P1.1
SNCL SNDA
SDA SCL
MGM687
SNRST
Product specification
SAA4974H
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Besic without ADC
6 6.1 PINNING INFORMATION Pinning
SAA4974H
67 VDDIO3
76 UOUT
74 VOUT
79 YOUT
SDA SCL P1.5
66 BLND
72 VDFL
71 HDFL
handbook, full pagewidth
65 VSSIO3 64 IE2 63 RE 62 UVI4 61 UVI5 60 UVI6 59 UVI7 58 YI0 57 YI1 56 YI2 55 YI3 54 YI4 53 YI5 52 YI6 51 YI7 50 VSSD3 49 TRST 48 VSSIO2 47 SWC 46 VDDIO2 45 n.c. 44 n.c. 43 n.c. 42 n.c. 41 n.c. n.c. 40
69 VDDD3 n.c. 36
75 VDDA1
80 VDDA2
77 VSSA2
73 VSSA1
78 VSSA3
1 2 3
P1.4 4 P1.3 P1.2 P1.1 VDDD1 RST 5 6 7 8 9
SNRST 10 VDDD2 11 SNDA 12
SAA4974H
SNCL 13 VSSD1 14 TMS 15 VSSIO1 16 n.c. 17 VDDIO1 18 n.c. 19 VA 20 VSSD2 21 HA 22 n.c. 23 RSTW 24 ANATEST 30 WE 32 n.c. 25 n.c. 26 n.c. 27 n.c. 28 n.c. 29 n.c. 31 LLA 33 n.c. 34 n.c. 35 n.c. 37 n.c. 38 n.c. 39
68 HRD
70 LLD
MGM688
Fig.2 Pin configuration.
1998 Apr 21
5
Philips Semiconductors
Product specification
Besic without ADC
6.2 Pin description SOT318-2 package PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 I2C-bus I2C-bus serial data (P 1.7) serial clock (P 1.6) DESCRIPTION
SAA4974H
Table 1
SYMBOL SDA SCL P1.5 P1.4 P1.3 P1.2 P1.1 VDDD1 RST SNRST VDDD2 SNDA SNCL VSSD1 TMS VSSIO1 n.c. VDDIO1 n.c. VA VSSD2 HA n.c. RSTW n.c. n.c. n.c. n.c. n.c. ANATEST n.c. WE LLA n.c. n.c. n.c. n.c. n.c.
Port 1 data input/output signal 5 Port 1 data input/output signal 4 Port 1 data input/output signal 3 Port 1 data input/output signal 2 Port 1 data input/output signal 1 digital supply voltage 1 (3.3 V) microprocessor reset input SNERT restart (port 1.0) digital supply voltage 2 (3.3 V) SNERT data SNERT clock digital ground 1 test mode select I/O ground 1 not connected I/O supply voltage 1 (5 V) not connected vertical synchronization input, acquisition part digital ground 2 digital horizontal reference input not connected reset write signal output, memory 1 not connected not connected not connected not connected not connected analog test input not connected write enable signal output, memory 1 acquisition clock input not connected not connected not connected not connected not connected
1998 Apr 21
6
Philips Semiconductors
Product specification
Besic without ADC
SAA4974H
SYMBOL n.c. n.c. n.c. n.c. n.c. n.c. n.c. VDDIO2 SWC VSSIO2 TRST VSSD3 YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 UVI7 UVI6 UVI5 UVI4 RE IE2 VSSIO3 BLND VDDIO3 HRD VDDD3 LLD HDFL VDFL VSSA1 VOUT VDDA1 UOUT VSSA2
PIN 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 not connected not connected not connected not connected not connected not connected not connected I/O supply voltage 2 (5 V) serial write clock output I/O ground 2 test reset, LOW active digital ground 3 Y digital input bit 7 (MSB) Y digital input bit 6 Y digital input bit 5 Y digital input bit 4 Y digital input bit 3 Y digital input bit 2 Y digital input bit 1 Y digital input bit 0 U digital input bit 1 U digital input bit 0 V digital input bit 1 V digital input bit 0
DESCRIPTION
read enable signal output, memory 1 input enable signal output, memory 2 I/O ground 3 horizontal blanking signal output, display part I/O supply voltage 3 (5 V) horizontal reference signal output, deflection part digital supply voltage 3 (3.3 V) display clock input horizontal synchronization signal output, deflection part vertical synchronization signal output, deflection part analog ground 1 V analog output analog supply voltage 1 (3.3 V) U analog output analog ground 2
1998 Apr 21
7
Philips Semiconductors
Product specification
Besic without ADC
SAA4974H
SYMBOL VSSA3 YOUT VDDA2 7 7.1 7.1.1
PIN 78 79 80 analog ground 3 Y analog output analog supply voltage 2 (3.3 V)
DESCRIPTION
FUNCTIONAL DESCRIPTION Digital processing at 2fH level 4 : 1 : 1 TO 4 : 2 : 2 UP-CONVERSION
An up-converter to 4 : 2 : 2 is applied with a linear interpolation filter for creation of the extra samples. These are combined with the original samples from the 4 : 1 : 1 stream. 7.1.2 DCTI
Via I2C-bus it is possible to control: gain width (see Fig.4), threshold (i.e. immunity against noise), selection of simple or improved first differentiating filter (see Fig.3), limit for pixel shift range (see Fig.5), common or separate processing of U and V signals, hill protection mode (i.e. no discolourations in narrow colour gaps), low-pass filtering for U and V signals (see Fig.6) and a so called super hill mode, which avoids discolourations in transients within a colour component.
The Digital Colour Transient Improvement (DCTI) is intended for U and V signals originating from a 4 : 1 : 1 source. Horizontal transients are detected and enhanced without overshoots by differentiating, make absolute and again differentiating the U and V signals separately. This results in a 4 : 4 : 4 U and V bandwidth. To prevent third harmonic distortion, typical for this processing, a so called over the hill protection prevents peak signals to become distorted.
1998 Apr 21
8
Philips Semiconductors
Product specification
Besic without ADC
SAA4974H
MGM689
handbook, halfpage
1
signal amplitude 0.8
(1)
(2)
0.6
0.4
0.2
0 0 (1) dcti_ddx_sel = 1. (2) dcti_ddx_sel = 0. 0.05 0.1 0.15 0.2 f/fs 0.25
Fig.3 DCTI first differentiating filter; transfer function with variation of control signal dcti_ddx_sel.
handbook, full pagewidth
MGM690
500 digital signal 400 amplitude 300
(4) (3) (1) (2)
200 100 0
(5)
samples -100 -200 -300 -400 (1) (2) (3) (4) (5) Input signal. Gain = 1. Gain = 3. Gain = 5. Gain = 7. -500
Fig.4 DCTI with variation of gain setting (limit = 1).
1998 Apr 21
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Philips Semiconductors
Product specification
Besic without ADC
SAA4974H
handbook, full pagewidth
500 digital signal 400 amplitude 300 200 100 0
(4) (3) (2) (1)
MGM691
samples -100 -200 -300 -400 (1) (2) (3) (4) Input signal. Limit = 1. Limit = 2. Limit = 3. -500
Fig.5 DCTI with variation of limit setting (gain = 7).
handbook, halfpage
1.2
MGM692
signal amplitude
0.8
0.4
0 0 0.1 0.2 0.3 0.4 f/fs 0.5
Fig.6 DCTI post-filter transfer function.
1998 Apr 21
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Philips Semiconductors
Product specification
Besic without ADC
7.1.3 Y-PEAKING
SAA4974H
The band-passed and high-passed signals are weighted with factors 0, 18, 14 and 12. The impulse response becomes [-, -, 1 + 2 + 2, -, -], where is the band-pass weighting factor and the high-pass weighting factor. Coring is added to obtain no gain for low amplitudes in the (high-pass + band-pass) signal, which is then considered to be noise. Coring levels can be programmed as 0 (off), +1/-2, +3/-4 and +7/-8 LSB at 8-bit word.
A linear peaking is applied, which amplifies the luminance signal in the middle and the upper ranges of the bandwidth. The filtering is an addition of: * The original signal * The original signal band-passed with centre frequency = 14fs * The original signal high-passed with maximum gain at frequency = 12fs.
handbook, halfpage
12
MGE097
handbook, halfpage
12
MGE098
(1) 10 IH_PeakingI (dB) 8 (1) 10 IH_PeakingI (dB) 8 (2) (3) (2) 6 (3) 4 (4) 4 6 (4)
2
2
0 0 (1) = 12. (2) = 14. (3) = 18. (4) = 0. 1/4fs 1/2fs
0 0 (1) = 12. (2) = 14. (3) = 18. (4) = 0. 1/4fs 1/2fs
Fig.7
Peaking transfer function with variation of ( = 18).
Fig.8
Peaking transfer function with variation of ( = 14).
1998 Apr 21
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Philips Semiconductors
Product specification
Besic without ADC
SAA4974H
handbook, halfpage
16
MGE099
handbook, halfpage
12
MGE100
14 IH_PeakingI (dB) 12 10
10 (1) IH_PeakingI (dB) 8
(1)
(2) 8 6 4 2 2 0 0 (1) = 12. (2) = 14. (3) = 18. (4) = 0. 1/4fs 1/2fs 0 0 1/4fs 1/2fs (3) (4) 6 (2) 4 (3)
(1) = 12. (2) = 14. (3) = 18.
Fig.9
Peaking transfer function with variation of ( = 12).
Fig.10 Peaking transfer function with variation of ( = 0).
7.1.4
Y-DELAY
The Y samples can be shifted onto 8 positions with reference to the UV samples. This shift is meant to account for a possible difference in delay previous to the SAA4974H. The zero delay setting is suitable for the nominal case of aligned input data according to the interface format standard. The other settings provide one to seven samples less delay in Y. 7.1.5 SIDEPANELS AND BLANKING
signal VBDA are programmable with reference to the rising edge of the VA signal. The range of the Y output signal can be selected between 9 and 10 bits. In case of 9 bits for the nominal signal there is room left for under and overshoot (adding up to a total of 10 bits). In case of selecting all 10 bits of the luminance Digital-to-Analog Converter (DAC) for the nominal signal any under or overshoot will be clipped. In case of selecting 9 bits of the luminance DAC for the nominal signal under or overshoots are limited within a programmable range (see Fig.12). 7.2 Digital-to-analog conversion
Sidepanels are generated by switching Y and the 4 MSB of U and V to certain programmable values. The start and stop values for the sidepanels with reference to the rising edge of the HRD signal are programmable in a resolution of 4 LLD clock cycles. In addition a fine shift of 0 to 3 LLD clock cycles of both values can be achieved. Blanking is done by switching Y to value 64 at 10-bit word and UV to value 0 (in twos complement). Blanking is controlled by a composite signal HVBDA, existing of a horizontal part HBDA and a vertical part VBDA. Set and reset value of the horizontal control signal HBDA are programmable with reference to the rising edge of the HRD signal, set and reset value of the vertical control
Three identical 10-bit DACs are used to map the 4 : 4 : 4 data to analog levels. 7.3 Microprocessor
The SAA4974H contains an embedded 80C51 microprocessor core including 256 byte RAM and 16 kbyte ROM. The microprocessor runs on a 16 MHz clock, generated by dividing the 32 MHz display clock by a factor of 2. For controlling internal registers a host interface, consisting of a parallel address and data bus, is
1998 Apr 21
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Philips Semiconductors
Product specification
Besic without ADC
built in, that can be addressed as internal AUXRAM via MOVX type of instruction. 7.3.1 I2C-BUS 7.3.4 WATCHDOG TIMER
SAA4974H
The I2C-bus interface in the SAA4974H is used in a slave receive and transmit mode for communication with in general a central system microprocessor. The standardized bus frequencies of both 100 kHz and 400 kHz can be dealt with. The I2C-bus slave address of the SAA4974H is 0 1 1 0 1 0 0 R/W. For a detailed description of the transmission protocol refer to brochure "I2C-bus and how to use it" (order number 9398 393 40011) and to Application Note "I2C-bus register specification of the SAA4974H" (AN97042). 7.3.2 SNERT-BUS
The microprocessor contains an internal Watchdog timer, which can be activated by setting the corresponding special function register PCON.4. Only a synchronous reset will clear this bit. To prevent a system reset the watchdog timer must be reloaded in time. The Watchdog timer is incremented every 0.75 ms. The time interval between the timer's reloading and the occurrence of a reset depends on the reloaded 8-bit value. 7.4 Memory controller
A SNERT interface is built in, which operates in a master receive and transmit mode for communication with peripheral circuits as SAA4990H or SAA4991WP. The SNERT interface replaces the standard UART interface. In contrary to the 8051 UART interface there are additional special function registers and there is no byte separation time between address and data. The SNERT interface transforms the parallel data from the microprocessor into 1 Mbaud SNERT data. The SNERT-bus consists of three signals: SNCL used as serial clock signal, generated by the SNERT interface; SNDA used as bidirectional data line, and SNRST used as reset signal, generated by the microprocessor to indicate the start of a transmission. The read or write operation must be set by the microprocessor. In case of writing to the bus, 2 bytes are loaded by the microprocessor: one for the address, the other for the data. In case of reading from the bus, one byte is loaded by the microprocessor for the address, the received byte is the data from the addressed SNERT location. 7.3.3 I/O-PORTS
The memory controller provides all necessary acquisition clock related write signals (WE and RSTW) and display clock related read signals (RE and IE2) to control one or two-field memory concepts. Furthermore the drive signals (HDFL and VDFL) for the horizontal and vertical deflection power stages are generated. Also a horizontal blanking pulse BLND is generated which can be used for peripheral circuits as SAA4990H. The memory controller is connected to the microprocessor via the host interface. Start and stop values for all pulses, referring to the corresponding horizontal or vertical reference signal, are programmable under control of the internal software. To allow an user access to these control signals via I2C-bus a range of subaddresses is reserved; for a detailed description of this user interface refer to Application Note "I2C-bus register specification of the SAA4974H" (AN97042). 7.4.1 WE
The write enable signal for field memory 1 is a composite signal consisting of a horizontal and a vertical part. The horizontal position with reference to the rising edge of the HA signal and the vertical position with reference to the rising edge of the VA signal are programmable. 7.4.2 RSTW
Reset write signal for field memory 1; this signal is derived from the positive edge of the VA input signal and has a pulse width of 64 s. 7.4.3 RE
A parallel 8-bit I/O-port (P1) is available, where P1.0 is used as SNERT reset signal (SNRST), P1.1 to P1.5 can be used for application specific control signals, and P1.6 and P1.7 are used as I2C-bus signals (SCL and SDA).
The read enable signal for field memory 1 is a composite signal consisting of a horizontal and a vertical part. The horizontal position with reference to the rising edge of the HA signal and the vertical position with reference to the rising edge of the VA signal are programmable.
1998 Apr 21
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Product specification
Besic without ADC
7.4.4 IE2 7.6
SAA4974H
4 : 1 : 1 digital input interfacing
Input enable signal for field memory 2, can be directly set or reset by the microprocessor. 7.4.5 HDFL
Digital input bus format 4 : 1 : 1 FORMAT INPUT PIN Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U01 U00 V01 V00 YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 UVI7 UVI6 UVI5 UVI4
Horizontal deflection signal for driving an deflection circuit; this signal has a cycle time of 32 s and a pulse width of 76 LLD clock cycles. 7.4.6 VDFL
Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 V07 V06
Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04
Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U03 U02 V03 V02
Vertical deflection signal for driving a deflection circuit; this signal has a cycle time of 10 ms; start and stop value with reference to the rising edge of the VA signal is programmable in steps of 16 s. 7.4.7 BLND
Horizontal blanking signal for peripheral circuits e.g. SAA4990H, start and stop values with reference to the rising edge of HRD are programmable. 7.5 Clock and sync interfacing
The line locked acquisition clock LLA and the line locked display clock LLD must be provided by the application. Also an acquisition clock synchronous line frequent signal must be provided by the application at pin HA. A vertical 50 or 60 Hz synchronization signal has to be applied on pin VA. Typically the circuit operates as a two clock system, i.e. LLA has to be supplied with a 16 MHz clock and LLD with a 32 MHz clock. The circuit can also operate as a one clock system, i.e. a 32 MHz line locked display clock has to be provided to both pins LLA and LLD. In this case the internal horizontal pixel counter is reset by the rising edge of the HA input, and the corresponding control signal en_hdsp_rst has to be set via the I2C-bus. A display clock synchronous line frequent signal is put out at pin HRD providing a duty factor of 50%. The rising edge of HRD is also the reference for display related control signals as BLND, RE, HDAV and HBDA. The acquisition clock is buffered internally and put out as serial write clock (SWC) for supplying the field memory.
The start position, when the first phase of the 4 : 1 : 1 YUV dataword is expected on the input bus, can be defined by the internal control signal HDAV. The luminance input signal is expected in 8-bit straight binary format, whereas U and V input signals are expected in twos complement format. U and V input signals are inverted if the corresponding control bit uv_inv is set via the I2C-bus. 7.7 Test mode operation
The SAA4974H provides a test mode function which should be avoided to be entered by the customer. If the TRST input is driven to HIGH, different test modes can be selected by applying HIGH to the TMS input for a defined number of LLD clock cycles. Also the ANATEST input is only active during test mode operation. To exit the test mode TMS and TRST must be driven LOW.
1998 Apr 21
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Philips Semiconductors
Product specification
Besic without ADC
7.8 I2C-bus control registers BIT NAME DESCRIPTION
SAA4974H
ADDRESS
Subaddress 00H to 35H: reserved; note 1 Subaddress 36H and 37H (DCTI) 36H 0 to 2 3 to 6 7 37H 2 3 4 5 dcti_gain dcti_threshold dcti_ddx_sel dcti_separate dcti_protection dcti_filteron dcti_superhill DCTI gain: 0, 1, 2, 3, 4, 5, 6 and 7 DCTI threshold: 0 and 1 to 15 DCTI selection of first differentiating filter; see Fig.3 DCTI limit for pixel shift range: 0, 1, 2 and 3 DCTI separate processing of U and V signals; 0 = off and 1 = on DCTI over the hill protection; 0 = off and 1 = on DCTI post-filter; 0 = off and 1 = on DCTI super hill mode; 0 = off and 1 = on reserved
0 and 1 dcti_limit
6 and 7 -
Subaddress 3AH and 3BH (sidepanels overlay) 3AH 3BH 0 to 3 4 to 7 0 to 7 overlay_u overlay_v overlay_y sidepanels overlay U (4 MSB) sidepanels overlay V (4 MSB) sidepanels overlay Y (8 MSB) peaking settings : 0, 18, 14 and 12 peaking settings : 0, 18, 14 and 12 peaking limiter settings in display mode = 0: (256/767, 171/852, 86/937 and 0/1023) peaking coring settings: 0, +1/-2, +3/-4 and +7/-8 LSB at 8-bit word
Subaddress 3CH (peaking) 3CH 0 and 1 peak_ 2 and 3 peak_ 4 and 5 peak_limit 6 and 7 peak_coring
Subaddress 3DH to 3FH (sidepanel position) 3DH 3EH 3FH 0 to 7 0 to 7 sidepanel_start sidepanel start position (8 MSB) with reference to the rising edge of HRD signal sidepanel_stop sidepanel stop position (8 MSB) with reference to the rising edge of HRD signal fine delay of sidepanel signal in LLD clock cycles: (0, 1, 2 and 3) display mode (display mode = 0: 9-bit for the nominal output signal, black level 288 and white level 767; display mode = 1: 10-bit for the nominal output signal, black level 64 and white level 1023) inverts UV input signals: 0 = no inversion, 1 = inversion variable Y-delay in LLD clock cycles: -7, -6, -5, -4, -3, -2, -1 and 0 enable hdsp reset: 0 = disable and 1 = enable display_mode
0 and 1 sidepanel_fdel 2
3 4 to 6 7 Note
uv_inv ydelay_out en_hdsp_rst
1. Detailed information about the software dependent I2C-bus registers can be found in Application Note "I2C-bus register specification of the SAA4974H" (AN97042).
1998 Apr 21
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Philips Semiconductors
Product specification
Besic without ADC
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDA(1,2) VDDD(1,2,3) Vi Tstg Tamb 9 analog supply voltage digital supply voltage input voltage for all I/O pins storage temperature operating ambient temperature PARAMETER MIN. -0.5 -0.5 -0.5 -0.5 -20 -20
SAA4974H
MAX. +3.45 +3.6 +5.5 +5.5 +150 +70 V V V V C C
UNIT
VDDIO(1,2,3) digital I/O supply voltage
THERMAL CHARACTERISTICS SYMBOL PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 53 UNIT K/W
Rth(j-a)
1998 Apr 21
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Philips Semiconductors
Product specification
Besic without ADC
10 CHARACTERISTICS VDDD = 3.0 to 3.6 V; VDDA = 3.15 to 3.45 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL Supply VDDA(1,2) VDDD(1,2,3) VDDIO(1,2,3) IDDA(1,2) IDDD(1,2,3) IDDIO(1,2,3) Dissipation Ptot total power dissipation - - analog supply voltage digital supply voltage I/O supply voltage analog supply current digital supply current I/O supply current 3.15 3.0 4.5 - - - 3.3 3.3 5.0 25 50 10 PARAMETER CONDITIONS MIN. TYP.
SAA4974H
MAX.
UNIT
3.45 3.6 5.5 40 70 20
V V V mA mA mA
0.5
W
Luminance output signal (display_mode = 0: Y black level digital 288, white level digital 767; display_mode = 1: Y black level digital 64, white level digital 1023); see Fig.12 Vo(p-p) Ro RL CL SVR ct S/N Y output level (peak-to-peak value) output resistance resistive load capacitive load supply voltage rejection crosstalk attenuation between outputs signal-to-noise ratio note 1 0 to 10 MHz nominal amplitude; 0 to 10 MHz ZL = 2 k 1.28 - 1 - 34 40 46 1.34 50 2 - - - - 1.40 100 - 25 - - - V k pF dB dB dB
Colour difference output signals (U and V digital range 0 to 1023) Vo(p-p) U output level (peak-to-peak value) V output level (peak-to-peak value) Gm(U-V) Ro RL CL SVR ct S/N gain matching U to V output resistance resistive load capacitive load supply voltage rejection crosstalk attenuation between outputs signal-to-noise ratio note 1 0 to 10 MHz nominal amplitude; 0 to 10 MHz ZL = 2 k ZL = 2 k 1.28 1.28 - - 1 - 34 40 46 1.34 1.34 1 50 2 - - - - 1.40 1.40 3 100 - 25 - - - V V % k pF dB dB dB
Output transfer function (sample rate 32 MHz/10 bits) INL DNL integral non linearity differential non linearity -2 -1 - - +2 +1 LSB LSB
1998 Apr 21
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Philips Semiconductors
Product specification
Besic without ADC
SAA4974H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital output signals: WE and RSTW (CL = 15 pF); timing referred to SWC clock VOH VOL td(o) th(o) HIGH-level output voltage LOW-level output voltage output delay time output hold time IOH = -2.0 mA IOL = 1.6 mA see Fig.11 see Fig.11 IOH = -2.0 mA IOL = 1.6 mA see Fig.11 IOH = -2.0 mA IOL = 1.6 mA see Fig.11 see Fig.11 IOH = -2.0 mA IOL = 1.6 mA IOH = -0.06 mA IOL = 1.6 mA 2.4 - - 4 - - - - - - - - - - - - - - - - - - - - - - - - - - 0.4 20 - - 0.4 12 - 0.4 20 - - 0.4 - 0.45 5.5 0.8 V V ns ns
Digital output signal: SWC (CL = 15 pF); timing referred to LLA clock VOH VOL td(o) HIGH-level output voltage LOW-level output voltage output delay time 2.4 - 3 V V ns
Digital output signals: IE2, BLND, RE, HDFL and VDFL (CL = 15 pF); timing referred to LLD clock VOH VOL td(o) th(o) VOH VOL VOH VOL VIH VIL VIH VIL tsu(i) th(i) VIH VIL tsu(i) th(i) HIGH-level output voltage LOW-level output voltage output delay time output hold time 2.4 - - 4 V V ns ns
Digital output signal: HRD HIGH-level output voltage LOW-level output voltage 2.4 - V V
Digital input/output signals: P1.1 to P1.5 and SNRST HIGH-level output voltage LOW-level output voltage HIGH-level input voltage LOW-level input voltage 2.4 0 2.0 0 V V V V
Digital input signals: YI and UVI; timing referred to LLD clock HIGH-level input voltage LOW-level input voltage input set-up time input hold time see Fig.11 see Fig.11 2.0 - 4 3 5.5 0.8 - - V V ns ns
Digital input signal: HA; timing referred to LLA clock HIGH-level input voltage LOW-level input voltage input set-up time input hold time see Fig.11 see Fig.11 2.0 - 7 4 5.5 0.8 - - V V ns ns
1998 Apr 21
18
Philips Semiconductors
Product specification
Besic without ADC
SAA4974H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. - -
MAX.
UNIT
Digital input signals: TRST, TMS, RST and VA VIH VIL fLLA clk VIH VIL tr tf fLLD clk VIH VIL tr tf HIGH-level input voltage LOW-level input voltage 2.0 - 5.5 0.8 V V
Digital input clock signal: LLA sample clock frequency clock duty factor HIGH-level input voltage LOW-level input voltage clock rise time clock fall time see Fig.11 see Fig.11 14 40 2.4 - - - 16 50 - - - - 34 60 - 0.6 5 5 MHz % V V ns ns
Digital input clock signal: LLD sample clock frequency clock duty factor HIGH-level input voltage LOW-level input voltage clock rise time clock fall time see Fig.11 see Fig.11 30 40 2.4 - - - 32 50 - - - - 34 60 - 0.6 5 5 - 0.4 400 - - - - - - - - MHz % V V ns ns
I2C-bus signal: SDA and SCL; note 2 VIH VIL VOL fSCL tHD;STA tLOW tHIGH tSU;DAT tSU;DAT1 tSU;DAT2 tSU;STA tSU;STO HIGH-level input voltage LOW-level input voltage LOW-level output voltage SCL clock frequency hold time START condition SCL LOW time SCL HIGH time data set-up time data set-up time (before repeated START condition) data set-up time (before STOP condition) set-up time repeated START set-up time STOP condition 3 mA sink current 0.7VDDIO - - - - 0.6 1.3 0.6 100 0.6 0.6 0.6 0.6 - - - - - - - - - - - V V kHz s s s ns s s s s 0.3VDDIO V
1998 Apr 21
19
Philips Semiconductors
Product specification
Besic without ADC
SAA4974H
SYMBOL
PARAMETER
CONDITIONS IOH = -2.0 mA IOL = 1.6 mA
MIN.
TYP. - - - - - - 1 - -
MAX.
UNIT
SNERT-bus: SNDA and SNCL; note 3 VOH VOL VIH VIL tsu(i) th(i) tcycle th(o) Notes 1. Supply voltage ripple rejection, measured over a frequency range from 20 Hz to 50 kHz. This includes 12fV, fV, 2fV, fH and 2fH which are major load frequencies: SVR is relative variation of the full scale analog input for a supply variation of 0.25 V. 2. The AC characteristics are in accordance with the I2C-bus specification for fast mode (clock frequency maximum 400 kHz). Information about the I2C-bus can be found in brochure "I2C-bus and how to use it" (order number 9398 393 40011). 3. More information about the SNERT-bus protocol can be found in Application Note "The SNERT-bus specification" (AN95127). HIGH-level output voltage LOW-level output voltage HIGH-level input voltage LOW-level input voltage input set-up time input hold time SNCL cycle time output hold time 2.4 - 2.0 - 700 0 - 50 V V V V ns ns s ns 0.4 5.5 0.8 - - - -
handbook, full pagewidth
tr
tf 2.4 V
CLOCK
1.5 V 0.6 V th(i) tsu(i) 2.0 V
INPUT DATA 0.8 V td(o) th(o) 2.4 V OUTPUT DATA 0.4 V
MGM597
Fig.11 Timing diagram.
1998 Apr 21
20
Philips Semiconductors
Product specification
Besic without ADC
SAA4974H
handbook, full pagewidth
8-BIT INPUT
display_mode = 1
10-BIT OUTPUT
display_mode = 0 1023 937 852 767
white 255
1023
peak_limit = 0
peak_limit = 1
peak_limit = 2
1.34 V
288 256 171 black 16 0 64 0 86 0
MGM693
Fig.12 Luminance levels.
11 APPLICATION The SAA4974H supports two different up-converter concepts. The simple one is shown in Fig.13. In this application only one field memory SAA4955TJ is needed for a 100 Hz conversion based on a field repetition algorithm (AABB mode). The concept can be upgraded by a noise reduction based on a motion adaptive field recursive filter if the SAA4956TJ is used instead of the SAA4955TJ. The SAA4974H supports a dual-clock system. The acquisition clock is taken from the digital front-end. The display control is based on a clock generated by an external H-PLL. By this structure the stability of the display is enhanced compared to a one-clock system if an unstable source like a VCR is used as an input. For low-cost applications it is possible to run the IC as a one-clock system.
The second system supported by the SAA4974H is shown in Fig.14. This concept needs two field memories (SAA4955TJ) and the signal processing IC MELZONIC (SAA4991WP). The SAA4991WP allows a vector based motion estimation and compensation for a display of 100 Hz pictures in high-end TV sets which is free of motion artefacts. It additionally provides a variable vertical zoom function, noise and cross colour reduction. Furthermore a multi-PIP feature is supported making use of the field memories.
1998 Apr 21
21
peak_limit = 3
Philips Semiconductors
Product specification
Besic without ADC
SAA4974H
handbook, full pagewidth
+3.3 V
+5 V
8, 11, 69, 75, 80 LLA +3.3 V 19, 22 3 4 5 6 7 8 9 10 YIN7 to YIN0 11 12 13 14 UVIN7 to UVIN4 25 26 1, 2, 39, 40 20 22 HRD +5 V 20, 21, 23 15 16 17, 18 38 37 36 35 33
18, 46, 67 9
10 F
8.2 k
SWC RSTW WE
47 24 32 51 52 53 54 55 56 57 58 59 60 61 62
79 76 74
YOUT UOUT VOUT
1 2
SDA SCL
SAA4955TJ
(1) 34
SAA4974H
10, 12, 13 3 to 7 64, 66 n.c. n.c. n.c.
33 32 31 30 29 28 27 24 RE
71 72
HDFL VDFL
63
68
14 to 16, 21, 30, 48 to 50, 17, 19, 23, 25 to 29, 70 65, 73, 77, 78 31, 34 to 45 n.c.
VA HA
DISPLAY PLL
SRC
MGM694
(1) Alternatively SAA4956TJ.
Fig.13 Application diagram 1.
1998 Apr 21
22
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Apr 21 23
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 3 4 5 6 7 8 9 11 12 13 14 25 26 1, 2, 39, 40 VA HA
Philips Semiconductors
Besic without ADC
LLA handbook, full pagewidth +3.3 V 19, 22 3 4 5 6 7 8 9 +5 V 20, 21, 23 15 16 17, 18 38 37 36 35 41 40 38 37 36 35 34 33 32 31 30 29 RE1 28 +5 V 47 1, 4, 20, 42, 46, 65, 78 48 49 50 51 52 53 54 55 56 57 58 59 61 +3.3 V 19, 22 +5 V 20, 21, 23 15 16 17, 18 38 37 36 35 WE2 11 64 66 67 68 69 70 71 72 73 74 75 RE2 76 2, 3, 5, 6, 7, 22, 26, 27, 39, 77 47, 60, 63, 79 to 84 62 25 24 23 21 19 18 17 16 15 14 13 12 45 8 to 10 n.c. D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 HRD 20 22 68 RE 24 32 51 52 53 54 55 56 57 58 59 60 61 62 63 SWC RSTW WE 33
+3.3 V
+5 V
8, 11, 69, 75, 80
18, 46, 67 9
10 F
8.2 k
79 76 74
YOUT UOUT VOUT
YIN7 to YIN0
10 11 12 13
SAA4955TJ 34 FM1 33
32 31 30 29 28 27
1 2
SDA SCL
UVIN7 to UVIN4
14
SAA4974H
25 26
10 3 to 7 64, 66
n.c. n.c. n.c.
24 1, 2, 39, 40
44
SNDA SNCL
12 13 71 14 to 16, 21, 30, 48 to 50, 65, 73, 77, 78 72 17, 19, 23, 31, 25 to 29, 70 34 to 45 n.c. HDFL VDFL
SAA4991WP
43
SAA4955TJ 34 FM2 33 10
32 31 30 29 28 27 24
DISPLAY PLL
SRC
Product specification
SAA4974H
MGM695
Fig.14 Application diagram 2.
Philips Semiconductors
Product specification
Besic without ADC
12 PACKAGE OUTLINE QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SAA4974H
SOT318-2
c
y X
64 65
41 40 ZE
A
e E HE wM pin 1 index bp 25 1 wM D HD ZD B vM B 24 vMA Lp L detail X A A2 A1 (A 3)
80
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.2 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.45 0.30 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.8 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.0 0.6 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT318-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1998 Apr 21
24
Philips Semiconductors
Product specification
Besic without ADC
13 SOLDERING 13.1 Introduction
SAA4974H
If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 Repairing soldered joints
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). 13.2 Reflow soldering
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. 13.3 Wave soldering
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm.
1998 Apr 21
25
Philips Semiconductors
Product specification
Besic without ADC
14 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA4974H
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 15 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 16 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 Apr 21
26
Philips Semiconductors
Product specification
Besic without ADC
NOTES
SAA4974H
1998 Apr 21
27
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 Internet: http://www.semiconductors.philips.com
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA59
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/00/01/pp28
Date of release: 1998 Apr 21
Document order number:
9397 750 03018

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