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INTEGRATED CIRCUITS
PCK2509S 50-150 MHz 1:9 SDRAM clock driver
Product specification 1999 Oct 19
Philips Semiconductors
Philips Semiconductors
Product specification
50-150 MHz 1:9 SDRAM clock driver
PCK2509S
FEATURES
* Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM
applications
* Spread Spectrum clock compatible * Operating frequency 50 to 150 MHz * (tphase error - jitter) at 100 to133 MHz = 50 ps * Jitter (peak-peak) at 100 to 133 MHz = 80 ps * Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps * Pin-to-pin skew < 200 ps * Available in plastic 24-Pin TSSOP * Distributes one clock input to one bank of ten outputs * External Feedback (FBIN) terminal Is used to synchronize the
outputs to the clock input
adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the PCK2509S does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the PCK2509S requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The PCK2509S is characterized for operation from 0C to +70C.
PIN CONFIGURATION
AGND VCC 1Y0 1Y1 1Y2 GND 1 2 3 4 5 6 7 8 9 24 CLK 23 AVCC 22 VCC 21 2Y0 20 2Y1 19 GND 18 GND 17 2Y2 16 2Y3 15 VCC 14 2G 13 FBIN
* On-Chip series damping resistors * No external RC network required * Operates at 3.3 V * Inputs compatible with 2.5 V and 3.3 V ranges
DESCRIPTION
The PCK2509S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLLto precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The PCK2509S operates at 3.3 V VCC and is input compatible with both 2.5 V and 3.3 V input voltage ranges. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are
GND 1Y3 1Y4
VCC 10 1G 11 FBOUT 12
SW00389
ORDERING INFORMATION
PACKAGES 24-Pin Plastic TSSOP TEMPERATURE RANGE 0C to +70C ORDER CODE PCK2509S PW DRAWING NUMBER SOT355-1
1999 Oct 19
2
853-2180 22544
Philips Semiconductors
Product specification
50-150 MHz 1:9 SDRAM clock driver
PCK2509S
PIN DESCRIPTIONS
PIN NUMBER 1 2, 10, 15, 22 3, 4, 5, 8, 9 6, 7, 18, 19 11 SYMBOL AGND VCC 1Y (0-4) GND 1G TYPE GND PWR OUT GND IN Power supply Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0-4) is enabled via the1G input. These outputs can be disabled to a logic LOW state by de-asserting the 1G control input. Each output has an integrated 25 series-damping resistor. Ground Output bank enable. 1G is the output enable for outputs 1Y(0-4). When 1G is LOW, outputs 1Y(0-4) are disabled to a logic LOW state. When 1G is HIGH, all outputs 1Y(0-4) are enabled and switch at the same frequency as CLK. Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an integrated 25 series-damping resistor. Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. Output bank enable. 2G is the output enable for outputs 2Y(0-3). When 2G is LOW, outputs 2Y(0-3) are disabled to a logic LOW state. When 2G is HIGH, all outputs 2Y(0-3) are enabled and switch at the same frequency as CLK. Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0-3) is enabled via the 2G input. These outputs can be disabled to a logic LOW state by de-asserting the 2G control input. Each output has an integrated 25 series-damping resistor. Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. Clock input. CLK provides the clock signal to be distributed by the PCK2509S clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. NAME, FUNCTION, and DIRECTION Analog ground. AGND provides the ground reference for the analog circuitry.
12
FBOUT
OUT
13
FBIN
IN
14
2G
IN
16, 17, 20, 21
2Y (0-3)
OUT
23
AVCC
PWR
24
CLK
IN
FUNCTION TABLE
INPUTS 1G X L L H H 2G X L H L H CLK L H H H H 1Y (0-4) L L L H H OUTPUTS 2Y (0-3) L L H L H FBOUT L H H H H
1999 Oct 19
3
Philips Semiconductors
Product specification
50-150 MHz 1:9 SDRAM clock driver
PCK2509S
FUNCTIONAL BLOCK DIAGRAM
1G 11 3
1Y0
4
1Y1
5
1Y2
8 9
1Y3 1Y4
2G
14 21 2Y0
20 CLK FBIN 24 13 PLL 17
2Y1
2Y2
16 AVCC 23 12
2Y3
FBOUT
SW00388
168-pin SDR SDRAM DIMM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM
BACK SIDE
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
FRONT SIDE A[L]VC A[L]VC A[L]VC PCK2509S
The PLL clock distribution device and A[L]VC registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation
SDRAM
SW00410
1999 Oct 19
4
Philips Semiconductors
Product specification
50-150 MHz 1:9 SDRAM clock driver
PCK2509S
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL AVCC VCC IIK VI IOK VO IO TSTG PARAMETER Supply voltage range Supply voltage range Input clamp current Input voltage range Output clamp current Output voltage range DC output source or sink current Storage temperature range VI < 0 Note 3 VO > VCC or VO < 0 Notes 3, 4 VO = 0 to VCC -65 -0.5 -0.5 CONDITION Note 2 -0.5 LIMITS MIN MAX < VCC + 0.7 +4.6 -50 6.5 50 VCC + 0.5 50 +150 UNIT V V mA V mA V mA C
PTOT Power dissipation per package 700 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. AVCC must not exceed VCC 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 4. This value is limited to 4.6 V maximum.
RECOMMENDED OPERATING CONDITIONS1
SYMBOL VCC, AVCC VIH VIL VI Tamb PARAMETER Supply voltage HIGH level input voltage LOW level input voltage Input voltage Operating ambient temperature range in free air 0 0 CONDITIONS LIMITS MIN 3 2 0.8 VCC +70 MAX 3.6 UNIT V V V V C
NOTE: 1. Unused inputs must be held high or low to prevent them from floating.
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise specified) SYMBOL VIK VOH PARAMETER Input clamp voltage HIGH level output voltage TEST CONDITIONS AVCC, VCC (V) 3 MIN to MAX 3 3 MIN to MAX VOL II ICC ICCA ICC CI CO LOW level output voltage Input current Quiescent supply current AVCC power supply current Additional supply current per input pin Input capacitance Output capacitance 3 3 3.6 3.6 AVCC = 3.3 3.3 to 3.6 3.3 3.3 One input at VCC - 0.6V; other inputs at VCC or GND VI = VCC or GND VO= VCC or GND 2.8 5.4 OTHER II = -18mA IOH = - 100A IOH = - 12mA IOH = - 6mA IOL = 100A IOL = 12mA IOL = 6mA VI = VCC or GND VI = VCC or GND; IO = 0, outputs: LOW or HIGH 30 VCC - 0.2 2.1 2.4 - - - 0.2 0.8 0.55 5 10 50 500 A A A A pF pF V V MIN LIMITS TYP MAX -1.2 UNIT V
1999 Oct 19
5
Philips Semiconductors
Product specification
50-150 MHz 1:9 SDRAM clock driver
PCK2509S
TIMING REQUIREMENTS
Over recommended ranges of supply voltage and operating free-air temperature. SYMBOL fCLK Clock frequency Input clock duty cycle Stabilization time1 PARAMETER MIN 50 40 MAX 150 60 1 UNIT MHz % ms
NOTE: 1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable.
SWITCHING CHARACTERISTICS
Over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF 1 PARAMETER tphase error 2 tphase error, - jitter 3 tSK(0) 4 jitter(peak-peak) jitter (cycle-cycle) Duty cycle reference tr tf FROM (INPUT)/CONDITION CLKIN = 100 MHz to 133 MHz CLKIN = 66 MHz CLKIN = 100 MHz to 133 MHz Any Y or FBOUT CLKIN = 66 MHz to 133 MHz F(CLKIN > 60 MHz) VO = 0.4 to 2 V VO = 0.4 to 2 V TO (OUTPUT) FBIN FBIN Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT Any Y or FBOUT -80 |65| 47 2.5 2.5 53 1 1 VCC, AVCC = 3.3 V 0.3 V MIN -100 -125 -50 TYP MAX 100 125 50 200 80 UNIT ps ps ps ps ps % V/ns V/ns
NOTES: 1. These parameters are not production tested. 2. This is considered as static phase error. 3. Phase error does not include jitter. (tphase error = static tphase error - jitter (cycle-cycle)). 4. The tSK(0) specification is only valid for equal loading of all outputs.
PARAMETER MEASUREMENT INFORMATION
3V
INPUT
50% VCC 0V tpe
FROM OUTPUT UNDER TEST 30pF 500
OUTPUT
2V 0.4V tr
50% VCC
2V 0.4V tf
VOH VOL
LOAD CIRCUIT FOR OUTPUTS
VOLTAGE WAVEFORMS & PHASE ERROR TIMES
NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 100MHz, ZO = 50 , tr 1.2ns, tf 1.2ns. 3. The outputs are measured one at a time with one transition per measurement.
SW00384
Figure 1. Load Circuit and Voltage Waveforms
1999 Oct 19
6
Philips Semiconductors
Product specification
50-150 MHz 1:9 SDRAM clock driver
PCK2509S
CLKIN
FBIN
tphase error
FBOUT
ANY Y
tSK(0)
ANY Y
ANY Y
tSK(0)
SW00385
Figure 2. Phase Error and Skew Calculations
1999 Oct 19
7
Philips Semiconductors
Product specification
50-150 MHz 1:9 SDRAM clock driver
PCK2509S
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
1999 Oct 19
8
Philips Semiconductors
Product specification
50-150 MHz 1:9 SDRAM clock driver
PCK2509S
NOTES
1999 Oct 19
9
Philips Semiconductors
Product specification
50-150 MHz 1:9 SDRAM clock driver
PCK2509S
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 10-99 Document order number: 9397-750-06505
Philips Semiconductors
1999 Oct 19 10

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