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Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Document order number: MC33880/D Rev 3.0, 01/2004 Advance Information Configurable Octal Serial Switch with Serial Peripheral Interface I/O The 33880 device is an eight-output hardware configurable high-side/lowside switch with 8-bit serial input control. Two of the outputs may be controlled directly via microprocessor for PWM applications. The 33880 incorporates SMARTMOS technology, with CMOS logic, bipolar/MOS analog circuitry, and DMOS power MOSFETs. The 33880 controls various inductive or incandescent loads by directly interfacing with a microcontroller. The circuit's innovative monitoring and protection features include very low standby currents, cascade fault reporting, output-specific diagnostics, and independent shutdown of output. Features * Designed to Operate 5.5 V < VPWR < 24.5 V * 8-Bit SPI for Control and Fault Reporting, 3.3 V/5.0 V Compatible * Outputs Are Current Limited (0.8 A to 2.0 A) to Drive Incandescent Lamps * Output Voltage Clamp Is +45 V (Typical) (Low-Side Drive) and -20 V (Typical) (High-Side Drive) During Inductive Switching * Internal Reverse Battery Protection on VPWR * Loss of Ground or Supply Will Not Energize Loads or Damage IC * Maximum 5.0 A IPWR Standby Current at 13 V VPWR up to 95C * RDS(ON) of 0.55 at 25C Typical * Short Circuit Detect and Current Limit with Automatic Retry * Independent Overtemperature Protection * 32-Pin SOIC Has Pins 8, 9, 24, and 25 Grounded for Thermal Performance 33880 CONFIGURABLE OCTAL SERIAL SWITCH WITH SERIAL PERIPHERAL INTERFACE Freescale Semiconductor, Inc... DW SUFFIX CASE 751F-05 28-PIN SOIC DWB SUFFIX CASE 1324-02 32-PIN SOIC ORDERING INFORMATION Device MC33880DW/R2 MC33880DWB/R2 Temperature Range (TA) -40C to 125C Package 28 SOIC 32 SOIC Simplified Application Diagram 33880 Simplified Application Diagram +5.0 V VPWR VBAT 33880 A0 VPWR VDD EN DI SCLK CS DO IN5 IN6 GND D1 D2 D3 D4 S1 S2 S3 S4 M D5 D6 D7 D8 S5 S6 S7 S8 High-Side Drive MOSI SCLK MCU CS MISO PWM1 PWM2 H-Bridge Configuration VBAT VBAT Low-Side Drive This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc. 2004 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. VDD VPWR ~50 A __ CS SCLK DI DO Internal Bias Charge Pump Overvoltage Shutdown/POR Sleep State GND OV, POR, SLEEP Freescale Semiconductor, Inc... EN ~50 A SPI and Interface Logic SPI Bit 0 Typical of All 8 Output Drivers TLIM IN5 ~50 A Enable SPI Bit 4 Gate Drive Control Current Limit Open Load Detect Current ~650 A D1 D2 D3 D4 D7 D8 S1 S2 S3 S4 S7 S8 Drain Outputs IN6 ~50 A IN5 + - + - Open/Short Comparator + _ ~1.5 V Open/Short Threshold Source Outputs TLIM Gate Drive Control Current Limit Open Load Detect Current ~650 A D5 D6 Drain Outputs + - + - Open/Short Comparator +_ S5 S6 Source Outputs ~1.5 V Open/Short Threshold Figure 1. 33880 Simplified Internal Block Diagram 33880 2 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. GND VDD S8 S8 D8 S2 D2 S1 D1 D6 S6 IN6 EN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DO VPWR S7 S7 D7 S4 D4 S3 D3 D5 S5 IN5 CS SCLK DI Freescale Semiconductor, Inc... SOIC 28-PIN FUNCTION DESCRIPTON Pin 1 2 3, 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25, 26 Pin Name GND VDD S8 D8 S2 D2 S1 D1 D6 S6 IN6 EN SCLK DI CS IN5 S5 D5 D3 S3 D4 S4 D7 S7 Digital ground. Logic supply voltage. Logic supply must be switched off for low current mode (VDD below 3.9 V). Output 8 MOSFET source pins. Output 8 MOSFET drain pin. Output 2 MOSFET source pin. Output 2 MOSFET drain pin. Output 1 MOSFET source pin. Output 1 MOSFET drain pin. Output 6 MOSFET drain pin. Output 6 MOSFET source pin. PWM direct control input pin for output 6. IN6 is "OR" with SPI bit. Enable input. Allows control of outputs. Active high. SPI control clock input pin. SPI control data input pin from MCU to the 33880. Logic [1] activates output. SPI control chip select input pin from MCU to the 33880. Logic [0] allows data to be transferred in. PWM direct control input pin for output 5. IN5 is "OR" with SPI bit. Output 5 MOSFET source pin. Output 5 MOSFET drain pin. Output 3 MOSFET drain pin. Output 3 MOSFET source pin. Output 4 MOSFET drain pin. Output 4 MOSFET source pin. Output 7 MOSFET drain pin. Output 7 MOSFET source pins. Description MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33880 3 Freescale Semiconductor, Inc. SOIC 28-PIN FUNCTION DESCRIPTON (continued) Pin 27 28 Pin Name VPWR DO Description Power supply pin to the 33880. VPWR has internal reverse battery protection. SPI control data output pin from the 33880 to the MCU. DO = 0 no fault, DO = 1 specific output has fault. Freescale Semiconductor, Inc... 33880 4 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. GND VDD S8 S8 D8 S2 D2 GND GND S1 D1 D6 S6 IN6 EN SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DO VPWR S7 S7 D7 S4 D4 GND GND S3 D3 D5 S5 IN5 CS DI Freescale Semiconductor, Inc... SOIC 32-PIN FUNCTION DESCRIPTON Pin 1, 8, 9, 24, 25 2 3, 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 26 27 28 29, 30 Pin Name GND VDD S8 D8 S2 D2 S1 D1 D6 S6 IN6 EN SCLK DI CS IN5 S5 D5 D3 S3 D4 S4 D7 S7 Digital ground. Logic supply voltage. Logic supply must be switched off for low current mode (VDD below 3.9 V). Output 8 MOSFET source pins. Output 8 MOSFETdrain pin. Output 2 MOSFET source pin. Output 2 MOSFET drain pin. Output 1 MOSFET source pin. Output 1 MOSFET drain pin. Output 6 MOSFETdrain pin. Output 6 MOSFET source pin. PWM direct control input pin for output 6. IN6 is "OR" with SPI bit. Enable input. Allows control of outputs. Active high. SPI control clock input pin. SPI control data input pin from MCU to the 33880. Logic [1] activates output. SPI control chip select input pin from MCU to the 33880. Logic [0] allows data to be transferred in. PWM direct control input pin for output 5. IN5 is "OR" with SPI bit. Output 5 MOSFET source pin. Output 5 MOSFET drain pin. Output 3 MOSFET drain pin. Output 3 MOSFET source pin. Output 4 MOSFET drain pin. Output 4 MOSFET source pin. Output 7 MOSFET drain pin. Output 7 MOSFET source pins. Description MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33880 5 Freescale Semiconductor, Inc. SOIC 32-PIN FUNCTION DESCRIPTON (continued) Pin 31 32 Pin Name VPWR DO Description Power supply pin to the 33880. VPWR has internal reverse battery protection. SPI control data output pin from the 33880 to the MCU. DO = 0 no fault, DO = 1 specific output has fault. Freescale Semiconductor, Inc... 33880 6 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Rating VDD Supply Voltage (Note 1) CS, DI, DO, SCLK, IN5, IN6, and EN (Note 1) Symbol VDD - VPWR - Value -0.3 to 7.0 -0.3 to 7.0 -16 to 50 Unit VDC VDC VDC VDC VPWR Supply Voltage (Note 1) Drain 1-8 (Note 2) 5.0 mA IOUT 0.3 A -18 to 40 - -28 to 40 VOC VOC ECLAMP 40 to 55 -15 to -25 50 VDC VDC mJ V VESD1 VESD2 TSTG TC TJ - PD 1.3 1.7 RJA RJA RJL 94 70 18 2000 200 -55 to 150 -40 to 125 -40 to 150 -40 to 150 VDC Freescale Semiconductor, Inc... Source 1-8 (Note 3) 5.0 mA IOUT 0.3 A Output Voltage Clamp Low-Side Drive (Note 4) Output Voltage Clamp High-Side Drive (Note 4) Output Clamp Energy (Note 5) ESD Voltage Human Body Model (Note 6) Machine Model (Note 7) Storage Temperature Operating Case Temperature Operating Junction Temperature Maximum Junction Temperature Power Dissipation (TA = 25C) (Note 8) 28 SOIC, Case 751F-05 32 SOIC, Case 1324-02 Thermal Resistance, Junction-to-Ambient, 28 SOIC, Case 751F-05 Thermal Resistance, Junction-to-Ambient, 32 SOIC, Case 1324-02 Thermal Resistance, Junction-to-Thermal Ground Leads, 32 SOIC, Case 1324-02 Notes 1. 2. 3. 4. 5. 6. 7. 8. C C C C W C/W C/W Exceeding these limits may cause malfunction or permanent damage to the device. Configured as low-side driver with 300 mA load as current limit. Configured as high-side driver with 300 mA load as current limit. With outputs OFF and 10 mA of test current for low-side driver, 30 mA test current for high-side driver. Maximum output clamp energy capability at 150C junction temperature using single non-repetitive pulse method. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). Maximum power dissipation with no heatsink used. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33880 7 Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions of 4.75 V VDD 5.25 V, 9.0 V VPWR 16 V, -40C TC 125C unless otherwise noted. Typical values, where applicable, reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C. Characteristic Symbol Min Typ Max Unit POWER INPUT Supply Voltage Range Fully Operational Supply Current Sleep State Supply Current (VDD and EN = 0 V, VPWR = 16 V) Temperature = -40C to 95C Temperature = 95C to 125C IPWR(ON) IPWR(SS) - - VOV VOV(HYS) VDD IDD VDD(UNVOL) VDD(UNVOL-HYS) 25 0.15 4.75 0.5 3.9 100 2.0 5.0 27 0.8 - 2.6 4.3 150 5.0 20 30 2.5 5.25 4.0 4.7 300 V V V mA V mV VPWR(FO) 5.5 - - 8.0 24.5 14 mA A V Freescale Semiconductor, Inc... Overvoltage Shutdown Overvoltage Shutdown Hysteresis Logic Supply Voltage Logic Supply Current Logic Supply Undervoltage Lockout Threshold Logic Supply Undervoltage Hysteresis POWER OUTPUT Drain-to-Source ON Resistance (VPWR = 16 V) IOUT = 0.25 A, TJ = 125C IOUT = 0.25 A, TJ = 25C IOUT = 0.25 A, TJ = -40C Output Self-Limiting Current High-Side and Low-Side Configurations VPWR = 16 V Output Fault Detect Threshold (Note 9), (Note 10) Outputs Programmed OFF Output Off Open Load Detect Current (Note 9) Outputs Programmed OFF Output Clamp Voltage Low-Side Drive ID = 10 mA Output Clamp Voltage High-Side Drive IS = -30 mA Output Leakage Current High-Side and Low-Side Configuration VDD = 0 V, VDS = 16 V Overtemperature Shutdown (Note 10) Overtemperature Shutdown Hysteresis (Note 10) TLIM TLIM(HYST) IOUT(LKG) - 155 5.0 1.0 - 10 7.0 185 15 VOC(HSD) -15 -20 -25 A VOC(LSD) 40 45 55 V IOCO 0.30 0.55 1.0 V VOUTth(F) 1.0 - 3.0 mA IOUT(LIM) 0.8 1.4 2.0 V RDS(ON) - - - 0.75 0.55 0.45 1.1 0.85 0.80 A C C Notes 9. Output Fault Detect Thresholds with outputs programmed OFF. Output fault detect threshold are the same for output open and shorts. 10. This parameter is guaranteed by design but is not production tested. 33880 8 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions of 4.75 V VDD 5.25 V, 9.0 V VPWR 16 V, -40C TC 125C unless otherwise noted. Typical values, where applicable, reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C. Characteristic Symbol Min Typ Max Unit DIGITAL INTERFACE Input Logic Voltage Thresholds (Note 11) IN5, IN6, and EN Input Logic Current IN5, IN6, EN = 0 V IN5, IN6, and EN Pull-Down Current 0.8 V to VDD IIN5, IN6, EN 30 ISCK, SI, TriSO -10 IICS -10 IICS -30 VDOHIGH VDD - 0.8 VDOLOW - CIN - - - 0.4 20 pF - VDD V - -100 V - 10 A - 10 A 45 100 A VINLOGIC IIN5, IN6, EN -10 - 10 A 0.8 - 2.2 V A Freescale Semiconductor, Inc... SCLK, DI, and Tri-State DO Input 0 V to VDD CS Input Current CS = VDD CS Pull-Up Current CS = 0 V DO High-State Output Voltage IDO-HIGH = -200 A DO Low-State Output Voltage IDO-HIGH = 1.6 mA Input Capacitance on SCLK, DI, Tri-State DO, IN5, IN6, EN (Note 12) Notes 11. Upper and lower logic threshold voltage levels apply to DI, CS, SCLK, IN5, IN6, and EN. 12. This parameter is guaranteed by design but is not production tested. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33880 9 Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions of 4.75 V VDD 5.25 V, 9.0 V VPWR 16 V, -40C TC 125C unless otherwise noted. Typical values, where applicable, reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C. Characteristic Symbol Min Typ Max Units POWER OUTPUT TIMING Output Slew Rate Low-Side Configuration (Note 13) RL = 620 Output Slew Rate Low-Side Configuration (Note 13) RL = 620 tF 0.1 tR 0.1 tF 0.1 tDLY(ON) tDLY(OFF) tFAULT 1.0 1.0 100 0.3 15 30 - 1.2 50 100 300 s s s 0.3 1.2 V/s 0.5 1.2 V/s tR 0.1 0.5 1.2 V/s V/s Freescale Semiconductor, Inc... Output Slew Rate High-Side Configuration (Note 13) RL = 620 Output Slew Rate High-Side Configuration (Note 13) RL = 620 Output Turn ON Delay Time, High-Side and Low-Side Configuration (Note 14) Output Turn OFF Delay Time, High-Side and Low-Side Configuration (Note 14) Output Fault Delay Time (Note 15) Notes: 13. Output Rise and Fall time respectively measured across a 620 resistive load at 10 to 90 percent and 90 to 10 percent voltage points. 14. Output turn ON and OFF delay time measured from 50 percent rising edge of CS to 90 and 10 percent of initial voltage. 15. Duration of fault before fault bit is set. Duration between access times must be greater than 300 s to read faults. 33880 10 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions of 4.75 V VDD 5.25 V, 9.0 V VPWR 16 V, -40C TC 125C unless otherwise noted. Typical values, where applicable, reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C. Characteristic Symbol Min Typ Max Units DIGITAL INTERFACE TIMING Recommended Frequency of SPI Operation Required Low State Duration on VDD for Reset (Note 16) VDD 0.2 V Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) tLEAD tLAG tDI(su) tDI(HOLD) tR(DI) tF(DI) tDO(EN) tDO(DIS) tVALID - tRESET - 100 50 16 20 - - - - - 4.0 - - - - 5.0 5.0 - - 25 10 - - - - - - 60 60 60 ns ns ns ns ns ns ns ns ns - 4.0 6.0 MHz s Freescale Semiconductor, Inc... Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) DI to Falling Edge of SCLK (Required Setup Time) Falling Edge of SCLK to DI (Required Hold Time) DI, CS, SCLK Signal Rise Time (Note 17) DI, CS, SCLK Signal Fall Time (Note 17) Time from Falling Edge of CS to DO Low Impedance (Note 18) Time from Rising Edge of CS to DO High Impedance (Note 19) Time from Rising Edge of SCLK to DO Data Valid (Note 20) Notes 16. 17. 18. 19. 20. This parameter is guaranteed by design but is not production tested. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at DO pin. Time required for output status data to be terminated at DO pin Time required to obtain valid data out from DO following the rise of SCLK. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33880 11 Freescale Semiconductor, Inc. Timing Diagrams CS 0.2 VDD tLEAD tLAG SCLK 0.7 VDD 0.2 VDD tDI(SU) tDI(HOLD) DI 0.7 VDD 0.2 VDD MSB in Freescale Semiconductor, Inc... tDO(EN) tVALID 0.7 VDD 0.2 VDD tDO(DIS) DO MSB out LSB out Figure 2. SPI Timing Diagram VDD = 5.0 V VDD = 5.0 V VPull-Up = 2.5 V SCLK 33880 Under Test DO CL = 200 pF 33880 RL = 1.0 k DO CL = 200 pF CS Under Test NOTE: CL represents the total capacitance of the test fixture and probe. NOTE: CL represents the total capacitance of the test fixture and probe. Figure 3. Valid Data Delay Time and Valid Time Test Circuit Figure 4. Enable and Disable Time Test Circuit 33880 12 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. tR(DI) VDD = 5.0 V VPWR = 13 V CS 33880 Under Test RL = 620 Output CL DO (Tri-State to Low) 0.2 VDD (2.5 V) <50 ns 90% 10% tDO(EN) 90% tF(DI) <50 ns 0.7 VDD 5.0 V CS 0 tDO(dis) VTri-State 10% tDO(EN) NOTE: CL represents the total capacitance of the test fixture and probe. 90% DO (Tri-State to High) 10% tDO(DIS) tSO(DIS) VOH Freescale Semiconductor, Inc... VTri-State Figure 5. Switching Time Test Circuit Figure 7. Enable and Disable Time Waveforms tR(DI) 0.7 VDD (2.5 V) SCLK < 50 ns 50% tF(DI) tR(DI) < 50 ns 5.0 V 0.2 VDD 0 CS 0.2 VDD (2.5 V) DO (Tri-State to Low) <50 ns 90% 10% tDO(EN) 90% tF(DI) <50 ns 0.7 VDD tDO(DIS) 5.0 V 0 tDLY(LH) DO (Low-to-High) DO (High-to-Low) 0.2 VDD tVALID 0.7 VDD tDLY(HL) tr(DO) 0.7 VDD VOH VTri-State VOL tDO(EN) VOH 0.2 VDD DO VOL (Tri-State to High) 10% 90% 10% t SO(DIS) tDO(DIS) VOH VTri-State Figure 6. Valid Data Delay Time and Valid Time Waveforms Figure 8. Turn-ON/OFF Waveforms MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33880 13 Freescale Semiconductor, Inc. Typical Electrical Characteristics 14 12 10 8 6 4 2 -40 -25 0 25 50 75 100 125 All Outputs OFF VPWR @ 16 V IPWR Current into VPWR Pin (mA) 1.4 1.2 1.0 RDS(ON) () 0.8 0.6 0.4 0.2 VPWR @ 16 V All Outputs ON Freescale Semiconductor, Inc... -40 -25 0 25 50 75 100 125 TA, Ambient Temperature (C) Figure 9. IPWR vs. Temperature Sleep State IPWR versus Temperature IPWR Current into VPWR Pin (A) IPWR Current into VPWR Pin (uA) 14 14 12 12 10 10 8 8 6 6 4 4 2 2 VPWR @ 16 V TA, Ambient Temperature (C) Figure 12. RDS(ON) vs. Temperature @ 250 mA 1.4 1.2 RDS(ON) () 1.0 0.8 0.6 0.4 0.2 VPWR @ 16 V -40 -25 -40 -25 25 50 75 100 25 50 75 100 TA, Ambient Temperature TA, Ambient Temperature (C) 0 0 125 125 0 5.0 10 15 20 25 VPWR (V) Figure 13. RDS(ON) vs. VPWR @ 250 mA Figure 10. Sleep State IPWR vs. Temperature IPWR Current into VPWR Pin (A) 70 IOUT(LIM), Current Limit (A) 60 50 40 30 20 10 0 5.0 10 VPWR Figure 11. Sleep State IPWR vs. VPWR 15 20 25 TA = 25C 1.6 1.5 1.4 1.3 1.2 1.1 1.0 VPWR @ 16 V -40 -25 0 25 50 75 100 125 TA, Ambient Temperature (C) Figure 14. Current Limit IOUT(LIM) vs. Temperature 33880 14 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. 1.4 IOCO, Open Load (mA) 1.2 1.0 0.8 0.6 0.4 0.2 VPWR @ 16 V High-Side Configuration 1.4 IOCO Open Load (mA) 1.2 1.0 0.8 0.6 0.4 0.2 0 5.0 10 15 20 25 TA = 25C Freescale Semiconductor, Inc... -40 -25 0 25 50 75 100 125 TA, Ambient Temperature (C) Figure 15. Open Load Detect Current vs. Temperature VPWR (V) Figure 16. Open Load Detect Current vs. VPWR IOUT(LKG), Leakage Current (A) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 5.0 10 15 20 25 TA = 25C VPWR (V) Figure 17. Sleep State Output Leakage vs. VPWR MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33880 15 Freescale Semiconductor, Inc. SYSTEM/APPLICATION INFORMATION INTRODUCTION The 33880 is an eight-output hardware configurable power switch with 8-bit serial control. The 33880 incorporates SMARTMOS 5 technology with CMOS logic, bipolar/MOS analog circuitry, and independent double diffused DMOS power output transistors. Many benefits are realized as a direct result of using this mixed technology. A simplified internal block diagram of the 33880 is shown in Figure 1, page 2. The 33880 device uses high-efficiency updrain power DMOS output transistors exhibiting low drain-to-source ON resistance values (RDS(ON) 0.55 at 25C) and dense CMOS control logic. All outputs have independent voltage clamps to provide fast inductive turn-off and transient protection. Operational bias currents of less than 4.0 mA on VDD and 12 mA on VPWR with any combination of outputs ON are a direct result of using SMARTMOS 5 technology. MCU INTERFACE DESCRIPTION Freescale Semiconductor, Inc... In operation the 33880 functions as an eight-output serial switch serving as a microcontroller (MCU) bus expander and buffer with fault management and fault reporting features. In doing so, the device directly relieves the MCU of the fault management functions. This device directly interfaces to an MCU using a Serial Peripheral Interface (SPI) for control and diagnostic readout. Figure 18 (below) and Figure 21, page 17, illustrate the basic SPI configuration between an MCU and one 33880. MC68HCxx Microcontroller MOSI Shift Register MISO DO DI Shift Register SCLK Parallel Port CS MC68xx MISO MCU DO DI with SPI Interface 33880 8 Outputs MOSI CS SCLK DO DI CS SCLK DO DI 33880 8 Outputs 33880 8 Outputs 33880 Figure 19. 33880 SPI System Daisy Chain Multiple 33880 devices can be controlled in a parallel input fashion using the SPI. Figure 20 illustrates 24 loads being controlled by three dedicated parallel MCU ports used for chip select. MOSI SCLK SCLK Receive Buffer Parallel Ports CS To Logic Figure 18. SPI Interface with Microcontroller All inputs are compatible with 5.0 V and 3.3 V CMOS logic levels and incorporate positive logic. Whenever an input is programmed to a logic low state (<0.8 V) the corresponding output will be OFF. Conversely, whenever an input is programmed to a logic high state (>2.2 V), the output being controlled will be ON. Diagnostics are treated in a similar manner. Outputs with a fault will feedback (via DO) to the microcontroller as a logic [1] while normal operating outputs will provide a logic [0]. Figure 19 illustrates the Daisy Chain configuration using the 33880. Data from the MCU is clocked daisy chain through each device while the Chip Select (CS) bit is commanded low by the MCU. During each clock cycle output status from the daisy chain, the 33880 is being transferred to the MCU via the Master In Slave Out (MISO) line. On rising edge of CS data stored in the input register is then transferred to the output driver. MISO DI SCLK DO CS 8 Outputs MC68xx Microcontroller SPI DI SCLK DO CS 8 Outputs Parallel Ports A B C DI SCLK DO CS 8 Outputs Figure 20. Parallel Input SPI Control 33880 16 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Figure 21. Data Transfer Timing MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33880 17 Freescale Semiconductor, Inc. FUNCTIONAL PIN DESCRIPTION CS Pin The system MCU selects the 33880 to communicate through the use of the CS pin. Whenever the pin is in a logic low state, data can be transferred from the MCU to the 33880 device and vice versa. Clocked-in data from the MCU is transferred from the 33880 shift register and latched into the power outputs on the rising edge of the CS signal. On the falling edge of the CS signal, output status information is transferred from the power outputs status register into the device's shift register. The falling edge of CS enables the DO output driver. Whenever the CS pin goes to a logic low state, the DO pin output is enabled, thereby allowing information to be transferred from the 33880 to the MCU. To avoid any spurious data, it is essential the high-to-low transition of the CS signal occurs only when SCLK is in a logic low state. reported as logic [1]. Conversely, normal operating outputs with non-faulted loads are reported as logic [0]. The first positive transition of SCLK will make output eight status available on DO pin. Each successive positive clock will make the next output status available. The DI/DO shifting of data follows a first-infirst-out protocol with both input and output words transferring the most significant bit (MSB) first. EN Pin The EN pin on the 33880 device either enables or disables the internal charge pump. The EN pin must be high for this device to enhance the gates of the output drivers, perform fault detection, and reporting. Active outputs during a low transition of the EN pin will become active again when the EN transitions high. If this feature is not required, it is recommended the EN pin be connected to VDD. Freescale Semiconductor, Inc... SCLK Pin The system clock pin (SCLK) clocks the internal shift registers of the 33880. The serial data input (DI) is latched into the input shift register on the falling edge of the SCLK. The serial data output pin (DO) shifts data out of the shift register on the rising edge of the SCLK signal. False clocking of the shift register must be avoided to guarantee validity of data. It is essential the SCLK pin be in a logic low state whenever chip select pin (CS) makes any transition. For this reason, it is recommended the SCLK pin is commanded to a logic low state when the device is not accessed (CS in logic high state). When the CS is in a logic high state, any signal at the SCLK and DI pin is ignored and the DO is tri-stated (high impedance). IN5 and IN6 Pins The IN5 and IN6 pins command inputs allowing outputs five and six to be used in PWM applications. IN5 and IN6 pins are ORed with the SPI communication input. For SPI control of outputs five and six, the IN5 and IN6 pins should be grounded or held low by the microprocessor. In the same manner, when using the PWM feature the SPI port must command the outputs off. Maximum PWM frequency for each output is 2.0 kHz. VDD Pin The VDD pin supplies logic power to the 33880 device and is used for power-on reset (POR). To achieve low standby current on VPWR supply, power must be removed from the VDD pin. The device will be in reset with all drivers off when VDD is below 3.9 VDC. DI Pin This pin is used for serial instruction data input. DI information is latched into the input register on the falling edge of SCLK. A logic high state present on DI will program a specific output on. The specific output will turn on with the rising edge of the CS signal. Conversely, a logic low state present on the DI pin will program the output off. The specific output will turn off with the rising edge of the CS signal. To program the eight outputs of the 33880 device on or off, enter the DI pin beginning with Output 8, followed by Output 7, Output 6, and so on to Output 1. For each falling edge of the SCLK while CS is logic low, a data bit instruction (on or off) is loaded into the shift register per the data bit DI state. Eight bits of entered information fills the shift register. To preserve data integrity, do not transition DI as SCLK transitions from a high to low logic state. D1-D8 Pins The D1-D8 pins are the open drain outputs of the 33880. For High-Side Drive configurations, the drain pins are connected to battery supply. In Low-Side Drive configurations, the drain pins are connected to the low side of the load. All outputs may be configured individually as desired. When Low-Side Drive is used, the 33880 limits the positive transient for inductive loads to 45 V. S1-S8 Pins The S1-S8 pins are the source outputs of the 33880. For High-Side Drive configurations, the source pins are connected directly to the load. In Low-Side Drive configurations the source is connected to ground. All outputs may be configured individually as desired. When High-Side drive is used, the 33880 will limit the negative transient for inductive loads to -20 V. DO Pin The serial data output (DO) pin is the output from the shift register. The DO pin remains tri-state until the CS pin goes to a logic low state. All faults on the 33880 device are reported as logic [1] through the DO data pin. Regardless of the configuration of the driver, open loads and shorted loads are 33880 18 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. FAULT OPERATION On each SPI communication, an 8-bit command word is sent to the 33880 and an 8-bit fault word is received from the 33880. The Most Significant Bit (MSB) is sent and received first (see below). MSB OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 LSB OUT1 Command Register Definition: 0 = Output Command Off 1 = Output Command On Fault Register Definition: 0 = No fault 1 = Fault. Table 1. Fault Operation Serial Output (SO) Pins Reports Overtemperature Fault reported by Serial Output (DO) pin. DO pin reports short to battery/supply or overcurrent condition. Not reported. DO pin reports output OFF open load condition. Freescale Semiconductor, Inc... Overcurrent Output ON Open Load Fault Output OFF Open Load Fault Device Shutdowns Overvoltage Total device shutdown at VPWR = 25 V to 30 V. Resumes normal operation with proper voltage. All outputs assuming the previous state upon recovery from overvoltage. Overtemperature Only the output experiencing an overtemperature fault shuts down. Output assumes previous state upon recovery from overtemperature. APPLICATIONS Power Consumption The 33880 device has been designed with one sleep and one operational mode. In the sleep mode (VDD 2.0 V), the current consumed by VPWR pin is less than 25 A. To place the 33880 in the sleep mode, turn all outputs off, then remove power from VDD and the EN (enable) input pin. Prior to removing power from the device, it is recommended all control inputs from the microcontroller are low. During normal operation, 4.0 mA will be drawn from the VDD supply and 12 mA from the VPWR supply. outputs are paralleled). Paralleling outputs from two or more different IC devices are possible but not recommended. Fault Logic Operation Fault logic of the 33880 device has been greatly simplified over other devices using SPI communications. As command word one is being written into the shift register, a fault status word is being simultaneously written out and received by the MCU. Regardless of the configuration, with no outputs faulted, all status bits being received by the MCU will be zero. When outputs are faulted (off state open circuit or on state short circuit/overtemperature), the status bits being received by the MCU will be one. The distinction between open circuit fault and short circuit/overtemperature is completed via the command word. For example, when a zero command bit is sent and a one fault is received in the following word, the fault is open/short-tobattery for high-side drive or open/short to ground for low-side drive. In the same manner, when a one command bit is sent and a one fault is received in the following word the fault is a shortto-ground/overtemperature for high-side drive or short-tobattery/overtemperature for low-side drive. The timing between two write words must be greater than 300 s to allow adequate time to sense and report the proper fault status. Paralleling of Outputs Using MOSFETs as output switches allows the connection of any combination of outputs together. RDS(ON) of MOSFETs have an inherent positive temperature coefficient, providing balanced current sharing between outputs without destructive operation. The device can even be operated with all outputs tied together. This mode of operation may be desirable in the event the application requires lower power dissipation or the added capability of switching higher currents. Performance of parallel operation results in a corresponding decrease in RDS(ON) while the outputs OFF open load detect currents and the output current limits increase correspondingly (by a factor of eight if all MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33880 19 Freescale Semiconductor, Inc. SPI Integrity Check It is recommended that one check the integrity of the SPI communication with the initial power-up of the VDD and EN pins. After initial system start-up or reset, the MCU will write one 16-bit pattern to the 33880. The first eight bits read by the MCU will be the fault status of the outputs, while the second eight bits will be the first byte of the bit pattern. Bus integrity is confirmed by the MCU receiving the same bit pattern it sent. Please note that the second byte the MCU sends to the device is the command byte and will be transferred to the outputs with rising edge of CS. This device has an internal 650 A current source connected from drain to source of the output MOSFET. This prevents either configuration of the driver from having a floating output. To achieve low sleep mode quiescent currents, the open load detect current source of each driver is switched off when VDD is removed. During output switching, especially with capacitive loads, a false output OFF open load fault may be triggered. To prevent this false fault from being reported, an internal fault filter of 100 s to 300 s is incorporated. A false fault reporting is a function of the load impedance, RDS(ON) , COUT of the MOSFET, as well as the supply voltage, VPWR. The rising edge of CS triggers the built-in fault delay timer. The timer will time out before the fault comparator is enabled and the fault is detected. Once the condition causing the open load fault is removed, the device will resume normal operation. The open load fault however, will be latched in the output DO register for the MCU to read. Overtemperature Fault Freescale Semiconductor, Inc... Overtemperature detect and shutdown circuits are specifically incorporated for each individual output. The shutdown following an overtemperature condition is independent of the system clock or any other logic signal. Each independent output shuts down at 155C to 185C. When an output shuts down due to an overtemperature fault, no other outputs are affected. The MCU recognizes the fault by a one in the fault status register. After the 33880 device has cooled below the switch point temperature and 15C hysteresis, the output will activate unless told otherwise by the MCU via SPI to shut down. Shorted Load Fault A shorted load (overcurrent) fault can be caused by any output being shorted directly to supply or an output causing the device to current limit (linear short). There are two safety circuits progressively in operation during load short conditions providing system protection: 1. The device's output current is monitored in an analog fashion using SENSEFET approach and current limited. 2. The device's output thermal limit is sensed and when attained causes only the specific faulted output to shut down. The output will remain off until cooled. The device will then reassert the output automatically. The cycle will continue until the fault is remove or the command bit instructs the output off. Overvoltage Fault An overvoltage condition on the VPWR pin will cause the device to shut down all outputs until the overvoltage condition is removed. When the overvoltage condition is removed, the outputs will resume their previous state. This device does not detect an overvoltage on the VDD pin. The overvoltage threshold on the VPWR pin is specified as 25 V to 30 V with 1.0 V typical hysteresis. A VPWR overvoltage detect is global, causing all outputs to be turned OFF. Output OFF Open Load Fault An output OFF open load fault is the detection and reporting of an open load when the corresponding output is disabled (input bit programmed to a logic low state). The output OFF open load fault is detected by comparing the drain-to-source voltage of the specific MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose. An output off open load fault is indicated when the drain-tosource voltage is less than the output threshold voltage (VTHRES) of 1.0 V to 3.0 V. Hence, the 33880 will declare the load open in the OFF state when the VDS is less than 1.0 V. Undervoltage Shutdown An undervoltage VDD condition will result in the global shutdown of all outputs. The undervoltage threshold is between 3.9 V and 4.6 V. When VDD goes below the threshold, all outputs are turned OFF and the Fault Status (FS) register is cleared. As VDD returns to normal levels, the FS register will resume normal operation. An undervoltage condition at the VPWR pin will not cause output shutdown and reset. When VPWR is between 5.5 V and 9.0 V, the output will operate per the command word. However, the status as reported by the serial data output (DO) pin may not be accurate below 9.0 V VPWR. Proper operation at VPWR voltages below 5.5 V cannot be guaranteed. 33880 20 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com Freescale Semiconductor, Inc. Output Voltage Clamp Each output of the 33880 incorporates an internal voltage clamp to provide fast turn-off and transient protection of each output. Each clamp independently limits the drain-to-source voltage to 45 V for low-side drive configurations and -20 V for high-side drive configurations (see Figure 22). The total energy clamped (EJ ) can be calculated by multiplying the current area under the current curve (IA) times the clamp voltage (VCL). Characterization of the output clamps, using a single pulse non-repetitive method at 0.3 A, indicates the maximum energy to be 50 mJ at 150C junction temperature per output. Drain-to-Source Clamp Voltage (VCL = 45 V) SPI Configurations The SPI configuration on the 33880 device is consistent with other devices in the OSS family. This device may be used in serial SPI or parallel SPI with the 33291 and 33298. Different SPI configurations may be provided. For more information, contact Analog Products Division. Reverse Battery The 33880 has been designed with reverse battery protection on the VPWR pin. However, the device does not protect the load from reverse battery. During the reverse battery condition, current will flow through the load via the output MOSFET substrate diode. Under this circumstance relays may energize and lamps will turn on. If load reverse battery protection is desired, a diode must be placed in series with the load. Freescale Semiconductor, Inc... Drain Voltage Drain Current (ID = 0.3 A) Clamp Energy (EJ = IA x VCL) Drain-to-Source ON Voltage (VDS(ON)) Current Area (IA) GND Drain-to-Source ON Voltage (VDS(ON)) Time VBAT Current Area (IA) GND Time Clamp Energy (EJ = IA x VCL) Source Current (IS = 0.3 A) Source Clamp Voltage (VCL = -20 V) Source Voltage Figure 22. Output Voltage Clamping MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33880 21 Freescale Semiconductor, Inc. PACKAGE DIMENSIONS DW SUFFIX 28-PIN SOIC PLASTIC PACKAGE CASE 751-05 ISSUE F A D 28 15 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.13 0.29 0.35 0.49 0.23 0.32 17.80 18.05 7.40 7.60 1.27 BSC 10.05 10.55 0.41 0.90 0 8 M E H 1 14 PIN 1 IDENT Freescale Semiconductor, Inc... B 0.25 M B e B 0.025 M A1 0.10 SEATING PLANE L C C CA S DIM A A1 B C D E e H L B S 33880 22 MOTOROLA ANALOG For More Information On This Product,INTEGRATED CIRCUIT DEVICE DATA Go to: www.freescale.com A Freescale Semiconductor, Inc. DWB SUFFIX 32-PIN SOIC PLASTIC PACKAGE CASE 1324-02 ISSUE A 10.3 7.6 7.4 C 5 1 32 B 9 2.65 2.35 30X 0.65 Freescale Semiconductor, Inc... PIN 1 ID 4 B B 9 11.1 10.9 C L 16 17 5.15 2X 16 TIPS A 32X SEATING PLANE 0.3 ABC A (0.29) 0.25 0.19 6 0.13 0.38 0.22 M BASE METAL 0.10 A NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4 MM PER SIDE. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. (0.203) A R0.08 MIN 0.25 GAUGE PLANE PLATING M MIN 0 0.29 0.13 CA B 8 8 0 SECTION A-A ROTATED 90 CLOCKWISE 0.9 0.5 SECTION B-B MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33880 23 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appl ication in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. (c) Motorola, Inc. 2004 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution: P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T., Hong Kong. 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 For More Information On This Product, Go to: www.freescale.com MC33880/D |
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