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| MC14016B Quad Analog Switch/ Quad Multiplexer The MC14016B quad bilateral switch is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each MC14016B consists of four independent switches capable of controlling either digital or analog signals. The quad bilateral switch is used in signal gating, chopper, modulator, demodulator and CMOS logic implementation. http://onsemi.com MARKING DIAGRAMS 14 PDIP-14 P SUFFIX CASE 646 1 14 SOIC-14 D SUFFIX CASE 751A 1 14 SOEIAJ-14 F SUFFIX CASE 965 MC14016B AWLYWW 1 14016B AWLYWW MC14016BCP AWLYYWW * * * * * * * Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Linearized Transfer Characteristics Low Noise -- 12 nV/Cycle, f 1.0 kHz typical Pin-for-Pin Replacements for CD4016B, CD4066B (Note improved transfer characteristic design causes more parasitic coupling capacitance than CD4016) For Lower RON, Use The HC4016 High-Speed CMOS Device or The MC14066B This Device Has Inputs and Outputs Which Do Not Have ESD Protection. Antistatic Precautions Must Be Taken. MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Symbol VDD Vin, Vout Iin ISW PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input Current (DC or Transient) per Control Pin Switch Through Current Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value - 0.5 to +18.0 - 0.5 to VDD + 0.5 10 25 500 - 55 to +125 - 65 to +150 260 Unit V V mA A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week ORDERING INFORMATION mA mW C C C Device MC14016BCP MC14016BD MC14016BDR2 MC14016BF MC14016BFEL Package PDIP-14 SOIC-14 SOIC-14 SOEIAJ-14 SOEIAJ-14 Shipping 2000/Box 55/Rail 2500/Tape & Reel See Note 1. See Note 1. 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. v v (c) Semiconductor Components Industries, LLC, 2000 1 March, 2000 - Rev. 3 Publication Order Number: MC14016B/D MC14016B PIN ASSIGNMENT IN 1 OUT 1 OUT 2 IN 2 CONTROL 2 CONTROL 3 VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD CONTROL 1 CONTROL 4 IN 4 OUT 4 OUT 3 IN 3 BLOCK DIAGRAM CONTROL 1 IN 1 CONTROL 2 IN 2 CONTROL 3 IN 3 CONTROL 4 IN 4 13 2 1 5 3 4 6 9 8 12 10 11 VDD = PIN 14 VSS = PIN 7 OUT 4 OUT 3 OUT 2 OUT 1 Control 0 = VSS 1 = VDD Switch Off On LOGIC DIAGRAM (1/4 OF DEVICE SHOWN) OUT CONTROL LOGIC DIAGRAM RESTRICTIONS VSS Vin VDD VSS Vout VDD IN http://onsemi.com 2 III II I I I II I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I IIII IIIIIIIII IIIIIIIIIIIIIIIII III II I I I II I I I I II I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I I I II I I I I II I I I II I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I II II II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I III II I I I II I I I I II I I I II I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I III II I I I II I I I I II I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II II II III II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I II I I I I I I II I I I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III II I I I II I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Input/Output Leakage Current (VC = VSS) (Vin = + 7.5, Vout = - 7.5 Vdc) (Vin = - 7.5, Vout = + 7.5 Vdc) "ON" Resistance Between any 2 circuits in a common package (VC = VDD) (Vin = 5.0 Vdc, VSS = - 5.0 Vdc) (Vin = 7.5 Vdc, VSS = - 7.5 Vdc) "ON" Resistance (VC = VDD, RL = 10 k) (Vin = + 5.0 Vdc) (Vin = - 5.0 Vdc) VSS = - 5.0 Vdc (Vin = 0.25 Vdc) Quiescent Current (Per Package) (5.) Input Capacitance Control Switch Input Switch Output Feed Through Input Current Control Input Voltage Control Input (Vin = + 15 Vdc) (Vin = + 0.25 Vdc) VSS = 0 Vdc (Vin = + 9.3 Vdc) (Vin = + 10 Vdc) (Vin = + 0.25 Vdc) VSS = 0 Vdc (Vin = + 5.6 Vdc) (Vin = + 7.5 Vdc) (Vin = - 7.5 Vdc) VSS = - 7.5 Vdc (Vin = 0.25 Vdc) Characteristic Figure 4,5,6 2,3 -- -- -- -- 1 Symbol RON RON VIH IDD Cin VIL -- Iin NOTE: All unused inputs must be returned to VDD or VSS as appropriate for the circuit application. 4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 5. For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e., the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14. http://onsemi.com MC14016B VDD Vdc 7.5 7.5 5.0 7.5 7.5 5.0 5.0 10 15 5.0 10 15 5.0 10 15 15 10 15 -- -- -- -- 3 Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 55_C 0.1 0.1 0.1 0.25 0.5 1.0 Max 360 360 360 600 600 600 360 360 360 600 600 600 -- -- -- -- -- -- -- -- -- -- -- -- MinIIII Typ (4.) Max 3.0 8.0 13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.00001 0.0015 0.0015 0.0005 0.0010 0.0015 25_C 260 260 300 260 310 310 240 240 180 300 300 280 5.0 5.0 5.0 0.2 2.0 6.0 11 1.5 1.5 1.5 15 10 0.1 0.1 0.1 0.25 0.5 1.0 400 400 400 660 660 660 400 400 400 660 660 660 0.9 0.9 0.9 -- -- -- -- -- -- -- -- -- Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 125_C 1.0 1.0 1.0 Max 520 520 520 840 840 840 520 520 520 840 840 840 7.5 15 30 -- -- -- -- -- -- -- -- -- -- -- -- Ohms Ohms Adc Adc Adc Unit Vdc Vdc pF IIII I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III II II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I I I I I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III II II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I I I I I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III II II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III II II III I II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIII I I I I I I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III II II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III II II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III IIII I I I I I I II II III II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III I II III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII 6. The formulas given are for typical characteristics only at 25_C. 7. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ELECTRICAL CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C) OFF Channel Feedthrough Attenuation (VSS = - 5.0 Vdc) Vout -50 dB) (VC = VSS, 20 log10 Vin (RL = 1.0 k) (RL = 10 k) (RL = 100 k) (RL = 1.0 M) Bandwidth (- 3.0 dB) (VC = VDD, Vin = 1.77 Vdc, VSS = - 5.0 Vdc, RMS centered @ 0.0 Vdc) (RL = 1.0 k) (RL = 10 k) (RL = 100 k) (RL = 1.0 M) Insertion Loss (VC = VDD, Vin = 1.77 Vdc, VSS = - 5.0 Vdc, RMS centered = 0.0 Vdc, f = 1.0 MHz) V Iloss 20 log10 out) Vin (RL = 1.0 k) (RL = 10 k) (RL = 100 k) (RL = 1.0 M) Second Harmonic Distortion (VSS = - 5.0 Vdc) (Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc, RL = 10 k, f = 1.0 kHz) Noise Voltage (VSS = 0 Vdc) (VC = VDD, f = 100 Hz) Crosstalk between any two switches (VSS = 0 Vdc) (RL = 1.0 k, f = 1.0 MHz, V crosstalk 20 log10 out1) Vout2 Crosstalk, Control to Output (VSS = 0 Vdc) (VC = VDD, Rin = 10 k, Rout = 10 k, f = 1.0 kHz) Control to Output (Vin 10 Vdc, RL = 10 k) Propagation Delay Time (VSS = 0 Vdc) Vin to Vout (VC = VDD, RL = 10 k) (VC = VDD, f = 100 kHz) v + + Characteristic + http://onsemi.com MC14016B Figure 12,13 10,11 12 -- -- -- 9 8 7 4 Symbol tPHZ, tPLZ, tPZH, tPZL tPLH, tPHL BW -- -- -- -- -- -- VDD Vdc 5.0 5.0 5.0 5.0 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 5.0 10 15 Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ (7.) 1250 140 18 2.0 2.3 0.2 0.1 0.05 0.16 - 80 30 50 100 15 7.0 6.0 54 40 38 37 12 12 15 24 25 30 34 20 15 Max 90 45 35 45 15 12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- nV/Cycle MHz Unit kHz mV dB dB ns ns % MC14016B VC Vin IS Vout VIL: VC is raised from VSS until VC = VIL. VIL: at VC = VIL: IS = 10 A with Vin = VSS, Vout = VDD or Vin = VDD, Vout = VSS. VIH: When VC = VIH to VDD, the switch is ON and the RON specifications are met. Figure 1. Input Voltage Test Circuit 10,000 VDD = 15 Vdc PD , POWER DISSIPATION (W) VDD TA = 25C 1000 10 Vdc 5.0 Vdc ID VDD Vout CONTROL INPUT VSS PD = VDD x ID Vin 10 k 100 PULSE GENERATOR TO ALL 4 CIRCUITS fc 10 1.0 5.0 k 10 k 100 k 1.0 M fc, FREQUENCY (Hz) 10 M 50 M Figure 2. Quiescent Power Dissipation Test Circuit Figure 3. Typical Power Dissipation per Circuit (1/4 of device shown) TYPICAL RON versus INPUT VOLTAGE 700 R ON, "ON" RESISTANCE (OHMS) R ON, "ON" RESISTANCE (OHMS) 600 500 400 300 200 100 0 - 10 - 8.0 VC = VDD = 7.5 Vdc VSS = - 7.5 Vdc VC = VDD = 5.0 Vdc VSS = - 5.0 Vdc RL = 10 k TA = 25C 700 600 500 400 300 200 100 0 - 4.0 0 4.0 Vin, INPUT VOLTAGE (Vdc) 8.0 10 0 2.0 6.0 10 14 Vin, INPUT VOLTAGE (Vdc) 18 20 VC = VDD = 15 Vdc VC = VDD = 10 Vdc VSS = 0 Vdc RL = 10 k TA = 25C Figure 4. VSS = - 5.0 V and - 7.5 V Figure 5. VSS = 0 V http://onsemi.com 5 MC14016B Vout RL Vin Vout RL VC Vin tPLH Vin Vout 20 ns 90% 50% tPHL 50% 20 ns VDD 10% VSS CL Figure 6. RON Characteristics Test Circuit Figure 7. Propagation Delay Test Circuit and Waveforms Vout VC Vin 20 ns VC tPZH Vout Vout 10% tPZL 90% 10% 50% 90% 10% tPHZ 90% VDD VSS Vin = VDD Vx = VSS VC Vout 10 k 15 pF RL VX CL Vin 1k tPLZ Vin = VSS Vx = VDD Figure 8. Turn-On Delay Time Test Circuit and Waveforms Figure 9. Crosstalk Test Circuit 35 30 NOISE VOLTAGE (nV/ CYCLE) 25 10 Vdc 20 15 10 5.0 0 10 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k 5.0 Vdc VDD = 15 Vdc OUT VC = VDD IN QUAN-TECH MODEL 2283 OR EQUIV Figure 10. Noise Voltage Test Circuit Figure 11. Typical Noise Characteristics http://onsemi.com 6 MC14016B 2.0 RL = 1 M AND 100 k TYPICAL INSERTION LOSS (dB) 0 10 k - 2.0 1.0 k - 4.0 - 6.0 - 8.0 - 10 - 12 10 k Vin 100 k 1.0 M 10 M fin, INPUT FREQUENCY (Hz) 100 M + 2.5 Vdc 0.0 Vdc - 2.5 Vdc - 3.0 dB (RL = 1.0 M ) - 3.0 dB (RL = 10 k ) - 3.0 dB (RL = 1.0 k ) VC Vout RL Figure 12. Typical Insertion Loss/Bandwidth Characteristics Figure 13. Frequency Response Test Circuit ON SWITCH CONTROL SECTION OF IC LOAD V SOURCE Figure 14. V Across Switch http://onsemi.com 7 MC14016B APPLICATIONS INFORMATION Figure A illustrates use of the Analog Switch. The 0-to-5 V Digital Control signal is used to directly control a 5 Vp-p analog signal. The digital control logic levels are determined by VDD and VSS. The VDD voltage is the logic high voltage; the VSS voltage is logic low. For the example, VDD = + 5 V logic high at the control inputs; VSS = GND = 0 V logic low. The maximum analog signal level is determined by VDD and VSS. The analog voltage must not swing higher than VDD or lower than VSS. The example shows a 5 Vp-p signal which allows no margin at either peak. If voltage transients above VDD and/or below VSS are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between VDD and VSS is 18.0 V. Most parameters are specified up to 15 V which is the recommended maximum difference between VDD and V SS. +5 V VDD +5 V 5 Vp-p ANALOG SIGNAL SWITCH IN VSS + 5.0 V SWITCH OUT 5 Vp-p ANALOG SIGNAL + 2.5 V EXTERNAL CMOS DIGITAL CIRCUITRY 0-TO-5 V DIGITAL CONTROL SIGNALS MC14016B GND Figure A. Application Example VDD Dx SWITCH IN Dx SWITCH OUT VDD Dx Dx VSS VSS Figure B. External Germanium or Schottky Clipping Diodes http://onsemi.com 8 MC14016B PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE M 14 8 B 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10_ 0.38 1.01 A F N -T- SEATING PLANE L C K H G D 14 PL 0.13 (0.005) M J M DIM A B C D F G H J K L M N http://onsemi.com 9 MC14016B PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F -A- 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -B- 1 7 P 7 PL 0.25 (0.010) M B M G C R X 45 _ F -T- SEATING PLANE D 14 PL 0.25 (0.010) M K TB S M A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 http://onsemi.com 10 MC14016B PACKAGE DIMENSIONS F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 965-01 ISSUE O 14 8 LE Q1 E HE M_ L DETAIL P 1 7 Z D e A VIEW P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056 c b 0.13 (0.005) M A1 0.10 (0.004) http://onsemi.com 11 MC14016B ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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