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| MM74C175 Quad D-Type Flip-Flop October 1987 Revised January 1999 MM74C175 Quad D-Type Flip-Flop General Description The MM74C175 consists of four positive-edge triggered Dtype flip-flops implemented with monolithic CMOS technology. Both are true and complemented outputs from each flip-flop are externally available. All four flip-flops are controlled by a common clock and a common clear. Information at the D-type inputs meeting the set-up time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. The clearing operation, enabled by a negative pulse at Clear input, clears all four Q outputs to logical "0" and Q's to logical "1". All inputs are protected from static discharge by diode clamps to VCC and GND. Features s Wide supply voltage range: s Guaranteed noise margin: s High noise immunity: 3V to 15V 1.0V 0.45 VCC (typ.) Fan out of 2 driving 74L s Low power TTL compatibility: Ordering Code: Order Number MM74C175M MM74C175N Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Truth Table Each Flip-Flop Inputs Clear L H H H H Clock X H L D X H L X X Outputs Q L H L NC NC Q H L H NC NC H = HIGH Level L = LOW Level X = Irrelevant = Transition from LOW-to-HIGH level NC = No Change Top View (c) 1999 Fairchild Semiconductor Corporation DS005900.prf www.fairchildsemi.com MM74C175 Block Diagrams Typical One of Four www.fairchildsemi.com 2 MM74C175 Absolute Maximum Ratings(Note 1) Voltage at Any Pin Operating Temperature Range Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range 700 mW 500 mW 3V to 15V -0.3V to VCC +0.3V -40C to +85C -65C to +150C Absolute Maximum VCC Lead Temperature (Soldering, 10 seconds) 18V 260C Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation. DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified Symbol CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC VIN(1) VIN(0) VOUT(1) VOUT(0) ISOURCE ISOURCE ISINK ISINK Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage Logical "1" Input Current Logical "0" Input Current Supply Current Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage Output Source Current (P-Channel) Output Source Current (P-Channel) Output Sink Current (N-Channel) Output Sink Current (N-Channel) VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V, IO = -10 A VCC = 10V, IO = -10 A VCC = 5V, IO = 10 A VCC = 10V, IO = 10 A VCC = 15V, VIN = 15V VCC = 15V, VIN = 0V VCC = 15V 74C, VCC = 4.75V 74C, VCC = 4.75V 74C, VCC = 4.75V, IO = -360 A 74C, VCC = 4.75V, IO = 360 A VCC = 5V, TA = 25C, VOUT = 0V VCC = 10V, TA = 25C, VOUT = 0V VCC = 5V, TA = 25C, VOUT = VCC VCC = 10V, TA = 25C, VOUT = VCC 8.0 16 mA 1.75 3.6 mA -8.0 -15 mA -1.75 -3.3 2.4 0.4 VCC - 1.5 0.8 -1.0 0.005 -0.005 0.05 300 4.5 9.0 0.5 1.0 1.0 3.5 8.0 1.5 2.0 V V V V V V V V A A A V V V V mA Parameter Conditions Min Typ Max Units CMOS/LPTTL INTERFACE OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current) 3 www.fairchildsemi.com MM74C175 AC Electrical Characteristics TA = 25C, CL = 50 pF, unless otherwise noted Symbol tpd Parameter Propagation Delay Time to a Logical "0" or Logical "1" from Clock to Q or Q tpd tpd tS tH tW tW tr tf fMAX CIN CPD Propagation Delay Time to a Logical "0" from Clear to Q Propagation Delay Time to a Logical "1" from Clear to Q Time Prior to Clock Pulse that Data Must be Present Time After Clock Pulse that Data Must be Held Minimum Clock Pulse Width Minimum Clear Pulse Width Maximum Clock Rise Time Maximum Clock Fall Time Maximum Clock Frequency Input Capacitance Power Dissipation Capacitance (Note 2) Conditions Min Typ 190 75 180 70 230 90 100 40 0 0 45 16 -11 -4 130 45 120 45 15 5.0 15 5.0 2.0 5.0 450 125 50 50 3.5 10 10 5.0 130 250 100 250 100 Max 300 110 300 110 400 150 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s MHz MHz pF pF pF VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5.0V VCC = 10V VCC = 5.0V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V Clear Input (Note 3) Any Other Input Per Package (Note 4) Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note AN-90. Switching Time Waveforms CMOS to CMOS www.fairchildsemi.com 4 MM74C175 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com MM74C175 Quad D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. |
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