View M48T12_135269.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M48T02 M48T12
16 Kbit (2Kb x8) TIMEKEEPER(R) SRAM
INTEGRATED ULTRA LOW POWER SRAM, REAL TIME CLOCK and POWER-FAIL CONTROL CIRCUIT BYTEWIDETM RAM-LIKE CLOCK ACCESS BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES and SECONDS TYPICAL CLOCK ACCURACY of 1 MINUTE a MONTH, AT 25C SOFTWARE CONTROLLED CLOCK CALIBRATION for HIGH ACCURACY APPLICATIONS AUTOMATICPOWER-FAILCHIP DESELECTand WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48T02: 4.5V VPFD 4.75V - M48T12: 4.2V VPFD 4.5V SELF-CONTAINED BATTERY and CRYSTAL in the CAPHAT DIP PACKAGE PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 2Kb x8 SRAMs DESCRIPTION The M48T02/12 TIMEKEEPER(R) RAM is a 2Kb x8 non-volatile static RAM and real time clock which is pin and functional compatible with the DS1642. A special 24 pin 600mil DIP CAPHATTM package houses the M48T02/12 silicon with a quartz crystal and a long life lithium button cell to form a highly integratedbatterybacked-upmemoryand real time clock solution. Table 1. Signal Names
G
A0-A10 DQ0-DQ7 E G W VCC VSS November 1998 Address Inputs Data Inputs / Outputs Chip Enable Output Enable Write Enable Supply Voltage Ground 1/15
24 1
PCDIP24 (PC) Battery/Crystal CAPHAT
Figure 1. Logic Diagram
VCC
11 A0-A10
8 DQ0-DQ7
W E
M48T02 M48T12
VSS
AI01027
M48T02, M48T12
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG TSLD (2) VIO VCC IO PD Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage Output Current Power Dissipation Value 0 to 70 -40 to 85 260 -0.3 to 7 -0.3 to 7 20 1 Unit C C C V V mA W
Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below -0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
Mode Deselect Write Read Read Deselect Deselect VSO to VPFD (min) VSO 4.75V to 5.5V or 4.5V to 5.5V VCC E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS Standby Battery Back-up Mode
Notes: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Figure 2. DIP Pin Connections
A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 24 2 23 3 22 4 21 5 20 6 M48T02 19 7 M48T12 18 8 17 9 16 10 15 11 14 12 13
AI01028
VCC A8 A9 W G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
DESCRIPTION (cont'd) The M48T02/12 button cell has sufficient capacity and storagelife to maintain data and clockfunctionality for an accumulated time period of at least 10 years in the absence of power over the operating temperature range. The M48T02/12 is a non-volatile pin and function equivalent to any JEDEC standard 2Kb x8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. As Figure 3 shows,the staticmemory array and the quartz controlled clock oscillator of the M48T02/12 are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE clock informationin the bytes with addresses7F8h7FFh. The clock locations contain the year, month, date,day, hour, minute, and secondin 24 hour BCD format. Corrections for 28, 29 (leap year), 30, and 31 day months are made automatically.
2/15
M48T02, M48T12
Figure 3. Block Diagram
OSCILLATOR AND CLOCK CHAIN 32,768 Hz CRYSTAL POWER
8 x 8 BiPORT SRAM ARRAY
A0-A10
LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY
2040 x 8 SRAM ARRAY VPFD
DQ0-DQ7
E W
BOK
G
VCC
VSS
AI01329
Byte 7F8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORTTM read/write memory cells. The M48T02/12 includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T02/12 also has its own Power-fail Detect circuit. The control circuitry constantlymonitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degreeof data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately3V, the control circuitry connectsthe battery which maintains data and clock operation until valid power returns.
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0V to 3V 1.5V
Note that Output Hi-Z is defined as the point where data is no longer driven.
Figure 4. AC Testing Load Circuit
5V
1.8k DEVICE UNDER TEST 1k
OUT
CL = 100pF
CL includes JIG capacitance
AI01019
3/15
M48T02, M48T12
Table 5. Capacitance (1) (TA = 25 C, f = 1 MHz )
Symbol C IN CIO
(2)
Parameter Input Capacitance Input / Output Capacitance
Test Condition VIN = 0V VOUT = 0V
Min
Max 10 10
Unit pF pF
Notes: 1. Effective capacitance measured with power supply at 5V. 2. Outputs deselected.
Table 6. DC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol ILI (1) ILO
(1)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Test Condition 0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC - 0.2V
Min
Max 1 5 80 3 3
Unit A A mA mA mA V V V V
ICC ICC1 (2) ICC2
(2)
V IL(3) VIH V OL VOH
-0.3 2.2 IOL = 2.1mA IOH = -1mA 2.4
0.8 VCC + 0.3 0.4
Notes: 1. Outputs Deselected. 2. Measured with Control Bits set as follows: R = '1'; W, ST, KS, FT = '0'.
Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70C)
Symbol VPFD VPFD VSO
(2) tDR
Parameter Power-fail Deselect Voltage (M48T02) Power-fail Deselect Voltage (M48T12) Battery Back-up Switchover Voltage Expected Data Retention Time
Min 4.5 4.2
Typ 4.6 4.3 3.0
Max 4.75 4.5
Unit V V V YEARS
10
Notes: 1. All voltages referenced to VSS. 2. At 25C.
4/15
M48T02, M48T12
Table 8. Power Down/Up Mode AC Characteristics (TA = 0 to 70C)
Symbol tPD tF
(1) (2)
Parameter E or W at VIH before Power Down VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSO VCC Fall Time VPFD(min) to VPFD (max) VCC Rise Time VSO to VPFD (min) VCC Rise Time E or W at VIH after Power Up
Min 0 300 10 0 1
Max
Unit s s s s s
tFB
tR tRB tREC
2
ms
Notes: 1. VPFD (max) to VPFD (min) fall time of less than t F may result in deselection/write protection not occurring until 50 s after VCC passes VPFD (min). 2. VPFD (min) to VSO fall time of less than t FB may cause corruption of RAM data.
Figure 5. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tPD INPUTS
RECOGNIZED
tDR tFB tRB DON'T CARE
tR tREC
NOTE RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI00606
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E high as VCC rises past VPFD(min). Some systems may perform inadvertent write cycles after VCC rises above VPFD(min) but before normal system operations begin. Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
5/15
M48T02, M48T12
Table 9. Read Mode AC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48T02 / M48T12 Symbol Parameter Min tAVAV tAVQV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tAXQX Read Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition 10 5 5 25 25 5 70 70 70 35 10 5 35 35 5 -70 Max Min 150 150 150 75 10 5 40 40 -150 Max Min 200 200 200 80 -200 Max ns ns ns ns ns ns ns ns ns Unit
Figure 6. Read Mode AC Waveforms
tAVAV A0-A10 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI01330
VALID tAXQX tEHQZ
tGHQZ
Note: Write Enable (W) = High.
6/15
M48T02, M48T12
Table 10. Write Mode AC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48T02 / M48T12 Symbol Parameter Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ tAVWH tAVEH tWHQX Write Cycle Time Address Valid to Write Enable Low Address Valid to Chip Enable Low Write Enable Pulse Width Chip Enable Low to Chip Enable High Write Enable High to Address Transition Chip Enable High to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable Low to Output Hi-Z Address Valid to Write Enable High Address Valid to Chip Enable High Write Enable High to Output Transition 60 60 5 70 0 0 50 55 0 0 30 30 5 5 25 120 120 10 -70 Max Min 150 0 0 90 90 10 10 40 40 5 5 50 140 140 10 -150 Max Min 200 0 0 120 120 10 10 60 60 5 5 60 -200 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
READ MODE The M48T02/12 is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 16,384 locations in the static storage array. Thus, the unique address specified by the 11 Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (t GLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before t AVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active,
output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access. WRITE MODE The M48T02/12 is in the Write Mode whenever W and E are active. The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from Write Enableprior to the initiation of anotherread or write cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for tWHDX afterward. G shouldbe kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.
7/15
M48T02, M48T12
Figure 7. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A10 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI01331
tWHAX
tWHQX
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A10 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01332B
tELEH
tEHAX
8/15
M48T02, M48T12
DATA RETENTION MODE With valid VCC applied,the M48T02/12operates as a conventionalBYTEWIDE static RAM. Should the supply voltage decay, the RAM will automatically power-faildeselect,write protectingitself when VCC falls within the VPFD(max), VPFD(min) window. All outputsbecome high impedance,and all inputs are treated as "don't care." Note: A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content.At voltagesbelow VPFD(min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T02/12 may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. The power switching circuit connects external VCC to the RAM and disconnects the battery when VCC rises above VSO. As VCC rises, the battery voltage is checked. If the voltage is too low, an internal BatteryNot OK (BOK) flag will be set.The BOKflag can be checked after power up. If the BOK flag is set, the first write attempted will be blocked. The flagis automatically clearedafter the firstwrite, and normal RAM operation resumes. Figure 9 illustrates how a BOK check routine could be structured. For more information on a Battery Storage Life refer to the Application Note AN1012. CLOCK OPERATIONS Reading the Clock Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. Because the BiPORT TIMEKEEPER cells in the RAM array are only data registers, and not the actual clock counters, updating the registers can be halted without disturbing the clock itself. Updatingis halted when a '1' is written to the READ bit, the seventh bit in the control register. As long as a '1' remains in that position, updating is halted. After a halt is issued, the registersreflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress.Updating is withina secondafter the read bit is reset to a '0'. Figure 9. Checking the BOK Flag Status
POWER-UP
READ DATA AT ANY ADDRESS
WRITE DATA COMPLEMENT BACK TO SAME ADDRESS
READ DATA AT SAME ADDRESS AGAIN
IS DATA COMPLEMENT OFFIRST READ? (BATTERY OK) YES
NO (BATTERY LOW)
NOTIFY SYSTEM OF LOW BATTERY (DATA MAY BE CORRUPTED)
WRITE ORIGINAL DATA BACK TO SAME ADDRESS
CONTINUE
AI00607
Setting the Clock The eighth bit of the control register is the WRITE bit. Setting the WRITE bit to a '1', like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 10). Resetting the WRITE bit to a '0' then transfers the values of all time registers (7F9h-7FFh) to the actual TIMEKEEPER counters and allows normal operationto resume.The FT bit and thebits marked as '0' in Table 10 must be written to '0' to allow for normal TIMEKEEPER and RAM operation. See the Application Note AN923 "TIMEKEEPER rolling into the 21st century" for more information on Century Rollover.
9/15
M48T02, M48T12
Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T02/12is shipped from STMicroelectronics with the STOP bit set to a '1'. When reset to a '0', the M48T02/12 oscillator starts within 1 second. Calibrating the Clock The M48T02/12 is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. A typical M48T02/12 is accurate within 1 minuteper month at 25C without calibration. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. The oscillation rate of any crystal changes with temperature (see Figure 10).Most clockchips compensatefor crystal frequencyand temperatureshift error with cumbersome trim capacitors. The M48T02/12 design, however, employs periodic counter correction.The calibration circuit adds or subtractscounts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 11. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five bit Calibration byte found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration byte occupies the five lower order bits in the Control register. This byte can be set to represent any value between 0 and 31 in binary form. The sixth bit is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurswithin a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened or lengthened by 128 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of addingor subtracting256 oscillator cycles for every 125,829,120actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T02/12 may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the Calibration byte.
Table 11. Register Map
Address D7 7FFh 7FEh 7FDh 7FCh 7FBh 7FAh 7F9h 7F8h 0 0 0 0 0 ST W R D6 D5 D4 Data D3 D2 Year 10 M. 10 Date 0 0 0 Month Date Day Hours Minutes Seconds Calibration D1 D0 Function/Range BCD Format Year Month Date Day Hour Minutes Seconds Control 00-99 01-12 01-31 01-07 00-23 00-59 00-59
10 Years 0 0 FT 0 0
10 Hours 10 Minutes 10 Seconds S
Keys: S = SIGN Bit FT = FREQUENCY TEST Bit (Set to '0' for normal clock operation) R = READ Bit W = WRITE Bit ST = STOP Bit 0 = Must be set to '0'
10/15
M48T02, M48T12
Figure 10. Crystal Accuracy Across Temperature
ppm 20
0
-20
-40 F = -0.038 ppm (T - T )2 10% 0 F C2 T0 = 25 C -80
-60
-100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 C
AI02124
Figure 11. Clock Calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
11/15
M48T02, M48T12
CLOCK OPERATION (cont'd) The second approach is better suited to a manufacturing environment, and involves the use of some test equipment. When the Frequency Test (FT) bit, the seventh-most significant bit in the Day Register, is set to a '1', and the oscillator is running at 32,768 Hz, the LSB (DQ0) of the Seconds Register will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a -10(WR001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency. The device must be selected and address 7F9h must be held constant when reading the 512 Hz on DQ0. TheFT bit must be set using the same methodused to set the clock, using the Write bit. The LSB of the Seconds Register is monitored by holding the M48T02/12 in an extended read of the Seconds Register, without having the Read bit set. The FT bit MUST be reset to '0' for normal clock operations to resume. For more information on calibration, see the Application Note AN924 "TIMEKEEPER Calibration". POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the VCC bus. The energy stored in the bypass capacitors will be releasedas low going spikes are generated or energy will be absorbed when overshoots occur. A bypass capacitor value of 0.1F (as shown in Figure 12) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one Volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommeded to connecta schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 12. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
12/15
M48T02, M48T12
ORDERING INFORMATION SCHEME
Example:
M48T02
-70
PC
1
Supply Voltage and Write Protect Voltage 02 12 VCC = 4.75V to 5.5V VPFD = 4.5V to 4.75V VCC = 4.5V to 5.5V VPFD = 4.2V to 4.5V -70 -150 -200
Speed 70ns 150ns 200ns PC
Package PCDIP24
Temp. Range 1 0 to 70 C
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
13/15
M48T02, M48T12
PCDIP24 - 24 pin Plastic DIP, battery CAPHAT
Symb Typ A A1 A2 B B1 C D E e1 e3 eA L N mm Min 8.89 0.38 8.38 0.38 1.14 0.20 34.29 17.83 2.29 25.15 15.24 3.05 24 Max 9.65 0.76 8.89 0.53 1.78 0.31 34.80 18.34 2.79 30.73 16.00 3.81 Typ inches Min 0.350 0.015 0.330 0.015 0.045 0.008 1.350 0.702 0.090 0.990 0.600 0.120 24 Max 0.380 0.030 0.350 0.021 0.070 0.012 1.370 0.722 0.110 1.210 0.630 0.150
A2
A
A1 B1 B e3 D
N
L eA
C
e1
E
1 PCDIP
Drawing is not to scale.
14/15
M48T02, M48T12
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Spec ifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1998 STMicroelectronics - All Rights Reserved (R) TIMEKEEPER is a registered trademark of STMicroelectronics TM CAPHAT, BYTEWIDE and BiPORT are trademarks of STMicroelectronics STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
15/15

▲Up To Search▲

Price & Availability of M48T12

	To Download M48T12 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .