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Ordering number : EN*5557
CMOS LSI
LC74794, 74794M
On-Screen Display Controller LSI
Preliminary Overview
The LC74794 and LC74794M are CMOS LSIs for onscreen display, a function that displays characters and patterns on a TV screen under microprocessor control. They feature a built-in PDC/VPS/UDT interface circuit. These LSIs support 12 x 18 dot characters and can display 12 lines by 24 characters of text.
Package Dimensions
unit: mm 3196-DIP30SD
[LC74794]
Features
* Display format: 24 characters by 12 rows (Up to 288 characters) * Character format: 12 (horizontal) x 18 (vertical) dots * Character sizes: Three sizes each in the horizontal and vertical directions * Characters in font: 128 * Initial display positions: 64 horizontal positions and 64 vertical positions * Blinking: Specifiable in character units * Blinking types: Two periods supported: 1.0 second and 0.5 second * Blanking: Over the whole font (12 x 18 dots) * Background color -- Background coloring: 8 colors (internal synchronization mode): 4fsc -- Background coloring: 6 colors (internal synchronization mode): 2fsc -- Blue background only: NTSC * Line background color -- Can be set for 3 lines -- Line background coloring: 8 colors (internal synchronization mode): 4fsc -- Line background coloring: 6 colors (internal synchronization mode): 2fsc * External control input: 8-bit serial input format * On-chip sync separator and AFC circuits * PDC/VPS/UDT interface circuit * Composite video output in the PAL or NTSC format
SANYO: DIP30SD
unit: mm 3216A-MFP30S
[LC74794M]
SANYO: MFP30S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
22897HA (OT)/No. 5557-1/30
LC74794, 74794M Pin Assignment
Pin Functions
Pin no. 1 2 Pin VSS1 XtalIN XtalOUT (MUTE) Crystal oscillator (MUTE input) Ground Function Ground connection (digital system ground) These pins are used either to connect a crystal and capacitor to form an external crystal oscillator to generate internal synchronizing signals, or to input an external clock signal (2fsc or 4fsc). As a mask option, the XtalOUT pin can be set to function as the MUTE input pin. When the MUTE pin is set low, the video output is held at the pedestal level. (A pull-up resistor is built in so the input has hysteresis characteristics.) Switches the mode between external clock input and crystal oscillator operation. A low level selects crystal oscillator operation and a high level selects external clock input. As a mask option, the CTRL1 input pin can be set to function as the CHABLK (character * border) output. This is a 3-value output. PDC/VPS data output enable input. Data output is enabled by a low-level input. (A pull-up resistor is built in so the input has hysteresis characteristics.) Clock input for PDC/VPS data output (A pull-up resistor is built in so the input has hysteresis characteristics.) PDC/VPS data output (This is either an n-channel open-drain output or a CMOS output.) Outputs the state of the external synchronizing signal presence/absence judgment. Outputs a high level when synchronizing signals are present. Outputs the crystal oscillator clock when CS1 is low and RST is low. (This signal is not output on command resets.) Notes
3
4
CTRL1 Crystal oscillator input switching (CHABLK) (CHABLK output)
5 6 7
CS2 SCLK2 DOUT
Enable input 2 Clock input 2 Data output
8
External synchronizing signal judgment SYNCJDG output
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LC74794, 74794M
Continued from preceding page.
Pin no. 9 Pin CS1 Enable input 1 Function Notes Enable input for OSD serial data input Serial data input is enabled by a low-level input. (A pull-up resistor is built in so the input has hysteresis characteristics.) Serial data clock input (A pull-up resistor is built in so the input has hysteresis characteristics.) Serial data input (A pull-up resistor is built in so the input has hysteresis characteristics.) Composite video signal level adjustment power supply (analog system power supply) The charge pump output. Connect a low-pass filter to this pin. VCO control voltage input Ground (VCO ground) Power supply (+5 V: VCO power supply) Connection for the VCO range adjustment resistor Outputs a low level when PDC/VPS data has been received. Composite video signal output Ground (analog system ground) Composite video signal input SECAM chrominance signal input Power supply (+5 V: digital system power supply) Internal sync separator circuit video signal input Internal sync separator circuit adjustment input Composite synchronizing signal output for the built-in sync separator circuit. Can be switched to function as an output for the signal (high or ST. pulse) due to MOD0 by setting SEL0 high. Inputs the vertical synchronizing signal created by integrating the SEPOUT pin output signal. An integration circuit must be connected to the SEPOUT pin. This pin must be tied to VDD1 if unused. Background color phase adjustment resistor connection System reset input A pull-up resistor is built in so the input has hysteresis characteristics. Power supply (+5 V: digital system power supply)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
SCLK1 SIN1 VDD2 CPOUT VCOIN VSS3 VDD3 VCOR DAV CVOUT VSS2 CVIN CVCR VDD1 SYNIN SEPC SEPOUT
Clock input 1 Data input 1 Power supply Charge pump output Oscillator control voltage input Ground Power supply (+5 V) Oscillator range adjustment Data present output Video signal output Ground Video signal input Video signal input Power supply (+5 V) Sync separator circuit input Sync separator circuit adjustment Composite synchronizing signal output
27
SEPIN CDLR RST VDD1
Vertical synchronizing signal input
28 29 30
Background color phase adjustment Reset input Power supply (+5 V)
No. 5557-3/30
LC74794, 74794M
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD VIN VOUT Pd max Topr Tstg VDD1 and VDD2 All input pins DAV, DOUT, SEPOUT, and SYNCJDG Conditions Ratings VSS - 0.3 to VSS + 7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 350 -30 to +70 -40 to +125 Unit V V V mW C C
Allowable Operating Ranges at Ta = -30 to +70C
Parameter Symbol VDD1 VDD2 VIH1 VIH2 Input low-level voltage VIL1 VIL2 Pull-up resistance Composite video signal input voltage Input voltage Oscillator frequency RPU VIN1 VIN2 VIN3 FOSC1 FOSC2 VDD1 and VDD2 VDD2 RST, CS1, CS2, SIN1, SCLK1, SCLK2, and MUTE CTRL1 RST, CS1, CS2, SIN1, SCLK1, SCLK2, and MUTE CTRL1 RST, CS1, CS2, SIN1, SCLK1, SCLK2, and MUTE CVIN and CVCR; VDD1 = 5 V SYNIN; VDD1 = 5 V XtalIN (in external clock input mode) fin = 2 fsc or 4 fsc ; VDD1 = 5 V XtalIN and XtalOUT oscillator pins (2 fsc: PAL) XtalIN and XtalOUT oscillator pins (4 fsc: PAL) 1.5 0.10 8.867 17.734 Conditions Ratings min 4.5 5.5 0.8 VDD1 0.7 VDD1 VSS - 0.3 VSS - 0.3 25 50 2.0 2.0 2.5 5.0 typ 5.0 5.0 max 5.5 1.27 VDD1 VDD1 + 0.3 VDD1 + 0.3 0.2 VDD1 0.3 VDD1 90 Unit V V V V V V k Vp-p Vp-p Vp-p MHz MHz
Supply voltage
Input high-level voltage
Note: When the XtalIN pin is used in clock input mode, extreme care must be taken to prevent noise from entering the input signal.
Electrical Characteristics at Ta = -30 to +70C, VDD1 = 5 V unless otherwise specified.
Parameter Input off leakage current Output off leakage current Output high-level voltage Output low-level voltage Symbol Ileak1 Ileak2 VOH1 VOL1 CVIN and CVCR CVOUT DAV, DOUT, SEPOUT, CPOUT, SYNCJDG ; VDD1 = 4.5 V, IOH = -1.0 mA DAV, DOUT, SEPOUT, CPOUT, SYNCJDG ; VDD1 = 4.5 V, IOL = 1.0 mA CHABLK ; VDD1 = 5.0 V Three-value output voltage VO H M L IIH IIL Operating current drain IDD1 IDD2 SYNC level VSN RST, CS1, CS2, SIN, SCLK1, SCLK2, CTRL1, MUTE, SEPIN, and VCOIN VIN = VDD1 CTRL1, SEPIN, and VCOIN ; VIN = VSS1 VDD1; with all outputs open Xtal : 17.734 MHz, VCO : 27 MHz VDD2; VDD2 = 5 V CVOUT; VDD1 = 5.0 V VDD2 = 5.0 V CVOUT; VDD1 = 5.0 V VDD2 = 5.0 V CVOUT; VDD1 = 5.0 V VDD2 = 5.0 V -1 40 20 3.3 1.8 0 3.5 1.0 5.0 2.3 0.8 1 Conditions Ratings min typ max 1 1 Unit A A V V V V V A A mA mA V V V V V V V V V
Input current
Pedestal level
VPD
Color burst low level
VCBL

0.80 1.00 1.30 1.37 1.57 1.87 1.07 1.27 1.57
Continued on next page. No. 5557-4/30
LC74794, 74794M
Continued from preceding page.
Parameter Symbol Conditions CVOUT; VDD1 = 5.0 V VDD2 = 5.0 V CVOUT; VDD1 = 5.0 V VDD2 = 5.0 V CVOUT; VDD1 = 5.0 V VDD2 = 5.0 V CVOUT; VDD1 = 5.0 V VDD2 = 5.0 V CVOUT; VDD1 = 5.0 V VDD2 = 5.0 V CVOUT; VDD1 = 5.0 V VDD2 = 5.0 V Ratings min typ 1.67 1.87 2.17 1.23 (1.16) 1.43 (1.36) 1.73 (1.66) 2.37 (2.01) 2.57 (2.21) 2.87 (2.51) 1.50 1.70 2.00 2.08 2.28 2.58 2.65 2.85 3.15 max Unit V V V V V V V V V V V V V V V V V V
Color burst high level
VCBH
Background color low level
VRSL
Background color high level
VRSH
Frame level 0
VBK0
Frame level 1
VBK1
Character level
VCHA

Notes: When the sync level is 0.8 V. When the sync level is 1.0 V. When the sync level is 1.3 V. The values in parentheses for the background color high and low levels are the values for a blue background.
Timing Characteristics at Ta = -30 to +70C, VDD1 = 5 0.5 V OSD write (See Figure 1.)
Parameter Symbol tW(SCLK) tW(CS1) tSU(CS1) tSU(SIN) th(CS1) th(SIN) tword twt SCLK1 CS1 (The period when CS1 is high) CS1 SIN1 CS1 SIN1 The time to write 8 bits of data The RAM data write time Conditions Ratings min 200 1 200 200 2 200 4.2 1 typ max Unit ns s ns ns s ns s s
Minimum input pulse width
Data setup time
Data hold time
One word write time
PDC/VPS reads (For the n-channel open-drain output circuit. See Figure 2.)
Parameter Symbol tCKCY Minimum input pulse width tCKL tCKH Setup time Output delay time tICK tCKO SCLK2 SCLK2 SCLK2 SCLK2 DOUT Conditions Ratings min 2 1 1 10 0.5 typ max Unit s s s s s
Note: Timings follow those for OSD write when the CMOS output circuit is used.
No. 5557-5/30
LC74794, 74794M
Figure 1 OSD Serial Data Input Timing
Note: DOUT goes to the high-impedance state while CS2 is high.
Figure 2 PDC/VPS Serial Output Test Conditions (For the n-channel open-drain output)
No. 5557-6/30
LC74794, 74794M System Block Diagram
No. 5557-7/30
LC74794, 74794M Display Control Commands Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of a command identification code in the first byte and command data in the following bytes. The following commands are supported. 1 COMMAND0: Display memory (VRAM) write address setup command 2 COMMAND1: Display character data write command 3 COMMAND2: Vertical display start position and vertical character size setup command 4 COMMAND3: Horizontal display start position and horizontal character size setup command 5 COMMAND4: Display control setup command 6 COMMAND5: Display control setup command 7 COMMAND6: Synchronizing signal detection setup command 8 COMMAND7 to COMMAND12: Display control setup commands 9 COMMAND13 to COMMAND17: VPS/PDC commands Display Control Command Table
First byte Command Command identification code 7 COMMAND0 Write address setup COMMAND1 Character write COMMAND2 Vertical character size and vertical display start position COMMAND3 Horizontal character size and horizontal display start position COMMAND4 Display control COMMAND5 Display control COMMAND6 Synchronizing signal detection COMMAND7 Display control COMMAND8 Display control COMMAND9 Display control COMMAND10 Display control COMMAND11 Display control COMMAND12 Display control COMMAND13 VPS/PDC control COMMAND14 VPS/PDC control COMMAND15 VPS/PDC control COMMAND16 VPS/PDC control COMMAND17 VPS/PDC control 1 1 1 6 0 0 0 5 0 0 1 4 0 1 0 3 V3 0 VS 21 HS 21 2 V2 0 VS 20 HS 20 Data 1 V1 0 VS 11 HS 11 OSC STP NON DIS LIN 0 0 1 1 0 0 1 1 0 0 1 0 V0 0 VS 10 HS 10 SYS RST INT MUT 0 1 0 1 0 1 0 1 0 1 0 7 0 at 0 6 0 c6 FS 5 0 c5 VP 5 HP 5 BLK 2 0 RN 2 CIN SEL LNA 3 LNB 3 LNC 3 0 0 CPA 1 0 0 ECP 19 0 BLK 1 HLF INT RN 1 CIN CTL LNA 2 LNB 2 LNC 2 0 0 CPA 0 0 ECV 15 ECP 18 ECP 25 Second byte Data 4 H4 c4 VP 4 HP 4 BLK 0 BCL RN 0 VNP SEL LNA 1 LNB 1 LNC 1 0 0 0 HBS 2 ECV 14 ECP 17 ECP 24 3 H3 c3 VP 3 HP 3 BK 1 CB SN 3 VSP SEL LNA 0 LNB 0 LNC 0 LNC SEL 0 VPM 3 HBS 1 ECV 13 ECP 16 ECP 23 2 H2 c2 VP 2 HP 2 BK 0 PH 2 SN 2 MSK ERS LPA 2 LPB 2 LPC 2 MOD 3 SEL 2 VPM 2 BMS ECV 12 ECP 15 ECP 22 1 H1 c1 VP 1 HP 1 RV PH 1 SN 1 MSK SEL LPA 1 LPB 1 LPC 1 LNB SEL SEL 1 VPM 1 EMS ECV 11 ECP 14 ECP 21 0 H0 c0 VP 0 HP 0 DSP ON PH 0 SN 0 EGL LPA 0 LPB 0 LPC 0 MOD 2 CTL 3 VPM 0 DCE ECV 5 ECP 13 ECP 20
1
0
1
1
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1 1 1 1 1 1
0 1 0 1 1 1 1 1 1 1 1 1 1 1
TST RAM MOD ERS NP1 SEL 0 0 0 0 0 0 0 0 0 1 1 1 NP0 MOD 0 0 0 0 0 1 1 1 1 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
Once written, the command identification code in the first byte is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74794/M locks into the display character data write mode, and another first byte cannot be written. When the CS1 pin is set high, the LC74794/M is set to the COMMAND0 (display memory write address setup mode) state.
No. 5557-8/30
LC74794, 74794M COMMAND0 (Display memory write address setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- V3 V2 V1 V0 Contents State 1 0 0 0 0 1 0 1 0 1 0 1 Display memory line address (0 to B hexadecimal) Command 0 identification code Sets the display memory write address. Function Notes
Second byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- H4 H3 H2 H1 H0 Contents State 0 0 0 0 1 0 1 0 1 0 1 0 1 Display memory column address (0 to 17 hexadecimal) Second byte identification code Function Notes
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
COMMAND1 (Display character data write setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 0 0 1 0 0 0 0 Command 1 identification code Sets up display character data write mode. When this command is input, the LC74794/M locks in the display character data write mode until the CS1 pin goes high. Function Notes
No. 5557-9/30
LC74794, 74794M Second byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register at c6 c5 c4 c3 c2 c1 c0 Contents State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Character code (00 to 7F hexadecimal) Character attribute off Character attribute on Function Notes
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
COMMAND2 (Vertical display start position and vertical character size setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- VS21 VS20 VS11 VS10 Contents State 1 0 1 0 0 1 0 1 0 1 0 1
VS11 VS21 VS20
Function Command 2 identification code Sets the vertical display start position and the vertical character size
Notes
0 1H/dot 3H/dot
1 2H/dot 1H/dot 1 2H/dot 1H/dot First line vertical character size Second line vertical character size
0 1
VS10
0 1H/dot 3H/dot
0 1
Second byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- FS VP5 (MSB) VP4 VP3 VP2 VP1 VP0 (LSB) Contents State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Second byte identification bit Crystal oscillator frequency: 2fsc Crystal oscillator frequency: 4fsc If VS is the vertical display start position then: VS = H x (2 2n VPn)
n=0 5
Function
Notes
H: the horizontal synchronization pulse period The vertical display start position is set by the 6 bits VP0 to VP5. The weight of bit 1 is 2H.
No. 5557-10/30
LC74794, 74794M COMMAND3 (Horizontal display start position and horizontal size setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- HS21 HS20 HS11 HS10 Contents State 1 0 1 1 0 1 0 1 0 1 0 1
HS11 HS21 HS20
Function Command 3 identification code Sets the horizontal display start position and the horizontal character size.
Notes
0 1Tc/dot 3Tc/dot
1 2Tc/dot 1Tc/dot 1 2Tc/dot 1Tc/dot First line horizontal character size Second line horizontal character size
0 1
HS10
0 1Tc/dot 3Tc/dot
0 1
Second byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- HP5 (MSB) HP4 HP3 HP2 HP1 HP0 (LSB) Contents State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 If HS is the horizontal start position then: HS = Tc x (2 2n HPn)
n=0 5
Function Second byte identification bit
Notes
Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating mode.
The horizontal display start position is set by the 6 bits HP0 to HP5. The weight of bit 1 is 2Tc.
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-11/30
LC74794, 74794M COMMAND4 (Display control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- TSTMOD RAMERS OSCSTP SYSRST Contents State 1 1 0 0 0 1 0 1 0 1 0 1 Reset all registers and turn display off. Erase display RAM. (Set the RAM data to 7F hexadecimal.) Do not stop the crystal and LC oscillators. Stop the crystal and LC oscillators. Normal operating mode Test mode This bit must be set to 0. Erasing RAM takes about 500 s. (This operation must be executed in the DSPOFF state.) Valid in external synchronization mode when character display is off. The registers are reset when the CS1 pin is low, and the reset state is cleared when CS1 is set high. Command 4 identification code Display control setup Function Notes
Second byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- BLK2 BLK1 BLK0 BK1 BK0 RV DSPON Contents State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1
BLK1
Function Second byte identification bit Character display area Video display area
BLK0
Notes
Specifies the size for complete fill-in 0 Blanking off Border size 1 Character size Complete fill in Switches the blinking period Blinking in reverse video mode switches the display between normal character display and reverse video display. Changes the blanking size
0 1 Blinking period: About 0.5 s Blinking period: About 1.0 s Blinking off Blinking on Reverse video off Reverse video on Character display off Character display on
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-12/30
LC74794, 74794M COMMAND5 (Display control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- NP1 NP0 NON INT Contents State 1 1 0 1 0 1 0 1 1 0 0 1 Interlaced Noninterlaced External synchronization Internal synchronization
NPP1 NP0
Function Command 5 identification code Display control setup
Notes
0 NTSC (525) PAL (525)
1 NTSC (625) PAL (625) Switches between NTSC and PAL. ( ) external input V Switches between interlaced and noninterlaced video. Switches between external and internal synchronization
0 1
Second byte
DA 0 to 7 7 6 5 4 3 Register -- -- HLFINT BCL CB Contents State 0 0 0 1 0 1 0 1 0 2 PH2 1 0 1 PH1 1 0 0 PH0 1 Normal mode No background coloring (Only the background level is set) Background coloring on No background coloring (Only the background level is set) Color burst signal output Color burst signal output stopped PH2 0 0 0 0 1 1 1 1 PH1 0 0 1 1 0 0 1 1 PH0 0 1 0 1 0 1 0 1 Background color (phase) Cyan Yellow Red Blue Cyan - blue Green Orange Magenta * *: When 2 fsc is used. * * * * * Background color specification Only valid when BCL is high. Only valid in internal synchronization mode. Second byte identification bit Function Notes
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-13/30
LC74794, 74794M COMMAND6 (Synchronizing signal detection setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- SEL0 MOD0 DISLIN MUT Contents State 1 1 1 0 0 1 0 1 0 1 0 1 Sync separator signal Output signal set by MOD0 High-level output ST pulse signal 12 lines 10 lines Normal output CVIN is cut and CVOUT is held at the pedestal level. CVOUT switching Switches the number of lines displayed. Only valid when SEL0 is high. Switches the SEPOUT (pin 19) output. Command 6 identification code Sets up synchronizing signal control. Function Notes
Second byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- RN2 RN1 RN0 SN3 SN2 SN1 SN0 Contents State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SN3 0 0 0 0 1 SN2 0 0 0 1 0 SN1 0 0 1 0 0 SN0 0 1 0 0 0 Number of times HSYNC detected Not detected 32 times 64 times 128 times 256 times External synchronizing signal detection control Signal present signal absent transition detection Sets the sampling period in which SYNC cannot be detected continuously in the horizontal synchronizing signal period (1H). Second byte identification bit RN2 0 0 0 1 RN1 0 0 1 0 RN0 0 1 0 0 Number of times HSYNC detected 0 times 4 times 8 times 16 times External synchronizing signal detection control Signal absent signal present transition detection Sets the sampling period in which SYNC can be detected continuously in the horizontal synchronizing signal period (1H). Function Notes
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-14/30
LC74794, 74794M COMMAND7 (Display control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 0 0 0 0 Extended command 0 identification code Command 7 identification code Display control setup Function Notes
Second byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- CINSEL CINCTL VNPSEL VSPSEL MSKERS MSKSEL EGL Contents State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Second byte identification bit Blank area (the logical OR of the character and frame signals) Video signal display area CVCR: off CVCR:: on V falling edge detection V rising edge detection VSEP: about 8.9 s (NTSC) VSEP: about 17.8 s (NTSC) Mask valid Mask invalid 3H (NTSC) 20H (NTSC) Border level 0 only (VBK0) Two-stage border level (VBK0 and VBK1) Switches the VSYNC mask. Switches the border level. (Only valid when BLK0 is 0 and BLK1 is 1.) Clears the HSYNC and VSYNK masks. Switches the internal V separation period. CVCR on signal switching Turns CVCR on or off. Switches the V acquisition polarity in external mode when internal V separation is used. Function Notes
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-15/30
LC74794, 74794M COMMAND8 (Display control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 0 0 0 1 Extended command 1 identification code Command 7 identification code Display control setup Function Notes
Second byte
DA 0 to 7 7 Register -- Contents State 0 0 6 LNA3 1 0 5 LNA2 1 0 4 LNA1 1 0 3 LNA0 1 0 2 LPA2 1 0 1 LPA1 1 0 0 LPA0 1 LPA2 0 0 0 0 1 1 1 1 LPA1 0 0 1 1 0 0 1 1 LPA0 0 1 0 1 0 1 0 1 Background color (phase) Cyan Yellow Red Blue Cyan - blue Green Orange Magenta * *: When 2 fsc is used. * * * * * Specifies the background color. Second byte identification bit LNA3 LNA2 LNA1 LNA0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 -- 0 1 0 1 0 1 0 1 0 1 0 1 -- Specified line Do not change the line background Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Specifies the line whose background is to be changed (Specifying the same line with LNA*, LNB*, and LNC* is not allowed.) Function Notes
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-16/30
LC74794, 74794M COMMAND9 (Display control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 0 0 1 0 Extended command 2 identification code Command 7 identification code Display control setup Function Notes
Second byte
DA 0 to 7 7 Register -- Contents State 0 0 6 LNB3 1 0 5 LNB2 1 0 4 LNB1 1 0 3 LNB0 1 0 2 LPB2 1 0 1 LPB1 1 0 0 LPB0 1 LPB2 0 0 0 0 1 1 1 1 LPB1 0 0 1 1 0 0 1 1 LPB0 0 1 0 1 0 1 0 1 Background color (phase) Cyan Yellow Red Blue Cyan - blue Green Orange Magenta * *: When 2 fsc is used. * * * * * Specifies the background color. Second byte identification bit LNB3 LNB2 LNB1 LNB0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 -- 0 1 0 1 0 1 0 1 0 1 0 1 -- Specified line Do not change the line background Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Specifies the line whose background is to be changed. (Specifying the same line with LNA*, LNB*, and LNC* is not allowed.) Function Notes
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-17/30
LC74794, 74794M COMMAND10 (Display control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 0 0 1 1 Extended command 3 identification code Command 7 identification code Display control setup Function Notes
Second byte
DA 0 to 7 7 Register -- Contents State 0 0 6 LNC3 1 0 5 LNC2 1 0 4 LNC1 1 0 3 LNC0 1 0 2 LPC2 1 0 1 LPC1 1 0 0 LPC0 1 LPC2 0 0 0 0 1 1 1 1 LPC1 0 0 1 1 0 0 1 1 LPC0 0 1 0 1 0 1 0 1 Background color (phase) Cyan Yellow Red Blue Cyan - blue Green Orange Magenta * *: When 2 fsc is used. * * * * * Specifies the background color. Second byte identification bit LNC3 LNC2 LNC1 LNC0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 -- 0 1 0 1 0 1 0 1 0 1 0 1 -- Specified line Do not change the line background Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Specifies the line whose background is to be changed. (Specifying the same line with LNA*, LNB*, and LNC* is not allowed.) Function Notes
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-18/30
LC74794, 74794M COMMAND11 (Display control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 0 1 0 0 Extended command 4 identification code Command 7 identification code Display control setup Function Notes
Second byte
DA 0 to 7 7 6 5 4 3 Register -- -- -- -- LNCSEL Contents State 0 0 0 0 0 1 0 2 MOD3 1 0 1 LNBSEL 1 0 0 MOD2 1 Normal line background color operation RV characters have the color of the PH* specified background color and RV characters have a white background. The specifications when LNCSEL is set to 1. RV characters have the background color specified by PH* and the RV characters themselves are white. Normal line background color operation RV characters have the color of the PH* specified background color and RV characters have a white background. The specifications when LNBSEL is set to 1. RV characters have the background color specified by PH* and the RV characters themselves are white. Valid when LNBSEL is high. Valid when LNCSEL is high. Switches the background color in RV mode for RV specified characters on LNB* specified lines. Switches the background color in RV mode for RV specified characters on LNB* specified lines. Second byte identification bit Function Notes
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-19/30
LC74794, 74794M COMMAND12 (Display control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 0 1 0 1 Extended command 5 identification code Command 7 identification code Display control setup Function Notes
Second byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- SEL2 SEL1 CTL3 Contents State 0 0 0 0 0 0 1 0 1 0 1 External synchronizing signal judgment output signal O/E signal Internal slice data External slice data Use internal V separation. Do not use internal V separation. Signal input from SEPIN (pin 27) when set to 1 V separation switching SYNCJDG (pin 8) output switching Second byte identification bit Function Notes
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-20/30
LC74794, 74794M COMMAND13 (VPS/PDC control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 0 1 1 0 Extended command 6 identification code Command 7 identification code Display control setup Function Notes
Second byte
DA 0 to 7 7 Register -- Contents State 0 0 6 CPA1 1 0 5 CPA0 1 4 -- 0 0 3 VPM3 1 0 2 VPM2 1 0 1 VPM1 1 0 0 VPM0 1 Note: All registers are set to 0 when the LC74794/M is reset by the RST pin. VPM3 VPM2 VPM1 VPM0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Operating mode VPS 8/30/2 (PDC) Automatic PDC and VPS switching 8/30/1 (UDT) Header time 1 Header time 2 Header time 3 Header time 4 Status display 1 Status display 2 Status display 3 Status display 4 CPA1 0 0 1 1 CPA0 0 1 0 1 Clock No.1 No.2 No.3 No.4 Data acquisition clock switching Second byte identification bit Function Notes
No. 5557-21/30
LC74794, 74794M COMMAND14 (VPS/PDC control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 0 1 1 1 Extended command 7 identification code Command 7 identification code Display control setup Function Notes
Second byte
DA 0 to 7 7 6 5 4 3 Register -- -- -- HBS2 HBS1 Contents State 0 0 0 0 1 0 1 0 2 BMS 1 1 EMS 0 1 0 0 DCE 1 Discrimination mode 1 Discrimination mode 2 Discrimination mode 1 Discrimination mode 2 Framing code Error checking enabled (Error checking can be turned on or off on a per-byte When 0, bytes for which error checking is basis.) specified and that have no errors are written to P-S. When 1, all bytes are written to P-S Error checking disabled (Applications can select whether to hold or write regardless of errors. data with errors on a per-byte basis.) Data hold Data write (In VPS mode, the error bit is set to 0.) The handling of bytes for which error checking is turned off when error checking is enabled. Clock line Second byte identification bit Function Notes
Error checking turned on for data unused bytes. VPS: bytes 3, 4, and 6 to 10. PDCC (8/30/2): bytes 7 to 12. Header 1: bytes 14 to 37. Header 2: bytes 14 to 29, Header 3: bytes 14 to 21. Status 1 (3): Error checking specification for bytes whose bytes 7 to 25. Status 2 (4): bytes 7 to 35. data is unused. Bi-phase (VPS), Hamming (PDC), or odd Error checking turned off for data unused bytes. VPS: bytes 3, 4, and 6 to 10. PDCC (8/30/2): bytes 7 to 12. Header 1: bytes parity (header) 14 to 37. Header 2: bytes 14 to 29, Header 3: bytes 14 to 21. Status 1 (3): bytes 7 to 25. Status 2 (4): bytes 7 to 35.
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-22/30
LC74794, 74794M COMMAND15 (VPS/PDC control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 1 0 0 0 Extended command 8 identification code Command 7 identification code Display control setup Function Notes
Second byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- ECV15 ECV14 ECV13 ECV12 ECV11 ECV5 Contents State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 Byte 15 bi-phase error check on (data held) Byte 15 bi-phase error check off (data written) Byte 14 bi-phase error check on (data held) Byte 14 bi-phase error check off (data written) Byte 13 bi-phase error check on (data held) Byte 13 bi-phase error check off (data written) Byte 12 bi-phase error check on (data held) Byte 12 bi-phase error check off (data written) Byte 11 bi-phase error check on (data held) Byte 11 bi-phase error check off (data written) Byte 5 bi-phase error check on (data held) Byte 5 bi-phase error check off (data written) Settings when the VPS data BMS = 0. Settings in parentheses apply when BMS = 1. Second byte identification bit Function Notes
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-23/30
LC74794, 74794M COMMAND16 (VPS/PDC control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 1 0 0 1 Extended command 9 identification code Command 7 identification code Display control setup Function Notes
Second byte
DA 0 to 7 7 Register -- Contents State 0 0 6 ECP19 1 0 5 ECP18 1 0 4 ECP17 1 0 3 ECP16 1 0 2 ECP15 1 0 1 ECP14 1 0 0 ECP13 1 Second byte identification bit Byte 19 Hamming error check on (data held) {Byte 44, 28, 36, 20, 32, 42, 32, and 42} Byte 19 Hamming error check off (data written) {Byte 44, 28, 36, 20, 32, 42, 32, and 42} Byte 18 Hamming error check on (data held) {Byte 43, 27, 35, 19, 31, 41, 31, and 41} Byte 18 Hamming error check off (data written) {Byte 43, 27, 35, 19, 31, 41, 31, and 41} Byte 17 Hamming error check on (data held) {Byte 42, 26, 34, 18, 30, 40, 30, and 40} Byte 17 Hamming error check off (data written) {Byte 42, 26, 34, 18, 30, 40, 30, and 40} Byte 16 Hamming error check on (data held) {Byte 41, 25, 33, 17, 29, 39, 29, and 39} Byte 16 Hamming error check off (data written) {Byte 41, 25, 33, 17, 29, 39, 29, and 39} Byte 15 Hamming error check on (data held) {Byte 40, 24, 32, 16, 28, 38, 28, and 38} Byte 15 Hamming error check off (data written) {Byte 40, 24, 32, 16, 28, 38, 28, and 38} Byte 14 Hamming error check on (data held) {Byte 39, 23, 31, 15, 27, 37, 27, and 37} Byte 14 Hamming error check off (data written) {Byte 39, 23, 31, 15, 27, 37, 27, and 37} Byte 13 Hamming error check on (data held) {Byte 38, 22, 30, 14, 26, 36, 26, and 36} Byte 13 Hamming error check off (data written) {Byte 38, 22, 30, 14, 26, 36, 26, and 36}
Settings when the PDC data (8/30/2) BMS = 0. Settings in parentheses apply when BMS = 1. The items in curly brackets are the bytes for which the odd parity check is turned on and off in header modes 1, 2, 3, and 4 and status modes 1, 2, 3, and 4, respectively.
Function
Notes
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-24/30
LC74794, 74794M COMMAND17 (VPS/PDC control setup command) First byte
DA 0 to 7 7 6 5 4 3 2 1 0 Register -- -- -- -- -- -- -- -- Contents State 1 1 1 1 1 0 1 0 Extended command A identification code Command 7 identification code Display control setup Function Notes
Second byte
DA 0 to 7 7 6 Register -- -- Contents State 0 0 0 5 ECP25 1 0 4 ECP24 1 0 3 ECP23 1 0 2 ECP22 1 0 1 ECP21 1 0 0 ECP20 1 Byte 23 Hamming error check off (data written) Byte 22 Hamming error check on (data held) {Byte ,,, 35, 45, 35, and 45} Byte 22 Hamming error check off (data written) {Byte ,,, 35, 45, 35, and 45} Byte 21 Hamming error check on (data held) {Byte ,,, 34, 44, 34, and 44} Byte 21 Hamming error check off (data written) {Byte ,,, 34, 44, 34, and 44} Byte 20 Hamming error check on (data held) {Byte 45, 29, 37, 21, 33, 43, 33, and 43} Byte 20 Hamming error check off (data written) {Byte 45, 29, 37, 21, 33, 43, 33, and 43} Byte 24 Hamming error check off (data written) Byte 23 Hamming error check on (data held) Byte 25 Hamming error check off (data written) Byte 24 Hamming error check on (data held) Byte 25 Hamming error check on (data held)
Settings when the PDC data (8/30/2) BMS = 0. Settings in parentheses apply when BMS = 1. The items in curly brackets are the bytes for which the odd parity check is turned off in header modes 1, 2, 3, and 4 and status modes 1, 2, 3, and 4, respectively.
Function Second byte identification bit
Notes
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-25/30
LC74794, 74794M PDC/VPS Output Data Formats Data is read out in order starting with bytes 1 and 7
PDC 8/30 mode Output data Format1 Format2 VPS mode Header time mode 1 (3) Header time mode 2 (4)
Data update bits *: The value is 0 when data is updated and 1 when not updated. Byte 1 Bit 7 6 5 4 3 2 1 0 Byte 2 Bit 7 6 5 4 3 2 1 0 Byte 3 Bit 7 6 5 4 3 2 1 0 Byte 4 Bit 7 6 5 4 3 2 1 0 Byte 5 Bit 7 6 5 4 3 2 1 0 Byte 6 Bit 7 6 5 4 3 2 1 0 byte 15 bit 0 1 2 3 4 5 6 7 byte 16 bit 0 1 2 3 4 5 6 7 byte 17 bit 0 1 2 3 4 5 6 7 byte 18 bit 0 1 2 3 4 5 6 7 byte 19 bit 0 1 2 3 4 5 6 7 byte 20 bit 0 1 2 3 4 5 6 7 byte 16 bit 0 1 2 3 byte 17 bit 0 1 2 3 byte 18 bit 0 1 2 3 byte 19 bit 0 1 2 3 byte 20 bit 0 1 2 3 byte 21 bit 0 1 2 3 byte 22 bit 0 1 2 3 byte 23 bit 0 1 2 3 byte 14 bit 0 1 2 3 byte 15 bit 0 1 2 3 byte 24 bit 0 1 2 3 byte 25 bit 0 1 2 3 byte 11 bit 0 1 2 3 4 5 6 7 byte 12 bit 0 1 2 3 4 5 6 7 byte 13 bit 0 1 2 3 4 5 6 7 byte 14 bit 0 1 2 3 4 5 6 7 byte 5 bit 0 1 2 3 4 5 6 7 byte 15 bit 0 1 2 3 4 5 6 7 byte 38 bit 0 (30) 1 2 3 4 5 6 7 byte 39 bit 0 (31) 1 2 3 4 5 6 7 byte 40 bit 0 (32) 1 2 3 4 5 6 7 byte 41 bit 0 (33) 1 2 3 4 5 6 7 byte 42 bit 0 (34) 1 2 3 4 5 6 7 byte 43 bit 0 (35) 1 2 3 4 5 6 7 byte 22 bit 0 (14) 1 2 3 4 5 6 7 byte 23 bit 0 (15) 1 2 3 4 5 6 7 byte 24 bit 0 (16) 1 2 3 4 5 6 7 byte 25 bit 0 (17) 1 2 3 4 5 6 7 byte 26 bit 0 (18) 1 2 3 4 5 6 7 byte 27 bit 0 (19) 1 2 3 4 5 6 7
Continued on next page.
No. 5557-26/30
LC74794, 74794M
Continued from preceding page.
PDC 8/30 mode Output data Byte 7 Bit 7 6 5 4 3 2 1 0 Byte 8 Bit 7 6 5 4 3 2 1 0 Byte 9 Bit 7 6 5 4 3 2 1 0 Byte 10 Bit 7 6 5 4 3 2 1 0 Byte 11 Bit 7 6 5 4 3 2 1 0 Byte 12 Bit 7 6 5 4 3 2 1 0 Byte 13 Bit 7 6 5 4 3 2 1 0 Format1 byte 21 bit 0 1 2 3 4 5 6 7 byte 13 bit 0 1 2 3 4 5 6 7 byte 14 bit 0 1 2 3 4 5 6 7 byte 22 bit 0 1 2 3 4 5 6 7 byte 23 bit 0 1 2 3 4 5 6 7 byte 24 bit 0 1 2 3 4 5 6 7 byte 25 bit 0 1 2 3 4 5 6 7 Format2 byte 13 bit 0 1 2 3 1 1 1 1 Error byte 16 information 1 17 18 19 20 21 22 23 Error byte 14 information 2 15 24 25 13 0 0 0 1 1 1 1 1 1 1 0 Error byte 11 information 1 12 13 14 5 15 0 0 VPS mode Header time mode 1 (3) byte 44 bit 0 (36) 1 2 3 4 5 6 7 byte 45 bit 0 (37) 1 2 3 4 5 6 7 Error byte 38 (30) information 39 (31) 40 (32) 41 (33) 42 (34) 43 (35) 44 (36) 45 (37) Header time mode 2 (4) byte 28 bit 0 (20) 1 2 3 4 5 6 7 byte 29 bit 0 (21) 1 2 3 4 5 6 7 Error byte 22 (14) information 23 (15) 24 (16) 25 (17) 26 (18) 27 (19) 28 (20) 29 (21)
Bits for which there is no data setting are 1.
No. 5557-27/30
LC74794, 74794M Data is read out in order starting with bytes 1 and 7 1, 2 : 8/30/2 3, 4 : 8/30/1
Output data Status display mode 1 (3) Status display mode 2 (4) Output data Byte 8 Bit 7 6 5 4 3 2 1 0 Byte 9 Bit 7 6 5 4 3 2 1 0 Byte 10 Bit 7 6 5 4 3 2 1 0 Byte 11 Bit 7 6 5 4 3 2 1 0 Byte 12 Bit 7 6 5 4 3 2 1 0 Byte 13 Bit 7 6 5 4 3 2 1 0 Bits for which there is no data setting are 1. Status display mode 1 (3) byte 33 bit 0 (33) 1 2 3 4 5 6 7 byte 34 bit 0 (34) 1 2 3 4 5 6 7 byte 35 bit 0 (35) 1 2 3 4 5 6 7 Error byte 26 (26) information 1 27 (27) 28 (28) 29 (29) 30 (30) 31 (31) 32 (32) 33 (33) Error byte 34 (34) information 2 35 (35) 0 0 0 0 0 0 Status display mode 2 (4) byte 43 bit 0 (43) 1 2 3 4 5 6 7 byte 44 bit 0 (44) 1 2 3 4 5 6 7 byte 45 bit 0 (45) 1 2 3 4 5 6 7 Error byte 36 (36) information 1 37 (37) 38 (38) 39 (39) 40 (40) 41 (41) 42 (42) 43 (43) Error byte 44 (44) information 2 45 (45) 0 0 0 0 0 0
Data update bits *: The value is 0 when data is updated. Byte 1 Bit 7 6 5 4 3 2 1 0 Byte 2 Bit 7 6 5 4 3 2 1 0 Byte 3 Bit 7 6 5 4 3 2 1 0 Byte 4 Bit 7 6 5 4 3 2 1 0 Byte 5 Bit 7 6 5 4 3 2 1 0 Byte 6 Bit 7 6 5 4 3 2 1 0 Byte 7 Bit 7 6 5 4 3 2 1 0 byte 26 bit 0 (26) 1 2 3 4 5 6 7 byte 27 bit 0 (27) 1 2 3 4 5 6 7 byte 28 bit 0 (28) 1 2 3 4 5 6 7 byte 29 bit 0 (29) 1 2 3 4 5 6 7 byte 30 bit 0 (30) 1 2 3 4 5 6 7 byte 31 bit 0 (31) 1 2 3 4 5 6 7 byte 32 bit 0 (32) 1 2 3 4 5 6 7 byte 36 bit 0 (36) 1 2 3 4 5 6 7 byte 37 bit 0 (37) 1 2 3 4 5 6 7 byte 38 bit 0 (38) 1 2 3 4 5 6 7 byte 39 bit 0 (39) 1 2 3 4 5 6 7 byte 40 bit 0 (40) 1 2 3 4 5 6 7 byte 41 bit 0 (41) 1 2 3 4 5 6 7 byte 42 bit 0 (42) 1 2 3 4 5 6 7
No. 5557-28/30
LC74794, 74794M Display Screen Structure The display consists of 12 lines of 24 characters each. Up to 288 characters can be displayed. The number of characters that can be displayed is reduced from the normal total of 288 when enlarged characters are displayed. Display memory addresses are specified as row (0 to b hexadecimal) and column (0 to 17 hexadecimal) addresses. Display Screen Structure (display memory addresses) 24 characters x 12 rows
No. 5557-29/30
LC74794, 74794M Composite Video Signal Output Levels (internally generated levels) CVOUT output level waveform (VDD2 = 5.0 V)
Output level VCHA: Character VRSH: Background color high VCBH: Color burst high VRSL: Background color low VBK1: Border VBK0: Border VPD: Pedestal VCBL: Color burst low VSN: Sync
Output voltage (1) [V] 2.65 2.37 (2.01) 1.67 1.23 (1.16) 2.08 1.50 1.37 1.07 0.80
Output voltage (2) [V] 2.85 2.57 (2.21) 1.87 1.43 (1.36) 2.28 1.70 1.57 1.27 1.00
Output voltage (3) [V] 3.15 2.87 (2.51) 2.17 1.73 (1.66) 2.58 2.00 1.87 1.57 1.30
Note: VDD2 = 5.0 V. Values in parentheses for VRSH and VRSL apply when the background color is blue.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 5557-30/30

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