View HMA510883_134312.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HMA510/883
April 1997
16 x 16-Bit CMOS Parallel Multiplier Accumulator
Description
The HMA510/883 is a high speed, low power CMOS 16 x 16-bit parallel multiplier accumulator capable of operating at 55ns clocked multiply-accumulate cycles. The 16-bit X and Y operands may be specified as either two's complement or unsigned magnitude format. Additional inputs are provided for the accumulator functions which include: loading the accumulator with the current product, adding or subtracting the accumulator contents and the current product, and preloading the Accumulator Registers from the external inputs. All inputs and outputs are registered. The registers are all positive edge triggered, and are latched on the rising edge of the associated clock signal. The 35-bit Accumulator Output Register is broken into three parts. The 16-bit least significant product (LSP), the 16-bit most significant product (MSP), and the 3-bit extended product (XTP) Registers. The XTP and MSP Registers have dedicated output ports, while the LSP Register shares the Y-inputs in a multiplexed fashion. The entire 35-bit Accumulator Output Register may be preloaded at any time through the use of the bidirectional output ports and the preloaded control.
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * 16 x 16-Bit Parallel Multiplication with Accumulation to a 35-Bit Result * High-Speed (55ns) Multiply Accumulate Time * Low Power CMOS Operation - ICCSB = 500A Maximum - ICCOP = 7.0mA Maximum at 1.0MHz * HMA510/883 is Compatible with the CY7C510 and the IDT7210 * Supports Two's Complement or Unsigned Magnitude Operations * Three-State Outputs
Ordering Information
PART NUMBER HMA510GM-55/883 HMA510GM-65/883 HMA510GM-75/883 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 PACKAGE 68 Ld CPGA 68 Ld CPGA 68 Ld CPGA PKG. NO. G68.B G68.B G68.B
Block Diagram
X0-15 16 RND TC SUB Y0-15 P0-15 16 ACC
REGISTER CLKY CLKX
REGISTER
REGISTER
MULTIPLIER ARRAY 35 PRELOAD CLKP ACCUMULATOR XTP REGISTER MSP REGISTER 3 LSP REGISTER 16 35
16
OEX OEM OEL
P32-34 P16-31
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
2807.2
3-10
HMA510/883 Pinout
68 LEAD CPGA TOP VIEW
11 N/C X15 RND ACC CLKY TC PREL CLKP P33
10
X13
X14
OEL
SUB
CLKX
VCC
OEX
OEM
P34
P32
N/C
9
X11
X12
P30
P31
8
X9
X10
P28
P29
7
X7
X8 TOP VIEW
P26
P27
6
X5
X6
P24
P25
5
X3
X4
P22
P23
4
X1
X2
P20
P21
3
Y0/P0
X0 Y10/ P10 Y11/ P11 G Y12/ P12 Y13/ P13 H Y14/ P14 Y15/ P15 J
P18
P19
2
N/C
Y1/P1
Y3/P3 Y5/P5
Y7/P7 Y8/P8
P16
P17
1 A
Y2/P2 B
Y4/P4 Y6/P6 C D
GND E
Y9/P9 F
N/C K L
Pin Descriptions
NAME VCC GND X0-X15 I TYPE DESCRIPTION The +5V power supply pins. 0.1F capacitors between the VCC and GND pins are recommended. The device ground. X-Input Data. These 16 data inputs provide the multiplicand which may be in two's complement or unsigned magnitude format. Y-Input/LSP Output Data. This 16-bit port is used to provide the multiplier which may be in two's complement or unsigned magnitude format. It may also be used for output of the least significant product (P0-P15) or for preloading the LSP Register. MSP Output Data. This 16-bit port is used to provide the most significant product output (P16-P31). It may also be used to preload the MSP Register. XTP Output Data. This 3-bit port is used to provide the extended product output (P32-P34). It may also be used to preload the XTP Register. Two's Complement Control. Input data is interpreted as two's complement when this control is HIGH. A LOW indicates the data is to be interpreted as unsigned magnitude format. This control is latched on the rising edge of CLKX or CLKY. Accumulate Control. When this control is HIGH, the Accumulator Output Register contents are added to or subtracted from the current product, and the result is stored back into the Accumulator Output Register. When LOW, the product is loaded into the Accumulator Output Register overwriting the current contents. This control is also latched on the rising edge of CLKX or CLKY.
Y0-Y15/P0-P15
I/O
P16-P3
I/O
P32-P34
I/O
TC
I
ACC
I
3-11
HMA510/883 Pin Descriptions
NAME SUB (Continued) DESCRIPTION Subtract Control. When both SUB and ACC are HIGH, the Accumulator Register contents are subtracted from the current product. When ACC is HIGH and SUB is LOW, the Accumulator Register contents and the current product are summed. The SUB control input is latched on the rising edge of CLKX or CLKY. Round Control. When this control is HIGH, a one is added to the most significant bit of the LSP. When LOW, the product is unchanged. Preload Control. When this control is HIGH, the three bidirectional ports may be used to preload the Accumulator Registers. The three-state controls (OEX, OEM, OEL) must be HIGH, and the data will be preloaded on the rising edge of CLKP. When this control is LOW, the Accumulator Registers function in a normal manner. Y-Input/LSP Output Port Three-State Control. When OEL is HIGH, the output drivers are in the high impedance state. This state is required for Y-data input or preloading the LSP Register. When OEL is LOW, the port is enabled for LSP output. MSP Output Port Three-State Control. A LOW on this control line enables the port for output. When OEM is HIGH, the output drivers are in the high impedance state. This control must be HIGH for preloading the MSP Register. XTP Output Port Three-State Control. A LOW on this control line enables the port for output. When OEX is HIGH, the output drivers are in the high impedance state. This control must be HIGH for preloading the XTP Register. X-Register Clock. The rising edge of this clock latches the X-Data Input Register along with the TC, ACC, SUB and RND inputs. Y-Register Clock. The rising edge of this clock latches the Y-Data Input Register along with the TC, ACC, SUB and RND inputs. Product Register Clock. The rising edge of CLKP latches the LSP, MSP and XTP Registers. If the preload control is active, the data on the I/O ports is loaded into these registers. If preload is not active, the accumulated product is loaded into the registers.
TYPE I
RND
I
PREL
I
OEL
I
OEM
I
OEX
I
CLKX
I
CLKY
I
CLKP
I
3-12
HMA510/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input or Output Voltage Applied . . . . . . . . G ND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
JA (oC/W) JC (oC/W) Thermal Resistance (Typical, Note 1) CPGA Package . . . . . . . . . . . . . . . . . . 43 10 Maximum Package Power Dissipation at 125oC CPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.17W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . . 65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . 55oC to 125oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4800 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. HMA5lO/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested GROUP A SUBGROUPS 1, 2, 3 TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125
PARAMETER Logical One Input Voltage Logical Zero Input Voltage Output HIGH Voltage
SYMBOL VlH VIL VOH VOL II IO ICCSB
TEST CONDITIONS VCC = 5.5V VCC = 4.5V IOH = -400A VCC = 4.5V (Note 2) IOL = +4.0mA VCC = 4.5V (Note 2) VlN = VCC or GND VOUT = VCC or GND, VCC = 5.5V VIN = VCC or GND, VCC = 5.5V, Outputs Open f = 1.0MHz, VIN = VCC or GND VCC = 5.5V (Note 3) (Note 4)
MIN 2.2
MAX -
UNITS V
1, 2, 3
-
0.8
V
1, 2, 3
2.6
-
V
Output LOW Voltage
1, 2, 3
-
0.4
V A A A
Input Leakage Current Output or I/O Leakage Current Standby Power Supply Current
1, 2, 3 1, 2, 3
-10 -10
+10 +10
1, 2, 3
-
500
Operating Power Supply Current
ICCOP
1, 2, 3
-55 TA 125
-
7.0
mA
Functional Test NOTES:
FT
7, 8
-55 TA 125
-
-
2. Interchanging of force and sense conditions is permitted. 3. Operating Supply Current a proportional to frequency, typical rating is 5mA/MHz. 4. Tested as follows: f = 1MHz, VIH (clock inputs) = 3.2V, VlH (all other inputs) = 2.6V, VIL = 0.4V, VOH 1.5V, and VOL 1.5V. TABLE 2. HMA510/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested -55 PARAMETER Multiply Accumulate Time Input Setup Time SYMBOL tMA tS (NOTE 5) CONDITIONS GROUP A SUBGROUPS 9, 10, 11 TEMPERATURE (oC) -55 TA 125 -55 TA 125 -65 -75
MIN MAX MIN MAX MIN MAX UNITS 55 65 75 ns
9, 10, 11
20
-
25
-
25
-
ns
3-13
HMA510/883
TABLE 2. HMA510/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Guaranteed and 100% Tested -55 PARAMETER Clock HIGH Pulse Width Clock LOW Pulse Width Output Delay Three-State Enable Time NOTES: 5. AC Testing as follows: VCC = 4.5V and 5.5V. Input levels 0V and 3.0V (0V and 3.2V tor clock inputs). Timing reference levels = 1.5V, Output load per test load circuit, with V1 = 2.4V, R1 = 500 and CL = 40pF. 6. Transition is measured at 1200mV from steady state voltage, Output loading per test load circuit, with V1 = 1.5V, R1 = 500 and CL = 40pF. TABLE 3. HMA510/883 ELECTRICAL PERFORMANCE SPECIFICATIONS -55 PARAMETER lnput Capacitance SYMBOL CIN TEST CONDITIONS VCC = Open, f = 1MHz All measurements are referenced to device GND NOTE 1 TEMPERATURE (oC) TA = 25 -65 -75 SYMBOL tPWH tPWL tD tENA (Note 5) (NOTE 5) CONDITIONS GROUP A SUBGROUPS 9, 10, 11 TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -65 -75
MIN MAX MIN MAX MIN MAX UNITS 20 25 25 ns
9, 10, 11
20
-
25
-
25
-
ns
9, 10, 11 9, 10, 11
-
30 30
-
35 30
-
35 35
ns ns
MIN MAX MIN MAX MIN MAX UNITS 10 10 10 pF
Output Capacitance I/O Capacitance Input Hold Time Three-State Disable Time Output Rise Time Output Fall Time NOTE:
COUT CI/O tH tDIS tr tf From 0.8V to 2.0V From 2.0V to 0.8V
1 1 1 1
TA = 25 TA = 25 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125
3 -
10 15 30
3 -
10 15 30
3 -
10 15 30
pF pF ns ns
1 1
-
10 10
-
10 10
-
10 10
ns ns
7. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C and D METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS 1 2, 3, 8A, 8B, 10,11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
3-14
HMA510/883 AC Test Circuit
V1 R1 VIH DUT C1 (SEE NOTE) VIL 1.5V 1.5V VOH VOL
AC Testing Input, Output Waveforms
NOTE: Includes Stray and Jig Capacitance
NOTE: AC Testing: All Parameters tested as per test circuit. Input rise and fall times are driven at 1ns/V.
Timing Diagram
DATA INPUT 3.0V 1.5V 0V 3.0V 1.5V 0V THREE STATE CONTROL tDIS OUTPUT THREE STATE tENA 1.5V
tS
tH
CLOCK INPUT
HIGH IMPEDANCE
FIGURE 1. SET-UP AND HOLD TIME
tPWL tPWH CLKX CLKY XIN, YIN RND, TC ACC, SUB CLKP tS tHCL
FIGURE 2. THREE-STATE CONTROL
tPWH tH CLKP tMA tD PREL OEX OEM OEL OUTPUT PINS
tPWL
tS
tH
OUTPUT P, Y
FIGURE 3. HMA510 TIMING DIAGRAM
FIGURE 4. PRELOAD TIMING DIAGRAM
3-15
HMA510/883 Burn-In Circuit
68 LEAD CPGA TOP VIEW
11 N/C X15 RND ACC CLKY TC PREL CLKP P33
10
X13
X14
OEL
SUB
CLKX
VCC
OEX
OEM
P34
P32
N/C
9
X11
X12
P30
P31
8
X9
X10
P28
P29
7
X7
X8
P26
P27
6
X5
X6
P24
P25
5
X3
X4
P22
P23
4
X1
X2
P20
P21
3
Y0/P0
X0 Y10/ P10 Y11/ P11 G Y12/ P12 Y13/ P13 H Y14/ P14 Y15/ P15 J
P18
P19
2
N/C
Y1/P1
Y3/P3 Y5/P5
Y7/P7 Y8/P8
P16
P17
1 A
Y2/P2 B
Y4/P4 Y6/P6 C D
GND E
Y9/P9 F
N/C K L
CPGA PIN B6 A6 B5 A5 B4 A4 B3 A3 B2 B1 C2 C1 D2 D1 E2 E1 F2 F1 G2 X6 X5 X4 X3 X2 X1 X0
PIN NAME
BURN-IN SIGNAL F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 GND F1 F2 F3 G1 H2 H1 J2 J1 K2 L2 K3 L3 K4 L4 K5 L5 K6 L6 K7 L7 K8 L8
CPGA PIN
PIN NAME Y11/P11 Y12/P12 Y13/P13 Y14/P14 Y15/P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29
BURN-IN SIGNAL F5 F4 F4 F8 F9 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
Y0/P0 Y1/P1 Y2/P2 Y3/P3 Y4/P4 Y5/P5 Y6/P6 Y7/P7 GND Y8/P8 Y9/P9 Y10/P10
3-16
HMA510/883
CPGA PIN K9 L9 K10 K11 J10 J11 H10 H11 G10 G11 F10 F11 E10 E11 D10 D11 C10 C11 B10 A10 B9 A9 B8 A8 B7 A7 A2 K1 L10 B11 NOTES: 8. VCC = 5.5V +0.5V/-0.0V with 0.1F decoupling capacitor to GND. 9. F0 = 100kHz, F1 = F0/2, F2 = F1/2, . . . . . . . . . . . . . . . . . 10% 10. VlH = VCC - 1V 0.5V (Min), VIL = 0.8V (Max). 11. 47k load resistors used on all pins except VCC and GND (PinGrid identifiers F10, G10, G11 and H11). P30 P31 P32 P33 P34 CLKP OEM PREL OEX TC VCC CLKY CLKY ACC SUB RND OEL X15 X14 X13 X12 X11 X10 X9 X8 X7 N.C. N.C. N.C. N.C. PIN NAME BURN-IN SIGNAL VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 F0 GND F6 GND F5 VCC F0 F0 F1 F2 F3 VCC F8 F9 F10 F11 F12 F13 F14 F15 F7 N.C. N.C. N.C. N.C.
3-17
HMA510/883 Die Characteristics
DIE DIMENSIONS: 184 x 176 x 19 1mils METALLIZATION: Type: Si - Al or Si-Al-Cu Thickness: 8kA GLASSIVATION: Type: Nitrox Thickness: 10kA WORST CASE CURRENT DENSITY: 0.9 x 105A/cm2
Metallization Mask Layout
HMA510/883
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
3-18

▲Up To Search▲

Price & Availability of HMA510883

	To Download HMA510883 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .