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GAL6001
High Performance E2CMOS FPLA Generic Array LogicTM Features
* HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- 30ns Maximum Propagation Delay -- 27MHz Maximum Frequency -- 12ns Maximum Clock to Output Delay -- TTL Compatible 16mA Outputs -- UltraMOS(R) Advanced CMOS Technology * LOW POWER CMOS -- 90mA Typical Icc * E2 CELL TECHNOLOGY -- Reconfigurable Logic -- Reprogrammable Cells -- 100% Tested/100% Yields -- High Speed Electrical Erasure (<100ms) -- 20 Year Data Retention * UNPRECEDENTED FUNCTIONAL DENSITY -- 78 x 64 x 36 FPLA Architecture -- 10 Output Logic Macrocells -- 8 Buried Logic Macrocells -- 20 Input and I/O Logic Macrocells * HIGH-LEVEL DESIGN FLEXIBILITY -- Asynchronous or Synchronous Clocking -- Separate State Register and Input Clock Pins -- Functional Superset of Existing 24-pin PAL(R) and FPLA Devices * APPLICATIONS INCLUDE: -- Sequencers -- State Machine Control -- Multiple PLD Device Integration
Functional Block Diagram
ICLK
INPUT CLOCK 2 INPUTS 2-11 14 23
11
{
ILMC
RESET
IOLMC
AND
OUTPUT ENABLE
14
D E
23
OLMC
0 7
OR
D
BLMC
E
{ OUTPUTS 14 - 23
OCLK OUTPUT CLOCK
Macrocell Names
ILMC BLMC OLMC INPUT LOGIC MACROCELL BURIED LOGIC MACROCELL OUTPUT LOGIC MACROCELL IOLMC I/O LOGIC MACROCELL
Pin Names
I0 - I10 ICLK OCLK INPUT INPUT CLOCK OUTPUT CLOCK I/O/Q VCC GND BIDIRECTIONAL POWER (+5) GROUND
Description
Using a high performance E2CMOS technology, Lattice Semiconductor has produced a next-generation programmable logic device, the GAL6001. Having an FPLA architecture, known for its superior flexibility in state-machine design, the GAL6001 offers a high degree of functional integration and flexibility in a 24pin, 300-mil package. The GAL6001 has 10 programmable Output Logic Macrocells (OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In addition, there are 10 Input Logic Macrocells (ILMC) and 10 I/O Logic Macrocells (IOLMC). Two clock inputs are provided for independent control of the input and output macrocells. Advanced features that simplify programming and reduce test time, coupled with E2CMOS reprogrammable cells, enable 100% AC, DC, programmability, and functionality testing of each GAL6001 during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
Pin Configuration
PLCC
I/ICLK
I/ICLK
DIP
1 24 Vcc I/O/Q I/O/Q I
Vcc
NC
I/O/Q
I/O/Q
I
I I
25 I/O/Q I/O/Q
I
4 I I I NC I I I 11 12 9 7 5
2
28
26
I I I I I I I GND 12 6
GAL 6001
18
I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q 13 OCLK
GAL6001
Top View
14 16
23
I/O/Q NC
21
I/O/Q I/O/Q
19 18
I/O/Q
I
I
OCLK
GND
NC
I/O/Q
Copyright (c) 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
I/O/Q
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
July 1997
6001_02
1
Specifications GAL6001
GAL6001 Ordering Information
Commercial Grade Specifications
Tpd (ns)
30
Fmax (MHz)
27
Icc (mA)
150 150
Ordering #
GAL6001B-30LP GAL6001B-30LJ
Package
24-Pin Plastic DIP 28-Lead PLCC
Part Number Description
XXXXXXXX _ XX X XX
GAL6001B Device Name Grade Blank = Commercial
Speed (ns) L = Low Power Power
Package P = Plastic DIP J = PLCC
2
Specifications GAL6001
Input Logic Macrocell (ILMC) and I/O Logic Macrocell (IOLMC)
The GAL6001 features two configurable input sections. The ILMC section corresponds to the dedicated input pins (2-11) and the IOLMC to the I/O pins (14-23). Each input section is configurable as a block for asynchronous, latched, or registered inputs. Pin 1 (ICLK) is used as an enable input for latched macrocells or as a clock input for registered macrocells. Configurable input blocks provide system designers with unparalleled design flexibility. With the GAL6001, external registers and latches are not necessary. Both the ILMC and the IOLMC are block configurable. However, the ILMC can be configured independently of the IOLMC. The three valid macrocell configurations are shown in the macrocell equivalent diagrams on the following pages.
Output Logic Macrocell (OLMC) and Buried Logic Macrocell (BLMC)
The outputs of the OR array feed two groups of macrocells. One group of eight macrocells is buried; its outputs feed back directly into the AND array rather than to device pins. These cells are called the Buried Logic Macrocells (BLMC), and are useful for building state machines. The second group of macrocells consists of 10 cells whose outputs, in addition to feeding back into the AND array, are available at the device pins. Cells in this group are known as Output Logic Macrocells (OLMC). The Output and Buried Logic Macrocells are configurable on a macrocell by macrocell basis. Buried and Output Logic Macrocells may be set to one of three configurations: combinatorial, D-type register with sum term (asynchronous) clock, or D/E-type register. Output macrocells always have I/O capability, with directional control provided by the 10 output enable (OE) product terms. Additionally, the polarity of each OLMC output is selected through the "D" XOR. Polarity selection is available for BLMCs, since both the true and complemented forms of their outputs are available in the AND array. Polarity of all "E" sum terms is selected through the "E" XOR. When the macrocell is configured as a D/E type register, it is clocked from the common OCLK and the register clock enable input is controlled by the associated "E" sum term. This configuration is useful for building counters and state-machines with state hold functions. When the macrocell is configured as a D-type register with a sum term clock, the register is always enabled and its "E" sum term is routed directly to the clock input. This permits asynchronous programmable clocking, selected on a register-by-register basis. Registers in both the Output and Buried Logic Macrocells feature a common RESET product term. This active high product term allows the registers to be asynchronously reset. Registers are reset to a logic zero. If connected to an output pin, a logic one will occur because of the inverting output buffer. There are two possible feedback paths from each OLMC. The first path is directly from the OLMC (this feedback is before the output buffer and always present). When the OLMC is used as an output, the second feedback path is through the IOLMC. With this dual feedback arrangement, the OLMC can be permanently buried (the associated OLMC pin is an input), or dynamically buried with the use of the output enable product term. The D/E registers used in this device offer the designer the ultimate in flexibility and utility. The D/E register architecture can emulate RS-, JK-, and T-type registers with the same efficiency as a dedicated RS-, JK-, or T-register. The three macrocell configurations are shown in the macrocell equivalent diagrams on the following pages.
3
Specifications GAL6001
ILMC and IOLMC Configurations
ICLK
LATCH E Q D INVALID REG.
INPUT or I/O 10
MUX
0 0 1 1
0 1
10
Q D
0 1
AND ARRAY
LATCH
ISYN
ILMC/IOLMC
Generic Logic Block Diagram
ILMC (Input Logic Macrocell) JEDEC Fuse Numbers ISYN 8218 LATCH 8219
IOLMC (I/O Logic Macrocell) JEDEC Fuse Numbers ISYN 8220 LATCH 8221
4
Specifications GAL6001
OLMC and BLMC Configurations
OE PRODUCT TERM RESET
AND ARRAY
IOLMC
OLMC ONLY
MUX
XORD(i)
D
R D MUX
Vcc
1
I/O
0 1
Q E
0
OLMC ONLY
XORE(i)
E
OSYN(i)
CKS(i)
MUX
0
1
OCLK
OLMC/BLMC
Generic Logic Block Diagram OLMC (Output Logic Macrocell) JEDEC Fuse Numbers OLMC 0 1 2 3 4 5 6 7 8 9 OCLK 8178 8182 8186 8190 8194 8198 8202 8206 8210 8214 OSYN 8179 8183 8187 8191 8195 8199 8203 8207 8211 8215 XORE 8180 8184 8188 8192 8196 8200 8204 8208 8212 8216 XORD 8181 8185 8189 8193 8197 8201 8205 8209 8213 8217 BLMC 7 6 5 4 3 2 1 0 BLMC (Buried Logic Macrocell) JEDEC Fuse Numbers OCLK 8175 8172 8169 8166 8163 8160 8157 8154 OSYN 8176 8173 8170 8167 8164 8161 8158 8155 XORE 8177 8174 8171 8168 8165 8162 8159 8156
5
ICLK
1(2)
2(3)
GAL6001 Logic Diagram
3(4)
LTC H.
4(5)
5(6)
6(7)
MU X
R EG.
7(9)
8(10)
9(11) 10(12)
BLMC 0
BLMC 1
11(13)
BLMC 2
BLMC 3
6
BLMC 4
BLMC 5
BLMC 6
BLMC 7
IOLMC 9
LTCH.
IOLMC 8 IOLMC 7 IOLMC 6 IOLMC 5
MUX
IOLMC 4 IOLMC 3 IOLMC 2 IOLMC 1 IOLMC 0
REG.
OLMC 0 OLMC 1 OLMC 2 OLMC 3 OLMC 4 OLMC 5 OLMC 6 OLMC 7 OLMC 8 OLMC 9
Specifications GAL6001
OLMC 9
R D XORD XORE 0 1 1 R D XORD XORE 0 1 1 R D XORD XORE 0 1 1 R D XORD XORE 0 1 1 R D XORD XORE 0 1 1 R D XORD XORE 0 1 E 0 1 Q 0 0 1 E Q 0 0 1 E Q 0 0 1 E Q 0 0 1 E Q 0 0 1 E Q 0
1
23(27)
1
R
BLMC 7
0
Q
D
E
0 1
XORE
OLMC 8
22(26)
1
0
1
R
BLMC 6
0
Q
D
E
0 1
XORE
OLMC 7
21(25)
1
0
1
R
BLMC 5
0
Q
D
E
0 1
XORE
OLMC 6
20(24)
1
0
1
R
BLMC 4
0
Q
D
E
0 1
XORE
OLMC 5
19(23)
GAL6001 Logic Diagram (Continued)
1
0
1
R
BLMC 3
0
Q
D
E
0 1
XORE
OLMC 4
18(21)
1
0
The number of Differential Product Terms that may switch is limited to a maximum of 15. Refer to the Differential Product Term Switching Applications section of this data sheet for a full explanation.
7
XORD XORE XORD XORE XORD XORE XORD XORE
1
R
BLMC 2
0
Q
D
E
0 1
XORE
OLMC 3
D 0 1 E 0
R Q
1 0
17(20)
1
0
1
R
BLMC 1
0
Q
D
1
E
0 1
XORE
OLMC 2
D 0 1 E 0
R Q
1 0
16(19)
1
0
1
R
BLMC 0
0
Q
D
1
E
0 1
XORE
OLMC 1
D 0 1 E 0
R Q
1 0
15(18)
1
0
1
OLMC 0
D 0 1 E 0
1 R Q 0
14(17)
1
RESET OCLK
Specifications GAL6001
13(16)
Specifications GAL6001
Absolute Maximum Ratings(1)
Supply voltage VCC ...................................... -0.5 to +7V Input voltage applied .......................... -2.5 to VCC +1.0V Off-state output voltage applied ......... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Ambient Temperature with Power Applied ........................................ -55 to 125C
1.Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
Recommended Operating Conditions
Commercial Devices: Ambient Temperature (TA) ............................... 0 to 75C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current Output Low Voltage Output High Voltage Low Level Output Current High Level Output Current Output Short Circuit Current VCC = 5V VOUT = 0.5V 0V VIN VIL (MAX.) 3.5VIH VIN VCC IOL = MAX. Vin = VIL or VIH IOH = MAX. Vin = VIL or VIH CONDITION MIN.
Vss - 0.5
TYP.2 -- -- -- -- -- -- -- -- --
MAX. 0.8 Vcc+1 -10 10 0.5 -- 16 -3.2 -130
UNITS V V A A V V mA mA mA
VIL VIH IIL IIH VOL VOH IOL IOH IOS1
2.0 -- -- -- 2.4 -- -- -30
COMMERCIAL ICC Operating Power
Supply Current
VIL = 0.5V
VIH = 3.0V
L -30
--
90
150
mA
ftoggle = 15MHz Outputs Open
1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 2) Typical values are at Vcc = 5V and TA = 25 C
Capacitance (TA = 25C, f = 1.0 MHz)
SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance MAXIMUM* 8 10 UNITS pF pF TEST CONDITIONS VCC = 5.0V, VI = 2.0V VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
8
Specifications GAL6001
AC Switching Characteristics
Over Recommended Operating Conditions COM -30 MIN. MAX. Combinatorial Input to Combinatorial Output Feedback or I/O to Combinatorial Output Transparent Latch Input to Combinatorial Output Input Latch ICLK to Combinatorial Output Delay Input Reg. ICLK to Combinatorial Output Delay Output D/E Reg. OCLK to Output Delay Output D Reg. Sum Term CLK to Output Delay Setup Time, Input before Input Latch ICLK Setup Time, Input before Input Reg. ICLK Setup Time, Input or Feedback before D/E Reg. OCLK Setup Time, Input or Feedback before D Reg. Sum Term CLK Setup Time, Input Reg. ICLK before D/E Reg. OCLK Setup Time, Input Reg. ICLK before D Reg. Sum Term CLK Hold Time, Input after Input Latch ICLK Hold Time, Input after Input Reg. ICLK Hold Time, Input or Feedback after D/E Reg. OCLK Hold Time, Input or Feedback after D Reg. Sum Term CLK Maximum Clock Frequency, OCLK ICLK or OCLK Pulse Duration, High Sum Term CLK Pulse Duration, High ICLK or OCLK Pulse Duration, Low Sum Term CLK Pulse Duration, Low Reset Pulse Duration Input or I/O to Output Enabled Input or I/O to Output Disabled Input or I/O to Asynchronous Reg. Reset Asynchronous Reset to OCLK Recovery Time Asynchronous Reset to Sum Term CLK Recovery Time -- -- -- -- -- -- -- 2.5 2.5 25 7.5 30 15 5 5 0 10 27 10 15 10 15 15 -- -- -- 20 10 30 30 35 35 35 12 35 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 25 25 35 -- -- UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns
PARAMETER
TEST COND1. A A A A A A A -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B C A -- --
DESCRIPTION
tpd1 tpd2 tpd3 tco1 tco2 tco3 tco4 tsu1 tsu2 tsu3 tsu4 tsu5 tsu6 th1 th2 th3 th4 fmax twh1 twh2 twl1 twl2 tarw ten tdis tar tarr1 tarr2
1) Refer to Switching Test Conditions section.
9
Specifications GAL6001
Switching Waveforms
INPUT or I/O FEEDBACK VALID INPUT
INPUT or I/O FEEDBACK VALID INPUT
tpd1,2
COMBINATORIAL OUTPUT
ICLK (REGISTER)
tsu2
th2 tco2
Combinatorial Output
COMBINATORIAL OUTPUT
tsu5
INPUT or I/O FEEDBACK VALID INPUT
OCLK
tsu1
ICLK (LATCH)
th1
Sum Term CLK
tsu6
tco1
tpd3
COMBINATORIAL OUTPUT
Registered Input Latched Input
INPUT or I/O FEEDBACK VALID INPUT
INPUT or I/O FEEDBACK
VALID INPUT
tsu3
OCLK
th3
tsu4
Sum Term CLK
th4
tco3
tco4
REGISTERED OUTPUT
REGISTERED OUTPUT
1/ fmax
Registered Output (Sum Term CLK)
INPUT or I/O FEEDBACK
Registered Output (OCLK)
tdis
OUTPUT
ten
INPUT or I/O FEEDBACK DRIVING AR REGISTERED OUTPUT
tarw
Input or I/O to Output Enable/Disable
tar
twh1
ICLK or OCLK
twl1
Sum Term CLK
tarr2
twh2 twl2
OCLK
Sum Term CLK
tarr1
Clock Width Asynchronous Reset
10
Specifications GAL6001
fmax Descriptions
CLK
CLK
LOGIC ARRAY
REGISTER
LOGIC ARRAY
REGISTER
tsu
tco
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured tsu and tco.
CLK
tcf tpd
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd.
LOGIC ARRAY
REGISTER
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 3ns 10% - 90% 1.5V 1.5V See Figure
FROM OUTPUT (O/Q) UNDER TEST TEST POINT R1 +5V
3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure) Test Condition A B C Active High Active Low Active High Active Low R1 300 300 300 R2 390 390 390 390 390 CL 50pF 50pF 50pF 5pF 5pF
R2
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
11
Specifications GAL6001
Array Description
The GAL6001 contains two E2 reprogrammable arrays. The first is an AND array and the second is an OR array. These arrays are described in detail below. AND ARRAY The AND array is organized as 78 inputs by 75 product term outputs. The 10 ILMCs, 10 IOLMCs, 8 BLMC feedbacks, 10 OLMC feedbacks, and ICLK comprise the 39 inputs to this array (each available in true and complement forms). 64 product terms serve as inputs to the OR array. The RESET product term generates the RESET signal described in the Output and Buried Logic Macrocells section. There are 10 output enable product terms which allow device pins 14-23 to be bi-directional or tri-state. OR ARRAY The OR array is organized as 64 inputs by 36 sum term outputs. 64 product terms from the AND array serve as the inputs to the OR array. Of the 36 sum term outputs, 18 are data ("D") terms and 18 are enable/clock ("E") terms. These terms feed into the 10 OLMCs and 8 BLMCs, one "D" term and one "E" term to each. The programmable OR array offers unparalleled versatility in product term usage. This programmability allows from 1 to 64 product terms to be connected to a single sum term. A programmable OR array is more flexible than a fixed, shared, or variable product term architecture.
Bulk Erase
Before writing a new pattern into a previously programmed part, the old pattern must first be erased. This erasure is done automatically by the programming hardware as part of the programming cycle and takes only 50 milliseconds.
Register Preload
When testing state machine designs, all possible states and state transitions must be verified, not just those required during normal operations. This is because in system operation, certain events may occur that cause the logic to assume an illegal state: powerup, brown out, line voltage glitches, etc. To test a design for proper treatment of these conditions, a method must be provided to break the feedback paths and force any desired state (i.e., illegal) into the registers. Then the machine can be sequenced and the outputs tested for correct next state generation. All of the registers in the GAL6001 can be preloaded, including the ILMC, IOLMC, OLMC, and BLMC registers. In addition, the contents of the state and output registers can be examined in a special diagnostics mode. Programming hardware takes care of all preload timing and voltage requirements.
Latch-Up Protection
GAL6001 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. Additionally, outputs are designed with n-channel pull-ups instead of the traditional p-channel pull-ups to eliminate any possibility of SCR induced latching.
Electronic Signature
An electronic signature (ES) is provided in every GAL6001 device. It contains 72 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. NOTE: The ES is included in checksum calculations. Changing the ES will alter the checksum.
Input Buffers
GAL devices are designed with TTL level compatible input buffers. These buffers, with their characteristically high impedance, load driving logic much less than traditional bipolar devices. This allows for a greater fan out from the driving logic. GAL6001 devices do not possess active pull-ups within their input structures. As a result, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to another active input, Vcc, or GND. Doing this will tend to improve noise immunity and reduce Icc for the device.
Security Cell
A security cell is provided in every GAL6001 device as a deterrent to unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the AND and OR arrays. This cell can be erased only during a bulk erase cycle, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell.
12
Specifications GAL6001
Power-Up Reset
Vcc
Vcc (min.)
tsu
CLK
twl tpr
INTERNAL REGISTER Q - OUTPUT
Internal Register Reset to Logic "0"
FEEDBACK/EXTERNAL OUTPUT REGISTER
Device Pin Reset to Logic "1"
Circuitry within the GAL6001 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1s MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown below. Because of the asynchronous nature
of system power-up, some conditions must be met to provide a valid power-up reset of the GAL6001. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements.
Differential Product Term Switching (DPTS) Applications
The number of Differential Product Term Switching (DPTS ) for a given design is calculated by subtracting the total number of product terms that are switching from a Logical HI to a Logical LO from those switching from a Logical LO to a Logical HI within a 5ns period. After subtracting take the absolute value. DPTS = (P-Terms)LH - (P-Terms)HL DPTS restricts the number of product terms that can be switched simultaneously - there is no limit on the number of product terms that can be used. A software utility is available from Lattice Semiconductor Applications Engineering that will perform this calculation on any GAL6001 JEDEC file. This program, DPTS, and additional information may be obtained from your local Lattice Semiconductor representative or by contacting Lattice Semiconductor's Applications Engineering Dept. (Tel: 503-6810118 or 1-888-ISP-PLDS; FAX: 681-3037).
13
Specifications GAL6001
Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.2 1.2
Normalized Tco vs Vcc
1.2
Normalized Tsu vs Vcc
Normalized Tpd
1.1
Normalized Tco
Normalized Tsu
PT H->L PT L->H
1
RISE 1.1 FALL
PT H->L
1.1
PT L->H
1
1
0.9
0.9
0.9
0.8 4.50 4.75 5.00 5.25 5.50
0.8 4.50 4.75 5.00 5.25 5.50
0.8 4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs Temp
1.3 1.3
Normalized Tco vs Temp
1.4
Normalized Tsu vs Temp
Normalized Tco
Normalized Tpd
Normalized Tsu
1.2 1.1 1 0.9 0.8 0.7 -55 -25
PT H->L PT L->H
1.2 1.1 1 0.9 0.8 0.7
RISE FALL
1.3 1.2 1.1 1 0.9 0.8 0.7
PT H->L PT L->H
0
25
50
75
100
125
-55
-25
0
25
50
75
100
125
-55
-25
0
25
50
75
100
125
Temperature (deg. C)
Temperature (deg. C) Delta Tpd vs # of Outputs Switching
Temperature (deg. C) Delta Tco vs # of Outputs Switching
0
0
Delta Tpd (ns)
-0.5
Delta Tco (ns)
-0.5
-1
-1
RISE
-1.5
RISE
-1.5
FALL
-2 1 2 3 4 5 6 7 8 9 10
FALL
-2 1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output Loading
12 12
Delta Tco vs Output Loading
Delta Tpd (ns)
Delta Tco (ns)
10 8 6 4 2 0 -2 0 50
RISE FALL
10 8 6 4 2 0 -2
RISE FALL
100
150
200
250
300
0
50
100
150
200
250
300
Output Loading (pF)
Output Loading (pF)
14
Specifications GAL6001
Typical AC and DC Characteristic Diagrams
Vol vs Iol
2.5 2 5 4
Voh vs Ioh
4.5
Voh vs Ioh
4.25
Voh (V)
1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00
3 2 1 0 0.00 10.00 20.00 30.00 40.00 50.00 60.00
Voh (V)
Vol (V)
4
3.75
3.5 0.00 1.00 2.00 3.00 4.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
1.20 1.2
Normalized Icc vs Temp
1.20
Normalized Icc vs Freq.
Normalized Icc
Normalized Icc
1.10
Normalized Icc
1.1 1 0.9 0.8 0.7
1.10
1.00
1.00
0.90
0.90
0.80 4.50 4.75 5.00 5.25 5.50
0.80 -55 -25 0 25 75 100 125 0 25 50 75 100
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Delta Icc vs Vin (1 input)
3 0 10 20
Input Clamp (Vik)
Delta Icc (mA)
2.5
1.5 1 0.5 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Iik (mA)
2
30 40 50 60 70 80 90 100 -2.00 -1.50 -1.00 -0.50 0.00
Vin (V)
Vik (V)
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Price & Availability of GAL6001

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