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FEATURES "CIickless" Bilateral Audio Switching Four SPST Switches in a 20-Pin Package Ultralow THD+N: 0.0008% @ 1 kHz (2 V rms, R L = 100 k ) Low Charge Injection: 35 pC typ High OFF Isolation: -100 dB typ (RL = 10 k @ 1 kHz) Low Crosstalk: -94 dB typ (R L = 10 k @ 1 kHz) Low ON Resistance: 28 typ Low Supply Current: 900 A typ Single or Dual Supply Operation: +11 V to +24 V or 5.5 V to 12 V Guaranteed Break-Before-Make TTL and CMOS Compatible Logic Inputs Low Cost-Per-Switch
CONTROL
Quad Audio Switch SSM2404
BLOCK DIAGRAM OF ONE SWITCH CHANNEL
V- LOGIC INTERFACE AND BREAK-BEFORE-MAKE CONTROL RAMP GENERATOR SW1 A SW1 B
DIGITAL CONTROL
V+
PIN CONNECTIONS Epoxy Mini-DIP (P Suffix) and SOIC (S Suffix)
GENERAL DESCRIPTION
SW1 A AGND SW1 B DGND SW1 CONTROL SW2 CONTROL NC* SW2 B AGND SW2 A
1 2 3 4 5 6 7 8 9 10 NC = NO CONNECT SW2 SW3 SW1 SW1 SW4
20 19 18
SW4 A AGND SW4 B V+ SW4 CONTROL SW3 CONTROL V- SW3 B AGND SW3 A
The SSM2404 integrates four SPST analog switches in a single 20-pin package. Developed specifically for high performance audio applications, distortion and noise are negligible over the full operating range of 20 Hz to 20 kHz. With very low charge injection of 35 pC, "clickless" audio switching is possible, even under the most demanding conditions. Switch control is realized by conventional TTL or CMOS logic. Guaranteed "break-before-make" operation assures that all switches in a large system will open before any switch reaches the ON state. Single or dual supply operation is possible. Additional features include -100 dB OFF isolation, -94 dB crosstalk and 28 ON resistance. Optional current-mode switching permits an extended signal-handling range. Although optimized for large load impedances, the SSM2404 maintains good audio performance even under low load impedance conditions.
O
TOP VIEW (Not to Scale) SSM2404
17 16 15 14 13 12 11
*CONNECT TO ANALOG GROUND
FOR BEST NOISE ISOLATION
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
SSM2404-SPECIFICATIONS
Parameter AUDIO PERFORMANCE Total Harmonic Distortion Plus Noise Spectral Noise Density Wideband Noise Density ANALOG SIGNAL SECTION Analog Voltage Range Analog Current Range ON Resistance RON Matching ON Leakage Current OFF Leakage Current Charge Injection ON-State Input Capacitance OFF-State Input Capacitance OFF Isolation Channel-to-Channel Crosstalk CONTROL SECTION Digital Input High Digital Input Low Turn-On Time1 Turn-Off Time2 Break-Before-Make Time Delay Logic Input Current Logic HI Logic LO POWER SUPPLY Supply Voltage Range Positive Supply Current Negative Supply Current Ground Current Symbol THD+N en en p-p VA IA RON RON Match IS(ON) IS(OFF) Q CON COFF ISO(OFF) CT VINH VINL tON tOFF tON-tOFF
(VS = 12 V, TA = +25 C, unless otherwise noted. Typical specifications apply at TA = +25 C.)
Conditions @ 1 kHz, with 80 kHz Filter, RL = 100 k, VIN = 2 V rms 20 Hz to 20 kHz 20 Hz to 20 kHz VINH = 2.4 V, IA = 2 mA VINH = 2.4 V, VA = 0 V IA = 10 mA, VA = 10 V dc IA = 10 mA, VA = 0 V VA = 10 V VA = 10 V VA = 5 V rms VA = 5 V rms VA = 50 mV rms, f = 1 kHz, RL = 10 k VA = 50 mV rms, f = 1 kHz, RL = 10 k DGND = 0 V DGND = 0 V See Test Circuit See Test Circuit 2.4 0 8 5 3 -1000 1.3 -1000 1.0 +11 5.5 -1.5 -2.0 0.9 -0.6 -0.3 Min Typ Max Units
0.0008 0.8 0.6 12 10 28 45 1 0.1 +20 0.1 +20 35 31 17 -100 -94 VS 0.8 50 30 20
% nV/Hz V p-p V mA % nA nA pC pF pF dB dB V V ms ms ms
-20 -20
VINH = 2.4 V VINL = 0.8 V VS ISY+ ISY- Single Supply Dual Supply All Channels On All Channels On All Channels On
+1000 nA +1000 nA +24 12 5 V V mA mA mA
NOTES 1 Turn-on time is measured from the time the logic input reaches the 50% point to the time the output reaches 50% of the final value. 2 Turn-off time is measured from the time the logic input reaches the 50% point to the time the output reaches 50% of the initial value. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
ORDERING GUIDE
Supply Voltage Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27 V Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5 V Analog Input Voltage (VA) . . . . . . . . . . . . . . . . . . . . . . . . . . VS Logic Input Voltage (VINL/INH) . . . . . . . . . . . . . . . . . . . . . . VS Maximum Current Through Any Switch . . . . . . . . . . . 20 mA Operating Temperature Range . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . +150C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300C Thermal Resistance1 20-Pin Plastic DIP (P): JA = 74, JC = 32 . . . . . . . . . C/W 20-Pin SOIC (S): JA = 90, JC = 27 . . . . . . . . . . . . . . C/W
NOTE 1 JA is specified for worst case mounting conditions, i.e., JA is specified for device in socket for P-DIP package.
Model SSM2404P SSM2404S
Operating Temperature Range -40C to +85C -40C to +85C
Package 20-Pin Plastic DIP 20-Pin SOIC
Package Option* N-20 R-20
*N = Plastic DIP, R = SOIC.
-2-
REV. B
SSM2404
VA (IN) = 50mVRMS f = 20Hz TO 100kHz VA (OUT) R L = 10k AND 100k
V (IN) A
50
OFF ISOLATION = 20 LOG
V (OUT) A V (IN) A
OFF Isolation Test Circuit
HIGH LOGIC INPUT LOW V (IN) A 1.4V
t r 100ns t f 100ns
1.4V
LOW
DC VOLTAGE CLOSED
Figure 2. Headroom (VS = 12 V, f = 1 kHz, with 80 kHz Filter)
V (OUT) A
OPEN
50%
50%
OPEN 1.0
t ON
t OFF
0.1
THD + N - %
tON/tOFF Timing Diagram
+12V V+ V (IN) A SWITCH CONROL V (OUT) A
0.01
0.001
GND
V- -12V
0.0001 100
1k 10k LOAD RESISTANCE -
100k
Test Circuit for tON/tOFF Timing Specification, tON/tOFF Switching Response, and ON/OFF Transition Photos
Figure 3. THD+N vs. Load (VS = 12 V, VA = 2 V rms, f = 1 kHz, with 80 kHz Filter)
0.01
THD + N - %
0.001
0.0001 0
4
8
12
Figure 1. THD+N vs. Frequency (VS = 12 V, VA = 2 V rms, with 80 kHz Filter)
SUPPLY VOLTAGE - V
Figure 4. THD+N vs. Supply Voltage (VA = 2 V rms, f = 1 kHz, RL = 100 k, with 80 kHz Filter)
REV. B
-3-
SSM2404
9.5
OUTPUT VOLTAGE SWING - VRMS
9.0 8.5 8.0 TA = 25C VS = 12V f = 20kHz
7.5 7.0 6.5
6.0 100
1k
10k
100k
LOAD RESISTANCE -
Figure 8. Output Voltage Swing vs. Load Resistance Figure 5. Frequency Response (VS = 12 V, VA = 1 V rms, RL = 100 k)
OUTPUT VOLTAGE SWING - VRMS
10 9 8 7 6 5 4 3 2 1 0 4 6 8 SUPPLY VOLTAGE - Volts 10 12 TA = 25C R L = 100k f = 20kHz 0.1% THD + N
CH A: 8.00V FS MKR: 0.11V/ Hz
1.00V/DIV
0Hz MKR: 20 000Hz
25kHz BW: 150Hz
Figure 6. SSM2404 Spectral Noise Density en [5 Devices (20 Switches) Chained Together]
Figure 9. Output Voltage Swing vs. Supply Voltage
-20 -30 -40 OFF ISOLATION - dB TA = 25C VS = 12V VA = 50mVRMS
10V
100
-50 R L = 100k -60 -70 -80 R L = 10k -90
0V
90
INPUT
0V
10 0%
OUTPUT
-100 -110 -120 10 100 1k FREQUENCY - Hz 10k 100k
10V
5s
Figure 7. Square Wave Response (TA = +25C, VS = 12 V, RL = 100 k, f = 20 kHz)
Figure 10. OFF-Isolation vs. Frequency
-4-
REV. B
SSM2404
0 -15 -30 TA = 25C VS = 12V VA = 50mVRMS
50
SWITCH LEAKAGE CURRENT - nA
40 30 VS = 12V VINL = 0.8V RL = -40C TO +85C
CROSSTALK - dB
-45 -60 -75 -90 R L = 10k R L = 100k
20 10
-105 -120 -135 -150 10 100 1k FREQUENCY - Hz 10k 100k
0 -10
-20 -10
-5
0
5
10
ANALOG INPUT VOLTAGE - Volts
Figure 11. Channel-to-Channel Crosstalk vs. Frequency (Worst Case Conditions, as Measured Between Switches 1 and 4, or 2 and 3)
Figure 14. Leakage Current vs. Analog Voltage
50 VS = 12V RL = IA = 10mA
SWITCHING TIME - ms
20 18 16 VS = 12V VA = 5V RL =
40
ON RESISTANCE -
+85C 30 +25C
14 12 10 8 6 TOFF 4 2 TON
20
-40C
10
0 -10
0 -5 5 ANALOG INPUT VOLTAGE - Volts
10
0 -40
-20
0
20 40 TEMPERATURE - C
60
80
100
Figure 12. ON Resistance vs. Analog Voltage
Figure 15. Switching Time vs. Temperature
90 80 TA = 25C VS = 12V RL = SUPPLY CURRENT - mA
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 I SY- IGND VS = 12V VA = GND VINH = 2.4V I SY+
SWITCH LEAKAGE CURRENT - mA
70 60 50 40 30 20 10 0
VIL = 0.8V
VIH = 2.4V
-10 -20 -15 -10 -5 0 5 ANALOG INPUT VOLTAGE - Volts 10 15
-20
0
20
40
60
80
100
TEMPERATURE - C
Figure 13. Overvoltage Characteristics
Figure 16. Supply Current vs. Temperature
REV. B
-5-
SSM2404
10V
100
5V 0
90
ANALOG OUTPUT VA (OUT)
SSM2404 can also be configured as a 4:1 multiplexer, or by using additional packages, as 8:1 or 16:1 and up. The breakbefore-make feature is guaranteed from part to part allowing such multiple-package applications. As Figure 20 shows, the SSM2404 is easy to use, and no additional devices are needed. The load resistors are recommended for improved OFF-isolation and charge injection. The ON resistance of the switch is only 28 typically, which causes very little signal attenuation even with a load resistor.
IN1 RL OUT1 DGND SW1 CONTROL 1 2 3 4 5 6 7 TOP VIEW (Not to Scale) SW1 20 SW4 19 RL 18 17 16 15 14 13 RL 9 SW2 SW3 12 11 R L IS OPTIONAL IN3 +12V SW4 CONTROL SW3 CONTROL -12V OUT3 SW SWITCH CONTROL STATE 0 1 OFF ON OUT4 IN4
5V 0
10 0%
LOGIC INPUT VINL/INH
5ms/div
Figure 17. tON/tOFF Switching Response
100 90
SSM2404
SW2 CONTROL
CLOSED (SWITCH ON) OPEN (SWITCH OFF)
OUT2 RL
8
10 0%
IN2
50mV 50s
10
Figure 18. Switch OFF-to-ON Transition (RL = 5 k)
Figure 20. Basic Circuit Configuration
OPTIMIZING PERFORMANCE
100 90
CLOSED (SWITCH ON) OPEN (SWITCH OFF)
50mV 50s
10 0%
As the performance curves show, the switch is optimized for high impedance loads. The distortion performance is at its best when the switch has a load impedance of 100 k or greater as shown in Figure 1. However, even at lower values of load resistances, the 1 kHz distortion performance is still excellent, 0.006% for a 10 k load. The main trade-off with THD is OFF-isolation and crosstalk. This is shown in Figures 10 and 11, again with two different load conditions. As these graphs show, the 10 k load yields approximately a 16 dB improvement in both characteristics. Thus, the optimum operating point depends on the most critical parameters. When THD is critical then high load impedances should be used; however, when crosstalk and OFFisolation are critical, lower impedances on the order of 10 k should be used. An additional benefit of using the smaller load resistor is that any charge injected onto the output will be shunted to ground through the resistor. If improved OFFisolation is needed, the SSM2404 dual audio switch should be considered with its excellent 120 dB OFF-isolation at 20 kHz. It is important that all of the AGND pins be connected to the system analog ground. These pins isolate the input and output of each switch. Without connecting these pins, the OFFisolation will degrade significantly.
Figure 19. Switch ON-to-OFF Transition (RL = 5 k)
APPLICATIONS INFORMATION
The SSM2404 integrates four analog CMOS switches with guaranteed "break-before-make" operation to provide high quality audio switching. Each switch has complementary N-channel and P-channel MOSFETs to allow the analog input voltage range to include the positive and negative rails and improve linearity. In addition, the topology permits fully bilateral switching. When using the SSM2404 there is full flexibility in configuring the switches. For example, they can be used individually as shown in Figure 20, or as a double-pole, double-throw (DPDT) switch, which is explained later. The
-6-
REV. B
SSM2404
DETAILED SWITCH OPERATION
A simplified circuit schematic with the functional sections is shown in Figure 21. The TTL interface has an internally regulated 5 V to ensure TTL logic levels regardless of the supply voltage. The logic threshold is with respect to the DGND pin, which can be offset. For example, if DGND is connected to the negative supply, then the SSM2404 will operate with negative rail logic. The interface shifts the control logic down to the negative supply and inverts it to drive N1.
V+
voltages of N4 and P4 are changing, the ON resistance of each switch is ramping from its OFF state to 28 and vice versa. The actual rise and fall times are shown in Figures 18 and 19 for a 5 k load. These times are significantly slower than typical switches, minimizing the SSM2404's charge injection and giving it "clickless" performance.
DOUBLE-POLE DOUBLE-THROW SWITCH
100nA P1
100nA
SW1 A BIAS P2 C1 15pF P3 N4 P4
-1 C2 15pF
SW CONTROL DGND
TTL INTERFACE N1 N2 N3
-1
The SSM2404 is ideal as a one-chip solution for a stereo switch. The schematic in Figure 22 shows the typical configuration. This circuit will select one of two stereo sources, channel A or B. The switch controls for the left and right input of each channel are tied together so that both will be turned on or off simultaneously. An inverter is inserted between the channel A and B controls so that only one logic signal is needed. The outputs can be configured many different ways, such as an inverting or noninverting amplifier stage, and the 10 k load resistors are added to improve the OFF-isolation. The performance of this stereo switch is equivalent to each individual switch, yielding a high quality audio switch that is virtually transparent to the signal.
V+
17
SW1 B V-
SSM2404
10 8
BREAK-BEFORE-MAKE
RAMP GENERATOR
Figure 21. Simplified Schematic
L INA
1
SW2
3
N1 in combination with C1 and the 100 nA current source provides the break-before-make operation of the switch. When the switch is on, N1 is off and C1 is charged up to the positive rail. However, when the SW CONTROL is turned off, then the gate of N1 is pulled high. This turns N1 on, providing a low impedance path to quickly discharge C1 to the negative rail, which quickly "breaks" the switch. On the other hand, when the SW CONTROL goes high again, the gate of N1 is pulled low, turning it off. This leaves C1 to be slowly charged up to the positive rail by the 100 nA current source. The difference in the discharge and charging times ensures break-before-make operation, even from device to device. The voltage on C1 is inverted by P1 to drive the ramp generator differential pair, consisting of P2, P3 and N2, N3. This differential pair steers the 100 nA of tail current to either charge or discharge C2. As discussed above, when the switch is on, C1 is charged up to the positive rail. P1 inverts this, putting a low voltage equivalent to the negative supply on the gate of P2. The BIAS voltage is approximately equal to the midpoint of the two supply voltages. Thus, when P2 is pulled down, it is turned on and P3 is off. All of the 100 nA flows through N2 and is mirrored by N3. Thus, the 100 nA discharges C2 through N3. When C2 is pulled low, the inverter turns N4 on by pulling its gate high, and the second inverter turns P4 on. To turn the switch off the gate of P2 is pulled above the BIAS so that all 100 nA charges C2 through P3. This is then inverted to turn off N4 and P4. The internal ramp has rise and fall times on the order of a few milliseconds which is sped up by the inverters. As the gate
L INB
6
SW1 SW2 CONTROL SW3 CONTROL DGND SW1 CONTROL SW4 CONTROL
13 12 19
L OUT 10k
AGND
2 9
SWA/SWB
15 4 5 16 11
SWA/SWB 0 1
CHANNEL SELECTED B A
R INA
20
SW3
18
R INB
SW4
14
R OUT 10k
V-
Figure 22. Double-Pole, Double-Throw Stereo Switch
VIRTUAL GROUND SWITCHING
The SSM2404 was built on a CMOS process with a 24 V operating limit for the total supply voltage across the part. This leads to a corresponding limit on the analog voltage range. However, to achieve larger signal swings, the SSM2404 should be configured in the virtual ground mode. As shown in Figure 23, the output of the SSM2404 is connected to the inverting input of an amplifier. Since the noninverting input is grounded, the SSM2404 will also be biased at ground, and large voltage swings on the circuit's input will not significantly change the voltage on the switch. The only limitation is that the current through the switch needs to be less than 10 mA, and the voltage range is limited only by the op amp and its supply voltages.
REV. B
-7-
SSM2404
The circuit was tested with an SSM2131 high slew rate audio amplifier and the results are shown in Figures 24 and 25. This configuration yields excellent THD performance that is primarily determined by the amplifier. Also, the headroom is now +24 dBu (0 dBu = 0.775 V rms), which is due to the amplifier's output voltage swing. Thus, even though the SSM2404 has a 12 V limitation on its supplies, it can be used in systems with much higher voltage ranges. For example, the double-pole double-throw switch from Figure 22 can be reconfigured in the virtual ground mode to allow higher voltage swings, as shown in Figure 26. This application realizes the excellent performance of Figures 24 and 25 while providing a low cost switching solution.
+12V R2 5k +18V 3
5k RINB
20 18
V+
17
SSM2404
5k LINA 5k LINB
10 8
SW2
1 3
5k
SW1
6
LOUT SSM2131
SWA/SWB
SW2 CONTROL AGND SW3 CONTROL DGND SW1 CONTROL SW4 CONTROL
2 9 12 19
15 4 5 16
5k RINA
11
13
SW3 5k
SSM2404
AUDIO IN 1N914 R1 5k 1 SW1 A SW1 B
SSM2131
AUDIO OUT
SW4
14
ROUT SSM2131
V-
-12V
-18V
Figure 23. Virtual Ground Switching
Figure 26. Double-Pole, Double-Throw Stereo Switch Using Virtual Ground Operation
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Mini-DIP (P Suffix)
20 PIN 1 1 1.060 (26.90) 0.925 (23.50) 0.210 (5.33) MAX 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 10 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 11 0.280 (7.11) 0.240 (6.10)
0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.070 (1.77) 0.045 (1.15)
Figure 24. Virtual Ground Switch THD+N vs. Frequency (VS = 12 V, VA = 2 V rms, with 80 kHz Filter)
SEATING PLANE
SOIC (S Suffix)
0.5118 (13.00) 0.4961 (12.60)
20
11
0.2992 (7.60) 0.2914 (7.40) PIN 1 0.4193 (10.65) 0.3937 (10.00)
1 10
0.0500 (1.27) BSC
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) X 45 0.0098 (0.25) 0- 8
Figure 25. Virtual Ground Switch Headroom (VS = 12 V for SSM2404; VS = 18 V for Op Amp, f = 1 kHz, with 80 kHz Filter)
0.0118 (0.30) 0.0040 (0.10)
0.0192 (0.49) 0.0138 (0.35)
0.0125 (0.32) 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
-8-
REV. B
PRINTED IN U.S.A.
C1626-20-1/92

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