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ST-BUSTM FAMILY MH89790B CEPT PCM 30/CRC-4 Framer & Interface Preliminary Information
Features
* * * * * * * * * * * * * * * Complete primary rate 2048 kbit/s CEPT transceiver with CRC-4 option Selectable HDB3 or AMI line code Two frame elastic buffer with 32s jitter buffer Tx and Rx frame and multiframe synchroniza-tion signals Frame alignment and CRC error counters Insertion and detection of A, B, C, D signalling bits with optional debounce Line driver and receiver Per channel, overall, and remote loop around Digital phase detector between E1 line and ST-BUS ST-BUS compatible Pin compatible with the MH89790 Inductorless clock recovery Loss of Signal (LOS) indication Available in standard, narrow and surface mount formats Supports single supply rail operation
MH89790B MH89790BN MH89790BS
ISSUE 5
May 1995
Ordering Information
40 Pin DIL Hybrid 1.3" row pitch 40 Pin DIL Hybrid 0.8" row pitch 40 Pin Surface Mount Hybrid
0C to 70C
Description
The MH89790B is Mitel's CEPT PCM 30 interface solution, designed to meet the latest CCITT standards PCM 30 format with CRC-4. The MH89790B provides a complete interface between a 2.048 Mbit/sec digital trunk and Mitel's Serial Telecom Bus, the ST-BUS. The MH89790B is a pin-compatible enhancement of the MH89790, permitting the removal of the tuneable inductor and inclusion of the external NAND gate used for generating RxD.
Applications
* * * Primary rate ISDN network nodes Multiplexing equipment Private network: PBX to PBX links
TxMF C2i F0i RxMF DSTo DSTi CSTi0 CSTi1 CSTo
ST-BUS Timing Cicuitry Digital Attenuator ROM
2 Frame Elastic Buffer with Slip Control
PADi TxG PADo CEPT Link Interface Transmitter OUTA OUTB RxA RxT Receiver LOS RxR RxB
Data Interface
* *
Serial Control Interface ABCD Signalling RAM Control Logic Phase Detector
*
Clock Extractor CEPT Counter
*
E2o
VDD ADl XCtl XSt
*
E8Ko VSS
Figure 1 - Functional Block Diagram
4-187
MH89790B
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC NC LOS NC NC NC NC VSS NC DSTo NC OUTB NC RxMF TxMF OUTA PADo TxG PADi VSS
Preliminary Information
IC E2o VDD RxA RxT RxR RxB NC CSTi1 CSTi0 E8Ko XCtl XSt CSTo ADl DSTi C2i E2o F0i
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Figure 2 - Pin Connections
Pin Description
Pin # 2 3 4 5 6 7 Name IC E2o VDD RxA RxT RxR Description Internal Connection. Leave open circuit. 2048 kHz Extracted Clock (Output): This clock is extracted by the device from the received signal. It is used internally to clock in data received at RxT and RxR. D.C. Power Input. (+5V). Receive A (Output): The bipolar CEPT signal received by the device at the RxR and RxT inputs is converted to a unipolar format and output at this pin. Receive Tip and Receive Ring Inputs. The AMI receive signal is input to these pins. Both inputs should be connected to a center-tapped, center-grounded transformer.If the receive side of the device is not used, these pins must be tied to ground through 1k resistors. Receive B (Output): The bipolar CEPT signal received by the device at the RxR and RxT inputs is converted to a unipolar format and output at this pin. No Connection. Control ST-BUS Input #1: A 2048 kbit/s stream that contains channel associated signalling, frame alignment and diagnostic functions. Control ST-BUS Input #0: A 2048 kbit/s stream that contains 30 per channel control words and two Master Control Words. 8 kHz Extracted Clock (Output): An 8 kHz output generated by dividing the extracted 2048 kHz clock by 256 and aligning it with the received CEPT frame. The 8 kHz signal can be used for synchronizing the system clock to the extracted 2048 kHz clock. Only valid when device achieves synchronization (goes low during a loss of signal or a loss of basic frame synchronization condition). E8Ko goes to high impedance when 8kHzSEL = 0 in MCW2. External Control (Output): An uncommitted external output pin which is set or reset via bit 1 in Master Control Word 2 on CSTi0. The state of XCtl is updated once per frame. External Status: The state of this pin is sampled once per frame and the status is reported in bit 1 of the Master Status Word 1 on CSTo. Control ST-BUS Output: A 2048 kbit/s serial control stream which provides the 16 signalling words, two Master Status Words, Phase Status Word and CRC Error Count.
8 9 10 11 12
RxB NC CSTi1 CSTi0 E8Ko
13 14 15
XCtl XSt CSTo
4-188
Preliminary Information
Pin Description (Continued)
Pin # 16 Name ADI Description
MH89790B
Alternate Digit Inversion (Input): If this input is high, the CEPT timeslots which are specified on CSTi0 as voice channels are ADI coded and decoded. When this bit is low it disables ADI coding for all channels. This feature allows either ADI or non-ADI codecs to be used on DSTi and DSTo. Internally pulled with a 4.7k resistor to +VDD. Data ST-BUS Input: This pin accepts a 2048 kbit/s serial stream which contains the 30 PCM or data channels to be transmitted on the CEPT trunk. 2048 kbit/s System Clock (Input): The master clock for the ST-BUS section of the chip. All data on the ST-BUS is clocked in on the falling edge of the C2i and output on the rising edge. The falling edge of C2i is also used to clock out data on the CEPT PCM 30 transmit link. 2048 kHz Extracted Clock (Output): Internally connected to pin 3. Frame Pulse Input: The ST-BUS frame synchronization signal which defines the beginning of the 32 channel frame. Ground. D.C. Power Return. PAD Input: Input to the symmetrical resistive 75 ohm T-type line matching circuit. In a typical application connect this input to the output of the line driving transformer. Transmit Ground: Common point of the T-type PAD circuit. Connect to GND in a typical application. PAD Output: Output from the T-type PAD circuit. Output impedance of the PAD is pure resistive 75. Output A (Open Collector Output): This is the output of the CEPT transmitter. It is suitable for use with an external pulse transformer to generate the transmit bipolar line signal. Transmit Multiframe Boundary (Input): This input can be used to set the channel associated and CRC transmitted multiframe boundary (clear the frame counters). If a transmit multiframe signal is not being generated externally to the device, the MH89790B will internally generate its own multiframe when this pin is tied high. Received Multiframe Boundary (Output): An output pulse delimiting the received multiframe boundary. (This multiframe is not related to the received CRC multiframe.) No Connection. Output B (Open Collector Output): Output of the CEPT transmitter. It is suitable for use with an external pulse transformer to generate the transmit bipolar line signal. No Connection. Data ST-BUS Output: A 2048 kbit/s serial output stream which contains the 30 PCM or data channels received from the CEPT line. No Connection. Ground. D.C. Power Return. No Connection. Loss of Signal (Output): This pin goes High when 128 contiguous ZEROs are received on the RxT and RxR inputs. When LOS is High, RxA and RxB are forced High. LOS is reset when 64 ONEs are received in a two E1-frame period. No Connection.
17 18
DSTi C2i
19 20 21 22 23 24 25
E2o F0i VSS PADi TxG PADo OUTA
26
TxMF
27 28 29 30 31 32 33 34 - 37 38
RxMF NC OUTB NC DSTo NC VSS NC LOS
39 - 40
NC
4-189
MH89790B
Functional Description
The MH89790B is a digital trunk interface conforming to CCITT Recommendation G.704 for PCM 30 and I.431 for ISDN. It includes features such as insertion and detection of synchronization patterns, optional cyclical redundancy check (CRC-4) and far end error performance reporting, HDB3 decoding and optional coding, channel associated or common channel signalling, programmable digital attenuation, and a two frame received elastic buffer. The MH89790B can also monitor several conditions on the CEPT digital trunk which include the following: Loss of Signal (LOS) indication, frame and multiframe synchronization, received all 1's alarms, data slips, as well as near and far end framing and CRC errors. The system interface to the MH89790B is a serial bus that operates at 2048 kbit/s known as the ST-BUS. This serial stream is divided into 125 s frames that are made up of 32 x 8 bit channels. The line interface to the MH89790B consists of split phase unipolar inputs and outputs which are supplied from/to a bipolar line receiver/driver, respectively.
Preliminary Information
mode. This allows use of timeslot 16 for 64 kbit/s common channel signalling. Synchronization is included within the CEPT bit stream in the form of a bit pattern inserted into timeslot 0. The contents of timeslot 0 alternate between the frame alignment pattern and the non-frame alignment pattern as described in Figure 3 below. Bit 1 of the frame alignment and non-frame alignment bytes have provisions for additional protection against false synchronization or enhanced error monitoring. This is described in more detail in the following section. In order to accomplish multiframe synchronization, a 16 frame multiframe is defined by sending four zeros in the high order quartet of timeslot 16 frame 0, i.e., once every 16 frames (see Figure 4). The CEPT format has four signalling bits, A, B, C and D. Signalling bits for all 30 information channels are transmitted in timeslot 16 of frames 1 to 15. These timeslots are subdivided into two quartets (see Table 6). Cyclic Redundancy Check (CRC) An optional cyclic redundancy check (CRC) has been incorporated within CEPT bit stream to provide additional protection against simulation of the frame alignment signal, and/or where there is a need for an enhanced error monitoring capability. The CRC process treats the binary string of ones and zeros contained in a submultiframe (with CRC bits set to binary zero) as a single long binary number. This string of data is first multiplied by x4 then divided by the polynomial x 4+x+1. This process takes place at both the transmitter and receiver end of the link. The remainder calculated at the receiver is compared to the one received with the data over the link. If they Bit Number 1 2
0
CEPT Interface
The CEPT frame format consists of 32, 8 bit timeslots. Of the 32 timeslots in a frame, 30 are defined as information channels, timeslots 1-15 and 17-31 which correspond to telephone channels 1-30. An additional data channel may be obtained by placing the device in common channel signalling
3
0
4
1
5
1
6
0
7
1
8
1
Timeslot 0 containing the frame alignment signal Timeslot 0 containing the non-frame alignment signal
Reserved for International use (1) Reserved for International use (2)
1
Alarm indication to the remote PCM multiplex equipment
See Note #3
See Note #3
See Note #3
See Note #3
See Note #3
Figure 3 - Allocation of Bits in Timeslot 0 of the CEPT Link
Note 1 : With CRC active, this bit is ignored. Note 2 : With SiMUX active, this bit transmits SMF CRC results in frames 13 and 15. Note 3 : Reserved for National use.
.
Timeslot 16 of frame 0
Timeslot 16 of frame 1
ABCD bits for telephone channel 1 (timeslot 1) ABCD bits for telephone channel 16 (timeslot 17)
Timeslot 16 of frame 15
***
0000
XYXX
ABCD bits for telephone channel 15 (timeslot 15)
ABCD bits for telephone channel 30 (timeslot 31)
Figure 4 - Allocation of Bits in Timeslot 16 of the CEPT Link
4-190
Preliminary Information
are the same, it is of high probability that the previous submultiframe was received error free. The CRC procedure is based on a 16 frame multiframe which is divided into two 8 frame submultiframes (SMF). The frames which contain the frame alignment pattern contain the CRC bits, C1 to C 4, respectively, in the bit 1 position. The frame which contains the non-frame alignment pattern contains within the bit 1 position, a 6 bit CRC multiframe alignment signal and two spare bits (in frames 13 and 15) which are used for CRC error performance reporting (refer to Figure 5). During the CRC encoding procedure the CRC bit positions are initially set at zero. The remainder of the calculation is stored and inserted into the respective CRC bits of the next SMF. The decoding process repeats the multiplication/division process and compares the remainder with the CRC bits received in the next SMF. The two spare bits (denoted Si1 and Si2 in Figure 5) following the 6-bit CRC multiframe alignment signal can be used to monitor far-end error performance. The results of the CRC-4 comparisons for the previously received SMFII and SMFI are encoded and transmitted back to the far end in the Si bits (refer to Table 1).
MH89790B
ST-BUS Interface
The ST-BUS is a synchronous time division multiplexed serial bus with data streams operating at 2048 kbit/s and configured as 32, 64 kbit/s channels (refer Figure 6). Synchronization of the data transfer is provided from a frame pulse which identifies the frame boundaries and repeats at an 8 kHz rate. Figure 2 shows how the frame pulse (F0i) defines the ST-BUS frame boundaries. All data is clocked into the device on the falling edge of the 2048 kbit/s clock (C2i), while data is clocked out on the rising edge of the 2048 kbit/s clock at the start of the bit cell. Si1 bit (frame 13) 1 1 0 0 Si2 bit (frame 15) 1 0 1 0
Meaning
CRC results for both SMFI, II are error free. CRC result for SMFII is in error. CRC result for SMFI is error free. CRC result for SMFII is error free. CRC result for SMFI is in error. CRC results for both SMFI, II are in error.
Table 1. Coding of Spare Bits Si1 and Si2
Multiple Frame Component
Frame Type
Frame Alignment Signal Non-Frame Alignment Signal
CRC Frame #
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Timeslot Zero 1
C1 0 C2 0 C3 1 C4 0 C1 1 C2 1 C3 Si1
(3)
2
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
3
0 A(1) 0 A(1) 0 A(1) 0 A(1) 0 A(1) 0 A(1) 0 A(1) 0 A(1)
4
1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2)
5
1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2)
6
0 Sn(2) 0 Sn(2) 0 Sn(2) 0 Sn(2) 0 Sn(2) 0 Sn(2) 0 Sn(2) 0 Sn(2)
7
1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2)
8
1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2) 1 Sn(2)
S M F I
Frame Alignment Signal Non-Frame Alignment Signal Frame Alignment Signal Non-Frame Alignment Signal Frame Alignment Signal Non-Frame Alignment Signal Frame Alignment Signal
S M F I I
Non-Frame Alignment Signal Frame Alignment Signal Non-Frame Alignment Signal Frame Alignment Signal Non-Frame Alignment Signal Frame Alignment Signal Non-Frame Alignment Signal
C4 Si2(3)
Figure 5 - CRC Bit Allocation and Submultiframing
Note 1 : Remote Alarm. Keep at 0 for normal operation. Note 2 : Reserved for National use. Keep at 1 for normal operation. Note 3 : Used to monitor far-end CRC error performance. indicates position of CRC-4 multiframe alignment signal
4-191
MH89790B
125s CHANNEL 31 CHANNEL 0
Preliminary Information
***
BIT 7 BIT 6 BIT 5 BIT 4
CHANNEL 30
CHANNEL 31
CHANNEL 0
Most Significant Bit (First)
BIT 3
BIT 2
BIT 1
BIT 0
Least Significant Bit (Last)
(8/2.048)s
Figure 6 - ST-BUS Stream Format Data Input (DSTi) The MH89790B receives information channels on the DSTi pin. Of the 32 available channels on this serial input, 30 are defined as information channels. They are channels 1-15 and 17-31. These 30 timeslots are the 30 telephone channels of the CEPT format numbered 1-15 and 16-30. Timeslot 0 and 16 are unused to allow the synchronization and signalling information to be inserted, from the Control Streams (CSTi0 and CSTi1). The relationship between the input and output ST-BUS stream and the CEPT line is illustrated in Figures 7 to 11. In common channel signalling mode timeslot 16 becomes an active channel. In this mode channel 16 on DSTi is transmitted on timeslot 16 of the CEPT link unaltered. This mode is activated by bit 5 of channel 31 of CSTi0. Control Input 0 (CSTi0) All the necessary control and signalling information is input through the two control streams. Control ST-BUS input number 0 (CSTi0) contains the control information that is associated with each information channel. Each control channel contains the per channel digital attenuation information, the individual
BIT
7
NAME
DATA
DESCRIPTION
Data Channel: If `1`, then the controlled timeslot on the CEPT 2048 kbit/s link is treated as a data channel; i.e., no ADI encoding or decoding is performed on transmission or reception, and digital attenuation is disabled. If `0`, then the state of the ADI pin determines whether or not ADI encoding and decoding is performed. Per-Channel Loopback: If `1`, then the controlled timeslot on the transmitted CEPT 2048 kbit/s link is looped internally to replace the data on the corresponding received timeslot. If `0`, then this function is disabled. This function only operates if frame synchronization is received from the CEPT link. If more than one channel is looped per frame only the first one will be active. Receive Attenuation Pad: Per timeslot receive attenuation control bits. RXPAD4 RXPAD2 RXPAD1 Gain (dB) 0 0 0 0 0 0 1 -1 0 1 0 -2 0 1 1 -3 1 0 0 -4 1 0 1 -5 1 1 0 -6 1 1 1 1 Transmit Attenuation Pad: Per timeslot transmit attenuation control bits. TXPAD4 TXPAD2 TXPAD1 Gain (dB) 0 0 0 0 -1 0 0 0 -2 0 1 1 -3 0 1 0 -4 1 0 1 -5 1 0 0 -6 1 1 1 1 1 1 0
6
LOOP
5,4,3
RXPAD4,2,1
2,1,0
TXPAD4,2,1
Table 2. Per Channel Control Word: Data Format for CSTi0 Channels 0-14, and 16-30
4-192
DSTi Channel # 5 5
CCS
0 6 7 8 9 10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30 30
31 31
CEPT Timeslot #
1
2
3
4
Figure 7 - Relationship between Input DSTi Channels and Transmitted CEPT Timeslots
5 5
SIG
DSTi Channel # 6 6 7 8 9 10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
0
1
2
3
4
27 27
28 28
29 29
30 30
31 31
Preliminary Information
CEPT Timeslot #
0
1
2
3
4
Figure 8 - Relationship between Received CEPT Timeslots and Output DSTo Channels
4 C1 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 C2
CSTi0 Channel #
0
1
2
3
Device Control
CEPT Channel # Control Word
1
2
3
4
Figure 9 - Relationship between Input CSTi0 Channels and Controlled CEPT Timeslots
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 C3 5 16 6 16 7 16 8 16 9 16 10 16 11 16 12 16 13 16 14 16 15 16 A 0 N 0 19 * 20 * 21 * 22 * 23 * 24 * 25 * 26 * 27 * 28 * 29 * 30 * 31 *
CSTi1 Channel # Device Control CEPT FRAME # CHANNEL #
0
1
2
3
0 16
1 16
2 16
3 16
4 16
Figure 10 - Relationship between Input CSTi1 Channels and Transmitted CEPT Frames
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 S1 5 16 6 16 7 16 8 16 9 16 10 16 11 16 12 16 13 16 14 16 15 16 A 0 N 0 19 S2 20 S3 21 S4 22 * 23 * 24 * 25 * 26 * 27 * 28 * 29 * 30 * 31 *
CSTo Channel #
0
1
2
3
Device Status
CEPT FRAME # TIMESLOT #
0 16
1 16
2 16
3 16
4 16
Figure 11- Relationship between Received CEPT Frames and Output CSTo Channels
-CCS Denotes Signalling Channel if Common Channel Signalling Mode Selected -S1 Denotes Master Status Word 1 (MSW1) -S2 Denotes Phase Status Word (PSW) -S3 Denotes CRC Error Count -S4 Denotes Master Status Word 2 (MSW2)
MH89790B
-
*Denotes Unused Channel (CSTo output is not put in high impedance state) A Denotes Frame-Alignment Frame N Denotes Non Frame-Alignment Frame C1, C2, C3 Denotes Master Control Words 1,2,3 SIG Denotes Signalling Channel
4-193
MH89790B
BIT
7 6
Preliminary Information
NAME
(N/A) LOOP16 Keep at `1` for normal operation.
DESCRIPTION
Channel 16 Loopback: If `1`, then timeslot 16 on the transmitted CEPT 2048 kbit/s link is looped internally to replace the data received on timeslot 16. If `0,` then this function is disabled. This function only operates if frame synchronization is received from the CEPT link and only a single timeslot can be looped within the frame. Keep at `1` for normal operation. Signalling Bit Debounce: If `1`, then no debouncing is applied to the received A, B, C or D signalling bits. If `0`, then the received A, B, C or D signalling bits are debounced for between 6 and 8 ms.
5,4 3,2, 1 &0
(N/A) NDBD, NDBC, NDBB & NDBA
Table 3. Master Control Word 1 (MCW1): Data Format for CSTi0 Channel 15 BIT
7 6 5
NAME
(N/A) (N/A) CCS Keep at `1` for normal operation. Keep at `0` for normal operation.
DESCRIPTION
Common Channel Signalling: If 1, then the MH89790B operates in its common channel signalling mode. Channel 16 on the DSTi pin is transmitted on timeslot 16 of the CEPT link, and timeslot 16 from the received CEPT link is output on channel 16 on the DSTo pin. Channel 15 on the CSTi0 pin contains the information for the control of timeslot 16. Channels 0 to 15 on CSTi1 and CSTo are unused. If `0`, the device is in channel associated signalling mode where channel 16 is used to transmit the ABCD signalling bits. 8kHz Select: If `1`, then an 8 kHz signal synchronized to the received CEPT 2048 kbit/s link is output on the E8Ko pin. This feature is only valid when frame synchronization is received from the CEPT link. If `0`, then the E8Ko pin goes into its high impedance state. Transmit Alarm Indication Signal: If `1`, then an all 1' s alarm signal is transmitted on all timeslots. If `0`, then the timeslots functions normally. Transmit Timeslot 16 Alarm Indication Signal: If `1`, then an all 1's alarm signal is transmitted on timeslot 16. If `0`, then timeslot 16 functions normally. External Control: If `1`, then the XCtl pin is driven high. If `0`, then the XCtl pin is driven low. (unused)
4
8kHzSEL
3
TXAIS
2
TXTS16AIS
1
XCtl
0
(N/A)
Table 4. Master Control Word 2 (MCW2): Data Format for CSTi0 Channel 31 BIT
7-4
NAME
MA1-4
DESCRIPTION
Transmit Multiframe Alignment Bits 1 to 4: These bits are transmitted on the CEPT 2048 kbit/s link in bit positions 1 to 4 of timeslot 16 of frame 0 of the multiframe. They should be kept at `0` to allow multiframe alignment to be detected. This bit is transmitted on the CEPT 2048 kbit/s link in bit position 5 of timeslot 16 of frame 0 of the multiframe. It is a spare bit which should be kept at `1` if unused. This bit is transmitted on the CEPT 2048 kbit/s link in bit position 6 of timeslot 16 of frame 0 of the multiframe. It is used to indicate the loss of multiframe alignment to the remote end of the link. A `1` on this bit is the signal that multiframe alignment on the received link has been lost. A `0' indicates that multiframe alignment is detected. These bits are transmitted on the CEPT 2048 kbit/s link in bit positions 7 and 8 respectively, of timeslot 16 of frame 0 of the multiframe. They are spare bits which should be kept at `1` if unused.
3 2
X1 Y
1,0
X2,X3
Table 5. Multiframe Alignment Signal:Data Format for CSTi1Channel 0 on the Transmitted CEPT Link
4-194
Preliminary Information
loopback control bit, and the voice or data channel identifier, see Table 2. When a channel is in data mode (B7 is high) the digital attenuation and Alternate Digit Inversion are disabled. It should be noted that the control word for a given information channel is input one timeslot early, i.e., channel 0 of CSTi0 controls channel 1 of DSTi. Channels 15 and
MH89790B
31 of CSTi0 contain Master Control Words 1 and 2 (MCW1, MCW2) which are used to set up the interface feature as seen by the respective bit functions of Tables 3 and 4.
BIT
7, 6, 5 &4
NAME
A(N), B(N), C(N) & D(N)
DESCRIPTION
Transmit Signalling Bits for Channel N: These bits are transmitted on the CEPT 2048 kbit/s link in bit positions 1 to 4 of timeslot 16 in frame N, and are the A, B, C and D signalling bits associated with telephone channel N. The value of N lies in the range 1 to 15 and refers to the channel on the CSTi1 channel from which the bits are sourced, the telephone channel with which the bits are associated and the frame on the CEPT link on which the bits are transmitted. For example, the bits input on the CSTi1 pin on channel 3 are associated with telephone channel 3, which is timeslot 3 of the CEPT link, and are transmitted on bits positions 1 to 4 of timeslot 16 in frame 3 of each multiframe on the CEPT link . If bits B, C or D are not used they should be given the values `1, 0` and `1` respectively. The combination `0000` for ABCD bits should not be used for telephone channels 1 to 15 as this would interfere with multiframe alignment. Transmit Signalling Bits for Channel N+15: These bits are transmitted on the CEPT 2048 kbit/s link in bit positions 5 to 8 of timeslot 16 in frame N, and are the A, B, C and D signalling bits associated with telephone channel N+15. The value of N lies in the range 1 to 15 and refers to both the channel on the CSTi1 stream where the bits are supplied and the frame on the CEPT link on which the bits are transmitted, and indirectly indicates the telephone channel with which the bits are are associated. For example, the bits input on the CSTi1 pin on channel 3 are associated with telephone channel 18, which is timeslot 19 of the CEPT link, and are transmitted in bits positions 5 to 8 of timeslot 16 in frame 3 of each multiframe on the CEPT link .
3, 2, 1 &0
A(N+15), B(N+15), C(N+15) & D(N+15)
Table 6. Channel Associated Signalling: Data Format for CSTi1 Channels 1 to 15 BIT
7
NAME
IU0
DESCRIPTION
International Use 0: When CRC is disabled, this bit is transmitted on the CEPT 2048 kbit/s link in bit position 1 of timeslot 0 of frame-alignment frames . It is reserved for international use and should be kept at `1' when not used. If CRC is enabled, this bit is not used. Transmit Frame Alignment Signal Bits 2 to 8: These bits are transmitted on the CEPT 2048 kbit/s link in bit positions 2 to 8 of timeslot 0 of frame-alignment frames. These bits form the frame alignment signal and should be set to `0011011`.
6-0
FAF2-8
Table 7. Frame-Alignment Signal: Data Format for CSTi1 Channel 16 BIT
7
NAME
IU1
DESCRIPTION
International Use 1: When the CRC is disabled and SiMUX bit in MCW3 is disabled, this bit is transmitted on the CEPT 2048 kbit/s link in bit position 1 of timeslot 0 of non-frame-alignment frames . It is reserved for international use and should be kept at `1` when not used. If CRC is enabled and SiMUX is disabled, this bit is transmitted in bit 1 of timeslot 0 for frame 13 and 15. If both CRC and SiMUX are enabled, then this bit is not used. Transmit Non-Frame Alignment Bit: This bit is transmitted on the CEPT 2048 kbit/s link in bit position 2 of timeslot 0 of non-frame-alignment frames . In order to differentiate between frame-alignment frames and non-frame-alignment frames, this bit should be kept at `1`. Non-Frame Alignment Alarm: This bit is transmitted on the CEPT 2048 kbit/s link in bit position 3 of timeslot 0 of non-frame-alignment frames . It is used to signal an alarm to the remote end of the CEPT link. The bit should be set to `1` to signal an alarm and should be kept at `0` under normal operation. National Use: These bits are transmitted on the CEPT 2048 kbit/s link in bit positions 4 to 8 of timeslot 0 of non-frame-alignment frames . These bits are reserved for national use, and on crossing international borders they should be set to `1`.
6
NFAF
5
ALM
4-0
NU1-5
Table 8. Non-Frame-Alignment Signal: Data Format for CSTi1 Channel 17
4-195
MH89790B
BIT
7 6
Preliminary Information
NAME
N/A SiMUX Keep at zero for normal operation.
DESCRIPTION
When set to `1', this bit will cause the SMFI CRC result to be transmitted in the next outgoing Si1 bit in frame 13 and the SMFII CRC result to be transmitted in the next outgoing Si2 bit in frame 15. Remote Loopback: respectively. If set the RxT and RxR signals are looped to OUTA and OUTB,
5 4 3
RMLOOP HDB3en Maint
Enable HDB3 Encoding: A '1' will disable the HDB3 line coding and transmit the information transparently. Maintenance: A '1' will force a complete reframe if the CRC multiframe synchro- nization is not achieved within 8 ms of frame synchronization. Reframe will also be generated if more than 914 CRC errors occur within a one second interval (CRC error counter is reset with every one second interval). A '0' will disable this option. Enable Cyclical Redundancy Check: A '1' will enable the CRC generation on the transmit data. A '0' will disable the CRC generator. The CRC receiver is always active regardless of the state of CRCen. Digital Loopack: When set, the transmitted signal is looped around from DSTi to DSTo. The normal received data is interrupted. Force Reframe: If set, for at least one frame, and then cleared the chip will begin to search for a new frame position when the chip detects the change in state from high to low. Only the change from high to low will cause a reframe, not a continuous low level.
2
CRCen
1 0
DGLOOP ReFR
Table 9. Master Control Word 3 (MCW3): Data Format for CSTi1 Channel 18 BIT
7-4
NAME
MA1-4
DESCRIPTION
Receive Multiframe Alignment Bits 1 to 4: These are the bits which are received from the CEPT 2048 kbit/s link in bit positions 1 to 4 of timeslot 16 of frame 0 of the multiframe. They should all be `0`. This is the bit which is received on the CEPT 2048 kbit/s link in bit position 5 of timeslot 16 of frame 0 of the multiframe. It is a spare bit which should be `1` if unused. It is not debounced. This is the bit which is received on the CEPT 2048 kbit/s link in bit position 6 of timeslot 16 of frame 0 of the multiframe. It is used to indicate the loss of multiframe alignment at the remote end of the link. A `1` on this bit is the signal that multiframe alignment at the remote end of the link has been lost. A `0` indicates that multiframe alignment is detected. It is not debounced. These are the bits which are received on the CEPT 2048 kbit/s link in bit positions 7 and 8 respectively, of timeslot 16 of frame 0 of the multiframe. They are spare bits which should be `1` if unused. They are not debounced.
3 2
X1 Y
1,0
X2,X3
Table 10. Received Multiframe Alignment Signal: Data Format for CSTo Channel 0 Control Input 1 (CSTi1) Control ST-BUS input stream number 1 (CSTi1) contains the synchronization information and the A, B, C & D signalling bits for insertion into timeslot 16 of the CEPT stream (refer to Tables 5 to 8). Timeslot 0 contains the four zeros of the multiframe alignment signal plus the XYXX bits (see Figure 4). Channels 1 to 15 of CSTi1 contain the A, B, C & D signalling bits as defined by the CEPT format (see Figure 4), i.e., channel 1 of CSTi1 contains the A, B, C & D bits for DSTi timeslots 1 and 17. Channel 16 contains the frame alignment signal, and channel 17 contains the non-frame alignment signal (see Figure 3). Channel 18 contains the Master Control Word 3 (see Table 9).
4-196
Figure 10 shows the relationship between the control stream (CSTi1) and the CEPT stream. Control Output (CSTo) Control ST-BUS output (CSTo) contains the multiframe signal from timeslot 16 of frame 0 (see Table 10). Signalling bits, A, B, C & D for each CEPT channel are sourced from timeslot 16 of frames 1-15 and are output in channels 1-15 on CSTo , as shown in Table 11. The frame alignment signal and non-frame alignment signal, received from timeslot 0 of alternate frames are output in timeslots 16 and 17, as shown in Tables 12 and 13.
Preliminary Information
MH89790B
DESCRIPTION
BIT
7, 6, 5 &4
NAME
A(N), B(N), C(N) & D(N)
Receive Signalling Bits for Channel N: These are the bits which are received from the CEPT 2048 kbit/s link in bit positions 1 to 4 of timeslot 16 in frame N (frame #), and are the A, B, C and D signalling bits associated with telephone channel N. The value of N lies in the range 1 to 15 and refers to the channel on the CSTo stream on which the bits are output, the telephone channel with which the bits are associated and the frame on the CEPT link on which the bits are received. For example, the bits output on the CSTo stream on channel 3 are associated with telephone channel 3, which is timeslot 3 of the CEPT link, and are received on bits positions 1 to 4 of timeslot 16 in frame 3 of each multiframe on the CEPT link . If bits B, C or D are not used they should have the values `1, 0` and `1', respectively. The combination `0000` for ABCD bits should not be found for telephone channels 1 to 15 as this implies interference with multiframe alignment. Receive Signalling Bits for Channel N+ 15: These are the bits which are received from the CEPT 2048 kbit/s link in bit positions 5 to 8 of timeslot 16 in frame N, and are the A, B, C and D signalling bits associated with telephone channel N+15. The value of N lies in the range 1 to 15 and refers to both the channel on the CSTo stream where the bits are output and the frame on the CEPT link on which the bits are received, and indirectly indicates the telephone channel with which the bits are are associated. The associated channel is N+15. For example, the bits output on the CSTo stream on channel 3 are associated with telephone channel 18, which is timeslot 19 of the CEPT link, and are received on bits positions 5 to 8 of timeslot 16 in frame 3 of each multiframe on the CEPT link .
3, 2, 1 &0
A(N+15), B(N+15), C(N+15) & D(N+15)
Table 11. Received Channel Associated Signalling: Data Format for CSTo Channels 1 to 15 BIT
7
NAME
IU0
DESCRIPTION
International Use 0: This is the bit which is received from the CEPT 2048 kbit/s link in bit position 1 of timeslot 0 of frame-alignment frames . It is reserved for the CRC remainder or for international use. Frame Alignment Signal Bits 2 to 8: These are the bits which are received from the CEPT 2048 kbit/s link in bit positions 2 to 8 of timeslot 0 of frame-alignment frames . These bits form the frame alignment signal and should have the values of `0011011`.
6-0
FAF2-8
Table 12. Received Frame Alignment Signal: Data Format for CSTo Channel 16 BIT
7
NAME
IU1
DESCRIPTION
International Use 1: This is the bit which is received from the CEPT 2048 kbit/s link in bit position 1 of timeslot 0 of non-frame-alignment frames. It is reserved for CRC framing bits or international bits. Receive Non-Frame Alignment Bit: This is the bit which is received from the CEPT 2048 kbit/s link in bit position 2 of timeslot 0 of non-frame-alignment frames . This bit should be `1` in order to differentiate between frame-alignment frames and non-frame-alignment frames. Non-Frame Alignment Alarm: This bit is received from the CEPT 2048 kbit/s link in bit position 3 of timeslot 0 of non-frame-alignment frames . It is used to signal an alarm from the remote end of the CEPT link. This bit should have the value `0` under normal operation and should go to `1 `to signal an alarm. National Use: These are the bits which are received on the CEPT 2048 kbit/s link in bit positions 4 to 8 of timeslot 0 of non-frame-alignment frames . These bits are reserved for national use, and on crossing international borders they should have the value `1`.
6
NFAF
5
ALM
4-0
NU1-5
Table 13. Received Non-Frame Alignment Signal: Data Format for CSTo Channel 17
4-197
MH89790B
BIT
7 6 5 4 3
Preliminary Information
DESCRIPTION
Frame Sync: This bit goes to `1` to indicate a loss of frame alignment synchronization by the MH89790B. It goes to `0` when frame synchronization is detected. Multiframe Sync: This bit goes to `1` to indicate a loss of multiframe synchronization by the MH89790B. It goes to `0` when multiframe synchronization is detected. Frame Alignment Error: This bit changes state when 16 or more errors have been detected in the frame alignment signal. It will not change state more than once every 128 ms. Control Slip: This bit changes state when a slip occurs between the received CEPT 2048 kbit/s link and the 2048 kbit/s ST-BUS. Receive Alarm Indication Signal: This bit goes to `1` to signal that an all-ones alarm signal has been detected on the received CEPT 2048 kbit/s link. It goes to '0' when the all-ones alarm signal is removed. Receive Timeslot 16 Alarm Indication Signal: This bit goes to `1` to signal that an all-ones alarm signal has been detected on channel 16 of the received CEPT 2048 kbit/s link. It goes to `0` when the all-ones alarm signal is removed. External Status: This bit contains the data sampled once per frame at the XSt pin. (Unused).
NAME
TFSYN MFSYN ERR SLIP RXAIS
2
RXTS16AIS
1 0
XSt N/A
Table 14. Master Status Word 1 (MSW1): Data Format for CSTo Channel 18 BIT
7-3 2-0
NAME
TxTSC TxBTC
DESCRIPTION
Transmit Timeslot Count: The value of these five bits indicate the timeslot count between the ST-BUS frame pulse and the rising edge of E8Ko. Transmit Bit Count: The value of these three bits indicate the bit position within the timeslot count reported in TxTSC above.
Table 15. Phase Status Word (PSW): Data Format for CSTo Channel 19 BIT
7-0
NAME
CERC
DESCRIPTION
CRC Error Counter: This byte is the CRC error counter. The counter will wrap around once it reaches FF count. If maintenance option is activated, the counter will reset once per second.
Table 16. CRC Error Count: Data Format for CSTo Channel 20 BIT
7 6 5-4 3 2
NAME
Si2 Si1 NA CRCTimer CRCRef
DESCRIPTION
The received Si bit in frame 15 is reported in this bit. Si2 will be updated after each RXMF pulse (pin 23). The received Si bit in frame 13 is reported in this bit. Si1 will be updated after each RXMF pulse (pin 23). Unused. CRC Timer: Transition from 1 to 0 indicates the start of one second interval in which CRC errors are accumulated. This bit stay high for 8 ms. CRC Reframe: A '1' indicates that the receive CRC multiframe synchronization could not be found within the time out period of 8 ms after detecting frame synchronization. This bit will go low if CRCSync goes low or if Maintenance is not activated. CRC Sync: A '0' indicates that CRC multiframing has been detected. Frame Count: This is the ninth and most significant bit of the Phase Status Word (see Table 15). If the phase status word is incrementing, this bit will toggle when the phase reading exceeds ST-BUS channel 31, bit 7. If the phase word is decrementing, then this bit will toggle when the reading goes below ST-BUS channel 0, bit 0.
1 0
CRCSync FrmPhase
Table 17. Master Status Word 2 (MSW2): Data Format for CSTo Channel 21
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Preliminary Information
Channel 18 contains a Master Status Word 1 (MSW1) which provides to the user information needed to determine the operating condition of the CEPT interface, i.e., frame synchronization, multiframe synchronization, frame alignment byte errors, slips, alarms, and the logic of the external status pin (see Table 14). Figure 11 shows the relationship between the control stream channels, and the CEPT signalling channels in the multiframe. The ERR bit in the Master Status Word 1 is an indicator of the number of errored frame alignment bytes that have been received in alternate timeslot zero. The time interval between toggles of the ERR bit can be used to evaluate the bit error rate of the line according to the CCITT Recommendation G.732 (see section on Frame Alignment Error Counter). Channel 19 contains the Phase Status Word (see Table 15) which can be used to determine the phase relationship between the ST-BUS frame pulse (F0i) and the rising edge of E8Ko. This information could be used to determine the long term trend of the received data rate, or to identify the direction of a slip. Channel 20 contains the CRC error count (see Table 16). This counter will wrap around once terminal count is achieved (256 errors). If the maintenance option is selected (bit 3 of MCW3) the counter is reset once per second. Channel 21 contains the Master Status Word 2 (see Table 17). This byte identifies the status of the CRC reframe and CRC sync. It also reports the Si bits received in timeslot 0 of frames 13 and 15 and the ninth and most significant bit (b 8) of the 9-bit Phase Status Word. Elastic Buffer The MH89790B has a two frame elastic buffer at the receiver which absorbs the jitter and wander in the received signal. The received data is written into the elastic buffer with the extracted E2o (2048 kHz) clock and read out of the buffer on the ST-BUS side with the system C2i (2048 kHz) clock (e.g., PBX system clock). Under normal operating conditions, in a synchronous network, the system C2i clock is phase-locked to the extracted E2o clock. In this situation every write operation to the elastic buffer is followed by a read operation. Therefore, underflow or overflow of data in the elastic buffer will not occur. If the system clock is not phase-locked to extracted clock (e.g., lower quality link which is selected as the clock source for the PBX) then data rate at which the data is being written into the not the the
MH89790B
device on the line side may differ from the rate at which it is being read out on the ST-BUS side. When the clocks are situations can occur: not phase-locked, two
Case #1: If the data on the line side is being written in at a rate SLOWER than it is being read out on the ST-BUS side, the distance between the write pointer and the read pointer will begin to decrease over time. When the distance is less than two channels, the buffer will perform a controlled slip which will move the read pointers to a new location 34 channels away from the write pointer. This will result in the REPETITION of the received frame. Case #2: If the data on the line side is being written in at a rate FASTER than it is being read out on the ST-BUS side, the distance between the write pointer and the read pointer will begin to increase over time. When the distance exceeds 42 channels, the elastic buffer will perform a controlled slip which will move the read pointer to a new location ten channels away from the write pointer. This will result in the LOSS of the last received frame.
Note that when the device performs a controlled slip, the ST-BUS address pointer is repositioned so that there is either a 10 channel or 34 channel delay between the input CEPT frame and the output ST-BUS frame. Since the buffer performs a controlled slip only if the delay exceeds 42 channels or is less than two channels, there is a minimum eight channel hysteresis built into the slip mechanism. The device can, therefore, absorb eight channels or 32.5s of jitter in the received signal. There is no loss of frame synchronization, multiframe synchronization or any errors in the signalling bits when the device performs a slip.
Frame Alignment Error Counter
The MH89790B provides an indication of the bit error rate found on the link as required by CCITT Recommendation G.703. The ERR bit (Bit 5 of MSW1) is used to count the number of errors found in the frame alignment signal and this can be used to estimate the bit error rate. The ERR bit changes state when 16 errors have been detected in the frame alignment signal. This bit can not change state more than once every 128 ms, placing an upper limit on the detectable error rate at approximately 10 -3. The following formula can be used to calculate the BER:
4-199
MH89790B
16* number of times ERR bit toggles BER= 7* 4000 * elapsed time in seconds where: 7 -is the number of bits in the frame alignment signal (0011011). -is the number of errored frame alignment signals counted between changes of state of the ERR bit. -is the number of frame alignment signals in a one second interval.
Preliminary Information
6.0 to 8.0 ms. By debouncing the signalling bits, a bit error in the latter will not affect the call in progress. (See Table 3, bits 3-0 of channel 15 on the CSTi0 line.)
CEPT PCM 30 Format MUX
The internal multiplexer formats the data stream corresponding to the CEPT PCM 30 format. The multiplexer will use timeslots 1 to 15 and 17 to 31 for data and timeslots 0 & 16 for the synchronization and channel associated signalling. The frame alignment and non-frame alignment signals for timeslot zero are sourced by the control stream input CSTi1 channel 16 and 17, respectively. The most significant bit of timeslot zero will optionally contain the cyclical redundancy check, CRC multiframe signal and Si bits used for far-end CRC monitoring.
16
4000
This formula provides a good approximation of the BER given the following assumptions: 1. The bit errors are uniformly distributed on the line. In other words, every bit in every channel is equally likely to get an error. 2. The errors that occur in channel 0 are bit errors. If the first assumption holds and the bit error rate is reasonable, (below 10-3) then the probability of two or more errors in 7 bits is very low. Attenuation ROM All transmit and receive data in the MH89790B is passed through the digital attenuation ROM according to the values set on bits 5 - 0 of data channels in the control stream (CSTi0). Data can be attenuated on a per-channel basis from 1 to 6 dB for both Tx and Rx data (refer Table 2). Digital attenuation is applied on a per-channel basis to the data found one channel after the control information stored in the control channel CSTi0, i.e., control stream 0 channel 4 contains the attenuation setting for data stream (DSTo) channel 5.
Framing Algorithms
There are three distinct framers within the MH89790B. These include a frame alignment signal framer, a multiframe framer and a CRC framer. Figure 12 shows the state diagram of the framing algorithms. The dotted lines show optional features which are enabled in the maintenance mode, that is selected by setting Maint bit of the Master Control Word 3 to "1". The frame synchronization circuit searches for the first frame alignment signal within the bit stream. Once detected, the frame counters are set to find the non-frame alignment signal. If bit 2 of the non-frame alignment signal is not one, a new search is initiated, else the framer will monitor for the frame alignment in the next frame. If the frame alignment signal is found, the device immediately declares frame synchronization. The multiframe synchronization algorithm is dependent upon the state of frame alignment framer. The multiframe framer will not initiate a search for multiframe synchronization until frame sync is achieved. Multiframe synchronization will be declared on the first occurrence of four consecutive zeros in the higher order quartet of channel 16. Once multiframe synchronization is achieved, the framer will only go out of synchronization after detection of two errors in the multiframe signal or loss of frame alignment synchronization. The CRC synchronization algorithm is also dependent on the state of the frame alignment
Signalling Bit RAM
The A, B, C, & D Bit RAM is used to retain the status of the per-channel signalling bits so that they may be multiplexed into the Control Output Stream (CSTo). This signalling information is only valid when the module is synchronized to the received data stream. If synchronization is lost, the status of the signalling bits will be retained for 6.0 ms provided the signalling debounce is active. Integrated into the signalling bit RAM is a debounce circuit which will delay valid signalling bit changes for
4-200
Preliminary Information
framer, but is independent of the multiframe synchronization. The CRC framer will not initiate a search for CRC framing signal until frame alignment synchronization is achieved. Once frame alignment synchronization is acquired, the CRC framer must find two framing signals in bit 1 of the non-frame alignment signal. Upon detection of the second CRC framing signal the MH89790B will immediately go into CRC synchronization. When maintenance feature is enabled (maint bit = 1) the CRC framer will force a complete reframe of the device if CRC frame synchronization is not found within 8 ms or more than 914 CRC errors occur per second. Bipolar Line Receiver The MH89790B receiver interfaces to the transmission line through a pulse transformer which splits the received AMI line signal into RxA and RxB. These two signals are combined by an internal NAND gate to form a new signal, which represents received data. The received data is clocked into the chip on the falling edge of E2o. Figure 28 shows the functional timing of the bipolar receiver.
MH89790B
Input impedance seen by the transmission line is about 75 ohms, (transformer ratio 1:1:1 with center-tap grounded) as required by G.703 for coaxial cable. Attenuation of the transmission line shall not exceed 6dB (at 1024 kHz) and attenuation characteristics shall be close to the "square root of F". AF [dB] = AFref [dB] *
f fref
where: AF - attenuation at frequency f in dB
AFref - attenuation at frequency fref in dB (in this case 6 dB) fref reference frequency (in this case 1024 kHz) frequency in kHz
f-
Input jitter tolerance of the MH89790B exceeds minimum jitter tolerance as specified in CCITT I.431 and G.823 (see Figure 13).
out of synchronization No search for frame alignment signal No Yes verify bit 2 of nonframe alignment signal Yes time out > 8ms verify second occurrence of frame alignment signal Yes frame synchronization acquired find two CRC frame alignment signals Yes CRC synchronization acquired search for multiframe alignment signal Yes multiframe synchronization acquired Yes - - - - - Only if the maintenance option is selected check for two errored multiframe alignment signals No No # of consecutive incorrect frame alignment signals = 3
number of CRC errors > 914/s
No
Figure 12 - Synchronization State Diagram
4-201
MH89790B
UI
Preliminary Information
AAAA AA AAAAAAAAAAAA AAAA AAAA 36.90AAAAAAAAAAAA AAAAAAAAAAAA AAAA AAAAAAAAAAAA AAAA A AAAAAAAAAAAA AAAAAAAAAAAA 20.50AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA P AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA E AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 10.0 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA K 8.00 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA * AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA T AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA O AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA * AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA P AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA E AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 2.50 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA K AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA J AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA I 1.5 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA T AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA T AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 1.00 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA E AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA R AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA S AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 0.54 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA (SINUSOIDAL) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 0.20 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
20 Hz 12 x 10-8 1 Hz 10 Hz 100 Hz JITTER FREQUENCY
2.4 kHz 1K
18 kHz 10 K 100 K
Figure 13 - Input Jitter Tolerance of MH89790B
- Maximum jitter tolerance of receiver - Minimum jitter tolerance specified by G.823 and I.431
Bipolar Line Transmitter The MH89790B provides two open collector drivers, OUTA and OUTB. These outputs are suitable for driving a center-tapped pulse transformer. Figure 29 illustrates how the two outputs combine to create opposite polarities of the AMI line code. Each output steers the transformer into producing a pulse of the opposite polarity. Clock Extractor The MH89790B contains a clock extraction circuit that generates the E2o clock from the received data. This clock is used to latch received data. The falling edge of E2o is approximately aligned with the center of the received data pulse. Alignment between these signals can be disrupted by jitter and wander on the received signal. Maximum tolerance of the MH89790B to the input jitter is shown in Figure 13 relative to minimum jitter tolerance specified in G.823 and I.431.
4-202
The extracted 8 kHz output (E8Ko) is derived from E2o clock by dividing it by 256. It can be used by an external phase-locked loop to generate the system clock and frame pulse that is synchronized to the network (see Figure 15).
MH89790B
VSS VDD
TR1 +5V (+12V) 2N2369 L1 C1 RxR OUTB R1
RxT
OUTA
* *
R2
* * * *
TR2
Preliminary Information
NOTES: L1 = 33H 130 mA C1 = 0.47F 20% Ceramic R1, R2 = 887 1% TR2 = Filtran* Part #TFS2915-5 (+5V Supply) Filtran* Part #TFS2915-4 (+12V Supply) TR1= Filtran* Part #TFS2574-4 LOS E2o E8Ko ADI
AAAAAAAAAAAAAAAA A A
AAAAAAAAAAAAAAAA A A
*
319
2N2369
RxA RxB 75 75 75
*
*
*
75
PADi
TxG
PADo
A A A A A A A A A A
* Filtran Ltd. 229 Colonade Road Nepean, Ontario Canada, K2E 7K3 Telephone: (613) 226-1626
DSTo DSTi CSTo CSTi0 CSTi1 F0i C2i RxMF TxMF XCtl Note: Variations in the transformer supply voltage will affect the transmit pulse amplitude (maximum tolerance is 5%).
XSt
MH89790B
Figure 14 - Interfacing the MH89790B to the 75 Coaxial Cable
4-203
MH89790B
4-204
MH89790B
+5V OUTA MT8979 DSTi TxA TxB R2 OUTB C1 Tx Line Driver R1 Twisted Pair
MT8980 Switch Matrix
* (+12V) * *
120 Line Matching Pad or Equalizer
*
TR2
STo0
* * *
TR1 RxT CSTi0 CSTo CSTi1 F0i C2i RxR
DSTo
STi0
F0i C4i
RxA RxB
* * *
Rx Line Receiver
Twisted Pair
MT8952 D-Channel Protocol Controller RxD
*
CDSTi E2i 75 Line Matching Pad E8Ko
M I C R O P R O C E S S O R Clock Extractor
CDSTo
MT8920B (Mode 1)
MT8941 (Note 1)
STo0 C2o
STi0 STo1
I N T E R F A C E
CS DS R/W
F0i
* *
C4i
DTACK IRQ IACK
F0b C4b C8Ko
16.384 MHz Osc.
MMS
+5V
NOTES: L1 = 33H 130 MA C1 = 0.47F 20% Ceramic R1, R2 = 909 1% TR2 = Filtran* Part #TFS2915-5 (+5V Supply) Filtran* Part #TFS2915-4 (+12V Supply) TR1 = Filtran* Part #TFS2574-4 * Filtran Ltd. 229 Colonnade Road Nepean, Ontario Canada, K2E 7K3 Telephone: (613) 226-1626
Note 1: Using the MT8941 may not meet some international standards for jitter performance. In cases where strict output jitter specification must be met, custom PLL may be required.
Preliminary Information
Figure 15 - Typical Primary Rate ISDN Application (interfacing to 120 Twisted Pair)
Preliminary Information
MH89790B
Line Side COM1 O
System Side
*
* *
OA
75
O
O F1 O F2
120 O
OB
Through Hole Parameter (Units)
Transformer Type Inductance (mH) (COM1-75) (COM1-120) Turns Ratio (COM1-75):(A-F1):(B-F2) (COM1-120):(COM1-75) Line Impedance () Operational Voltage (Volts) Dielectric Strength (Vrms) 1:1:1 1*26:1 75/120 1500 0*4:1:1 1*28:1 75/120 +12 1500 >1.2 >1.9 0.49 0.81
Units TFS 2915
TFS 2574-4
input
-4
output
-5
output >1 >1.5 1*12:1:1 1*22:1 75/120 +5 1500
Table 18. Typical Parameters of the Input and Output Transformers
Applications
ISDN Primary Rate User Network Interface Typical examples of primary rate interfaces are high capacity links from a PBX to a Central Office Exchange or multiple links between PBX's in a large private network. With the advent of Integrated Services Digital Networks (ISDN) a limited set of network interfaces is specified to allow equipment from different vendors to operate in the network. The MH89790B conforms to the ISDN S/T Primary Rate reference point standard, which calls for 30 B channels (64 kbit/s) and one D channel (64 kbit/s). Figure 15 illustrates a typical application of the MH89790B in an ISDN environment. Three types of information are passed through serial busses of the MH89790B:
SIGNALLING - Signalling information on the ISDN primary rate interface is carried over the D-channel using LAPD procedures. The ISDN D-channel is created by placing the MH89790B in Common Channel Signalling mode. The D-channel is tapped off from the ST-BUS and connected to the MT8952 Protocoller Controller. It receives and transmits data packets serially, in accordance with LAPD protocol requirements. CONTROL - The MT8920B (STPA) provides microprocessor access to directly control the MH89790B through its transmit and receive dual port RAMs. Status information can generate interrupts to notify the system in case of slips, loss of synchronization, alarms, violations, etc.
Interfacing to the Coaxial Cable Transmission Line Reliable operation of the CEPT link is directly related to the type of transmission medium and method of interfacing. Coaxial cables provide excellent transmission mediums if used properly. One of the most important things to remember is that the receive end of the cable must not be connected to ground, as shown in Figure 16. If both ends are
4-205
USER DATA - The data streams of the MH89790B are shown connected to the MT8980 Digital Crosspoint Switch. This allows voice and data channels to be switched dynamically within the system.
MH89790B
connected to the ground, uncontrolled current will flow through the shield of the cable and interfere with the transmitted signal. Magnetics Information Table 18 provides typical electrical parameters for suitable input and output transformers. For supporting initial design activities, Mitel Semiconductor has available CEPT MH89790B Ancilliary Component Kits which contains input and output transformers. Alternatively, they are available directly from the following manufacturer: Filtran Ltd. 229 Colonnade Road Nepean, Ontario Canada K2E 7K3 Telephone: 613-226-1626.
Preliminary Information
MH89790B 25
22
Tx
+V
*
MH89790B 24 Line Matching Pad 23
*
AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AAA AA AA
MH89790B
* **
29
* * *
AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AAA AA AA
A A A A A A A A A A A A A A A A
6 Rx
*
7
6 Rx
*
*
7
24 MH89790B 22 Line Matching Pad 23
**
*
A A A A A A A A A A A A A A A A
25 Tx +V
*
29
Note:
* **
Coaxial Cable This end is not grounded
Figure 16 - Grounding Method of the Outer Conductor to the Coaxial Cable
4-206
Preliminary Information
Absolute Maximum Ratings*
Parameter 1 2 3 4 5 Supply Voltage with respect to VSS Voltage on any pin other than supplies Current at any pin other than supplies Storage Temperature Package Power Dissipation TST P -40 Symbol VDD Min -0.3 VSS-0.3
MH89790B
Max 7 VDD+0.3 40 85 800
Units V V mA C mW
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3
I n p u t
Sym TOP VDD VIH VIH
Min 0 4.5 2.4 1.2 VSS
Typ
Max 70
Units C V V V
Test Conditions
Operating Temperature Supply Voltage Input High Voltage
5.0
5.5 VDD
For 400 mV noise margin RxT and RxR For 400 mV noise margin RxT and RxR
4
s
Input Low Voltage
VIL VIL
0.4 0.3
V V
DC Electrical Characteristics - Clocked operation over recommended temperature ranges and power supply voltages.
Parameters 1 2 3 4 5 6 7 8
O u t p u t I n p u t s
Sym IDD VIH VIL IIL VOH IOZ IOH VOL VOL IOL
Min
Typ 15
Max 45 VDD 0.8
Units mA V V A V nA mA
Test Conditions Outputs Unloaded Digital Inputs Digital Inputs Digital Inputs VIN=0 toVDD IOL=10mA VO = 0 to VDD Source Current, VOH=2.4V IOL=2mA IOL=10mA Sink Current, VOL=0.4V
Supply Current Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output High Leakage Output High Current Output Low Voltage OUTA or OUTB Output Low Current Input Impedance RxT to RxR
2.0 0.0 +1 2.4
+10 VDD 500
7 VSS
20 0.4 0.25
V V mA
9 10
s
2
10 319
AC Electrical Characteristics - Capacitance
Characteristics 1 2 Input Pin Capacitance Output Pin Capacitance Sym CI CO Min Typ 10 10 Max Units pF pF Test Conditions
Timing is over recommended temperature & power supply voltages. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. 4-207
MH89790B
Preliminary Information
AC Electrical Characteristics - ST-BUS Timing (Figures 17 and 18)
Characteristics 1 2 3 4 5 6 7 8 9 C2i Clock Period C2i Clock Width High or Low Frame Pulse Setup Time Frame Pulse Hold Time Frame Pulse Width Serial Output Delay Serial Input Setup Time Serial Input Hold Time Frame Pulse Setup Time 2 Sym tP20 tW20 tFPS tFPH tFPW tSOD tSIS tSIH tFPS2 30 55 20 Min 400 200 50 50 100 300 125 Typ 488 244 150 Max 600 Units ns ns ns ns ns ns ns ns ns 150 pF Load tP20 = 488 ns Test Conditions
Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
F0i
C2i
ST-BUS BIT CELLS
Channel 31 Bit 0
Channel 0 Bit 7
Channel 0 Bit 6
Figure 17 - Clock & Frame Alignment for 2048 kbit/s ST-BUS Streams
ST-BUS Bit Stream tFPW F0i VIH VIL tFPS VIH C2i VIL tSIS tFPH
Bit Cell
tFPS2
tP20 tW20 tW20
tSIH
DSTi VIH or CSTi0/1 VIL tSOD DSTo or CSTo VOH VOL
Figure 18 - Clock & Frame Timing for 2048 kbit/s ST-BUS Streams
4-208
Preliminary Information
AC Electrical Characteristics - Multiframe Clock Timing (Figure 21)
Characteristics 1 2 3 4 Receive Multiframe Output Delay Transmit Multiframe Setup Time Transmit Multiframe Hold Time Tx Multiframe to C2 Setup Time Sym tRMFD tTMFS tTMFH tMF2S 50 50 100 * Min Typ Max 150 Units ns ns ns ns
MH89790B
Test Conditions 50pF
Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * 256 tP20 - 100ns Frame 15 DSTo Bit Cells F0i Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 Bit 7 Bit 6 Frame 0 Bit 5 Bit 4 Bit 0 Bit 7
C2i
RxMF
Figure 19 - Functional Timing for Receive Multiframe Clocks
Frame N DSTi Bit Cells F0i Bit 7 Bit 6 Bit 5 Bit 4 Bit 0 Bit 7 Bit 6 Bit 5 Frame 0 Bit 4 Bit 0 Bit 7
C2i
TxMF
Figure 20 - Functional Timing for Transmit Multiframe Clock
F0i tRMFD
C2i tRMFD
RxMF(1) tMF2S
tTMFS TxMF(1)
tTMFH
Figure 21 - Clock and Frame Timing for 2048 kbit/s ST-BUS Streams
Note 1: These two signals do not have a defined phase relationship 4-209
MH89790B
Preliminary Information
AC Electrical Characteristics - XCtl, XS and E8Ko (Figures 22, 23 and 24)
Characteristics 1 2 3 4 5 6 7 External Control Delay External Status Setup Time External Status Hold Time E8Ko Output Delay E8Ko Output Low Width E8Ko Output High Width E8Ko Output Transition Time Sym tXCD tXSS tXSH t8OD t8OL t8OH t8OT 62.5 62.5 20 50 50 150 Min Typ Max 100 Units ns ns ns ns s s ns 50 pF load 50 pF load 50 pF load 50 pF load Test Conditions 50 pF load
Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
ST-BUS Bit Cell Boundary Between Bit 3 Channel 17 and Bit 2 Channel 17
F0i
VIH VIL
C2i
VIH VIL
VOH XCtl VOL tXCD
XS
VIH VIL tXSS tXSH
Figure 22 - XCtl Timing
Figure 23 - XS Timing
Received CEPT Bits
Timeslot 0 Bit 4
***
Timeslot 16 Bit 4
***
Timeslot 0 Bit 4
E2i
VOH VOL t8OD VOH VOL t8OL t8OT t8OT t8OH t8OT t8OD t8OD
E8Ko
Figure 24 - E8Ko Timing
4-210
Preliminary Information
AC Electrical Characteristics - CEPT Link Timing (Figures 25 and 26)
Characteristics 1 2 3 4 5 6 7 8 Transmit Steering Delay E2o Clock Period E2o Clock Width High or Low Receive Data Setup Time Receive Data Hold Time Receive Data Pulse Width Receive Data Fall Time Receive Data Rise Time Sym tTSD tPEC tWEC tRDS tRDH tRDW tRDF tRDR Min Typ 150 488 244 50 50 244 20 30 Max Units ns ns ns ns ns ns ns ns
MH89790B
Test Conditions See Figure 27, Note 1
Note 1 - The difference between T TSD for OUTA and OUTB is tyically 20 ns. Timing is over recommended operating temperature and power supply voltage ranges. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
Transmitted CEPT Link Bit Cells
Bit Cells
V IH C2i VIL tTSD OUTA or OUTB 11.8V 1.2V tTSD
Figure 25 - Transmit Timing for CEPT Link
Received CEPT Link Bit Cells tWEC E2o VOH VOL
Bit Cell tPEC tWEC
tRDS RxA or RxB VOH VOL tRDF tRDW
tRDH
tRDR
FIgure 26 - Receive Timing for CEPT Link
4-211
MH89790B
Preliminary Information
+5V
*
(+ 12V) 400 50pF
OUTA
**
+5V (+ 12V)
*
OUTB
*
400
*
50pF
*
Figure 27 - OUTA and OUTB Test Circuit
125Sec E2o
HDB3
RxA
RxB
E8K0
Figure 28 - CEPT Receive Timing
C2i
INT DATA
OUTA
OUTB HDB3
Figure 29 - CEPT Transmit Timing
4-212
Preliminary Information
MH89790B
2.0 ms FRAME 15 FRAME 0
********
TIMESLOT 0 TIMESLOT 1
FRAME 14
FRAME 15
FRAME 0
****
125s Bit 4 Bit 5 Bit 6 Bit 7
TIMESLOT 30
TIMESLOT 31
Most Significant Bit (First)
Bit 1
Bit 2
Bit 3
Bit 8
Least Significant Bit (Last)
(8/2.048)s
Figure 30 - CEPT PCM 30 Frame & Multiframe Formats
Packaging
The MH89790B is available in three package options which are: * The MH89790B which is pin compatible with the MH89790, has a row pitch of 1.3" and is fitted with a plastic lid. See Figure 31 for the dimensional drawing for this part.
2.12 (53.85)
*
*
The MH89790BN which is a narrow version of the MH89790B and has a row pitch of 0.8". See Figure 32 for the dimensional drawing for this part. The MH89790BS which is a surface mountable version of the MH89790BN is suitable for Infrared Reflow (I.R.) soldering. See Figure 33 for the dimensional drawing, and Figure 34 for the recommended footprint.
.31 (7.87) 1.3 (33.0) Note 2 0.10 + 0.01 (2.54 + 0.25)
MH89790B
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
0.09 (2.3)
0.260 (6.6)
Note 1 2.0 (50.8) Notes: 1) Pin 1 not fitted. 2) Row pitch is to the centre of the pins. 3) All dimensions are typical and in inches (mm). 4) Not to scale. 0.020 + 0.002 (0.51 + 0.051)
Figure 31 - Physical Dimensions for the 40 Pin Dual in Line Hybrid 1.3" Row Pitch
4-213
MH89790B
2.0 (50.8)
Preliminary Information
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
0.25 (6.35)
0.8 (20.32) Note 2 0.10 + 0.01 (2.54 + 0.25)
MH89790BN
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
0.09 (2.3) 0.260 (6.6)
Note 1 0.020 + 0.002 (0.51 + 0.051) Notes: 1) Pin 1 not fitted. 2) Row pitch is to the centre of the pins. 3) All dimensions are typical and in inches (mm). 4) Not to scale.
Figure 32 - Physical Dimensions for the 40 Pin Dual in Line Hybrid 0.8" Row Pitch
2.0 (50.8)
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA
0.25 (6.35)
0.78 (19.81) 0.06 (1.52) 0.9 (22.86)
0.125 (3.18)
0.10 + 0.01 (2.54 + 0.25)
0.06 (1.52)
MH89790BS
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
0.125 (3.18)
Note 1
0.020 + 0.002 (0.51 + 0.051)
Notes: 1) Pin 1 not fitted. 2) All dimensions are typical and in inches (mm). 3) Not to scale.
Figure 33 - Physical Dimensions for the 40 Pin Dual in Line S.M.T. Hybrid
4-214
Preliminary Information
MH89790B
0.760 (19.3) Pin 2 position 0.090 (2.29)
0.040 (1.02)
0.060 (1.52)
Figure 34 - Recommended Footprint for the 40 Pin Dual in Line S.M.T. Hybrid
4-215
MH89790B
Appendix
Control and Status Register Summary 7
UNUSED Keep at 1
Preliminary Information
6
LOOP16 1 Enabled 0 Disabled
5
UNUSED Keep at 1
4
3
NDBD 1 No Debounce 0 Debounce
2
NDBC 1 No Debounce 0 Debounce
1
NDBB 1 No Debounce 0 Debounce
0
NDBA 1 No Debounce 0 Debounce
Master Control Word 1 (MCW1) - CSTi0, Channel 15
UNUSED Keep at 1 UNUSED Keep at 0 CCS 1 Common Channel 0 Channel Associated 8 kHz SEL 1 Enabled 0 Disabled TXAIS 1 Alarm On 0 Alarm Off TXTS16AIS 1 Alarm On 0 Alarm Off XCTL 1 Set High 0 Cleared UNUSED
Master Control Word 2 (MCW2) - CSTi0, Channel 31
UNUSED Keep at 0 SiMUX 1 Enabled 0 Disabled RMLOOP 1 Enabled 0 Disabled HDB3en 1 Disabled 0 Enabled Maint 1 Enabled 0 Disabled CRCen 1 Enabled 0 Disabled DGLOOP 1 Enabled 0 Disabled ReFR Device reframes on High to Low Transition
Master Control Word 3 (MCW3) - CSTi1, Channel 18
DATA 1 No ADI 0 Enable ADI LOOP 1 Enabled 0 Disabled RxPAD4 RxPAD2 RxPAD1 TxPAD4 TxPAD2 TxPAD1
Per Channel Control Word - CSTi0, Channels 0-14 and 16-30
A(N) Tx Signalling Bit B(N) Tx Signalling Bit C(N) Tx Signalling Bit D(N) Tx Signalling Bit A(N+15) Tx Signalling Bit B(N+15) Tx Signalling Bit C(N+15) Tx Signalling Bit D(N+15) Tx Signalling Bit
Channel Associated Signalling - CSTi1, Channels N = 1 to 15
IUO Should be kept at 1 FAF2-8 Frame Alignment Signal - Keep at "0011011"
Frame Alignment Signal - CSTi1, Channel 16
MA1-4 Multiframe Alignment Signal - Keep at "0000" X1 Spare Bit Should be 1 Y 1 Alarm On 0 Alarm off X2, X3 Spare Bits - Should be 1
Multiframe Alignment Signals - CSTi1, Channel 0
IU1 Reserved for International Used NFAF Keep at "1" ALM 1 Alarm On 0 Alarm Off NU1-5 Bits Reserved for National Use - Should be kept at "1"
Non-Frame Alignment Signal - CSTi1, Channel 17
4-216
Preliminary Information
MH89790B
5 4
SLIP Changes State when Slip Performed
7
TFSYN 1 Out of Sync 0 In Sync
6
MFSYN 1 Out of Sync 0 In Sync
3
RXAIS 1 Alarm Detected 0 No Alarm
2
TXTS16AIS 1 Alarm Detected 0 No Alarm
1
XS 1 XSt High 0 XSt Low
0
UNUSED
ERR Frame Alignment Signal Error Count
Master Status Word 1 (MSW1) - CSTo, Channel 18
Si2 Remote SMF2 is: 1 Correct 0 Errored Si1 Remote SMF1 is: 1 Correct 0 Errored UNUSED CRC Timer Transition from 1 to 0 indicates start of the CRC Error Count CRC Ref 1 Reframed forced by lack of CRC frame CRC Sync 1 CRC Frame not Detected 0 CRC Frame Detected FrmPhase Bit 8 of Phase Status Word
Master Status Word 2 (MSW2) - CSTo, Channel 21
TxTSC Transmit Timeslot Count, Timeslots between F0i and E8Ko TxBTC Transmit Bit Count - bit positions within TxTSC between F0i and E8Ko
Phase Status Word - CSTo, Channel 19
CERC 0 - 7 Bits 0 - 7 of CRC Error Counter
CRC Error Counter - CSTo, Channel 20
A(N) Rx Signalling Bit B(N) Rx Signalling Bit C(N) Rx Signalling Bit D(N) Rx Signalling Bit A(N+15) Rx Signalling Bit B(N+15) Rx Signalling Bit C(N+15) Rx Signalling Bit D(N+15) Rx Signalling Bit
Received Channel Associated Signalling - CSTo, Channels N = 1 to 15
IUO International Bit FAF2-8 Received Frame Alignment Signal
Received Frame Alignment Signal - CSTo, Channel 16
MA1-4 Received Multiframe Alignment Signal X1 International Bit Y 1 Remote MF Lost 0 Remote MF Detected X2, X3 International Bits
Received Multiframe Alignment Signals - CSTo, Channel 0
IU1 Reserved for International Use NFAF ALM 1 Detected 0 Not Detected Bits Reserved for National Use NU1-5
Received Non-Frame Alignment Signal - CSTo, Channel 17
4-217
MH89790B
NOTES:
Preliminary Information
4-218

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