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CXA1977R
10-bit 20MSPS A/D Converter
Description The CXA1977R is a 10-bit 20MSPS 2-step parallel type A/D converter for video signal processing. This A/D converter operates on +5V power supplies. The analog signal can be converted to the digital signal by using this IC in conjunction with the Sample-and-hold IC. Features * Maximum operating speed : 20MSPS (Min.) * Resolution : 10-bit * Low power dissipation : 160mW (Typ.) * Wide-band analog input : 10MHz * Low input capacitance : 50pF (Typ.) * Built-in digital correction (Compensation within 16LSB) * TTL input * TTL output * Output code : binary/2'S complement/1'S complement Block Diagram
VREFBS VREFB VREF3 VREF2 VREF1 VREFT VREFTS N.C. N.C. DVCC3
25 24 PS 23 ENABLE
48 pin LQFP (Plastic)
Function 10-bit 20MSPS 2-step parallel type A/D converter Structure Bipolar silicon monolithic IC Applications High resolution video signal processing
36 N.C. 37 N.C. 38
35
34
33
32
N.C.
27
31
30
29
28
26
DVCC3
L-COMPARATOR
L-ENCORDER
VINL 39 VINH 40 N.C. 41 AVCC 42 N.C. 43 H-ENCODER AGND 44 DVCC2 45 UNDER 46 OVER 47 DGND1 48 1 2 3 4 5 6 7 8 OVER/UNDER OUTPUT BUFFER FINE OUTPUT BUFFER MATRIX H-COMPARATOR
22 CLK
CLK BUFFER
21 MINV 20 LINV 19 N.C. 18 DVCC3 17 DGND2 16 DGND1
CORRECTION COARSE OUTPUT BUFFER
15 DVCC1 14 DGND1 13 N.C.
9
10
11
12
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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(MSB) D9
(LSB) D0
DGND1
D1
D2
D3
D4
N.C.
D5
D6
D7
D8
E94326-PS
CXA1977R
Absolute Maximum Ratings (Ta = 25C) * Supply voltage DVcc1 0 to +6 V DVcc2 0 to +6 V DVcc3 0 to +6 V AVcc 0 to +6 V * Analog input voltage VINH AGND to AVcc + 0.3 V VINL AGND to AVcc + 0.3 V * Reference voltage VREFT AGND to AVcc + 0.3 V VREFB AGND to AVcc + 0.3 V * Digital input voltage CLK DGND1 - 0.5 to DVcc1 V MINV DGND1 - 0.5 to DVcc1 V LINV DGND1 - 0.5 to DVcc1 V PS DGND1 - 0.5 to DVcc1 V ENABLE DGND1 - 0.5 to DVcc1 V * Digital output voltage Vo DGND1 - 0.5 to +3.6 V (Vo: The voltage is applied to the output pin for high impedance output.) * Storage temperature Tstg -65 to 150 C 950 mW * Allowable power dissipation PD (On a fiber-glass epoxy board: 40mm x 40mm, t = 0.8mm) Recommended Operating Conditions * Supply voltage DVcc1 DVcc2 DVcc3 AVcc AGND DGND1 DGND2 VINH VINL VREFT VREFB VIH VIL Min. +4.6 +4.6 +4.6 +4.6 Typ. +5 +5 +5 +5 0 0 0 Max. +5.25 +5.25 +5.25 +5.25 Unit V V V V V V V V V V V V V ns ns C
* Analog input voltage * Reference voltage * Digital input voltage * Clock width * Operating temperature
+2 +2 +3.9 +1.9 +2 25 24 -20
+4 +2
+4 +4 +4.1 +2.1 +0.8
tPWH tPWL
Topr
+85
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CXA1977R
Pin Description Pin No. Symbol I/O Pin voltage Equivalent circuit
45 DVCC2
Description Digital output D0 (LSB) to D9 (MSB)
1 to 5 8 to 12
D0 to D9
O
1 D0 to 5 D4 8 D5 to 12 D9 46 UNDER 47 OVER
46
UNDER
O
TTL
200k
Underflow output
47
OVER
O
16 DGND1 17 DGND2
Overflow output
15 45 6, 14, 16, 48 18 25 26 17 44
DVCC1 DVCC2 DGND1 -- --
+5V (typ.) GND
Digital power supply Digital ground
DVCC3
--
+5V (typ.)
Digital power supply
DGND2 AGND
-- GND --
Digital negative power supply Analog negative power supply This input can invert output form of D0 to D8. In open condition, this pin turns to high level input. (For details, refer to the Output Formula Chart.) This input can invert output form of D9 (MSB). In open condition, this pin turns to high level input. (For details, refer to the Output Formula Chart.) 3-state control. Turns to enable when low is input. In open condition, this pin turns to high level input.
20
LINV
I
DVCC1 15 ENABLE 23 400k 100k 100k
TTL 21 MINV I
PS 24 MINV 21 LINV 20
DGND2 17
16 DGND1
23
ENABLE
I
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CXA1977R
Pin No.
Symbol
I/O
Pin voltage
Equivalent circuit
DVCC1 15 ENABLE 23 PS 24 400k 100k 100k
Description
24
PS
I
TTL
MINV 21 LINV 20
DGND2 17
16 DGND1 DVCC1 15 20k 30k 30k
Power save input. Power save condition is entered when high level is input. In open condition, this pin turns to high level input.
22
CLK
I
TTL
CLK 22
Clock input
DGND2 17
16 DGND1
29
VREFTS
-- +4V
VREFTS 29
130
Reference voltage sense (Top) Reference voltage force (Top)
30
VREFT
I
VREFT 30 VREF1 31
31
VREF1
--
+3.5V
VREF2 32
32
VREF2
--
+3.0V
VREF3 33 VREFB 34
33
VREF3
--
+2.5V
VREFBS 35 130
34
VREFB
I +2V
Reference voltage force (Bottom) Reference voltage sense (Bottom)
35
VREFBS
--
AGND 44
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CXA1977R
Pin No.
Symbol
I/O
Pin voltage
Equivalent circuit
Description
42 AVCC 11.2k 11.2k
39
VINL
I
+2V to +4V
VINL 39
VREF
Analog input (Lower comparator input)
44 AGND
42 AVCC 26k 26k
40
VINH
I
+2V to +4V
VINH 40
VREF
Analog input (Upper comparator input)
44 AGND
42
AVCC
--
+5V (Typ.)
Analog power supply Open. Not connected to internal circuit, but connection to DGND (digital ground) is recommended. Open. Not connected to internal circuit, but connection to AGND (analog ground) is recommended.
7, 13, 19, 27
N.C.
--
--
28, 36, 37, 38, 41, 43
N.C.
--
--
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CXA1977R
Electrical Characteristics (Ta = 25C, DVCC1, 2, 3, AVCC = +5V, AGND, DGND1, 2 = 0V, VREFB = +2V, VREFT = +4V) Item Resolution DC characteristics Integral linearity error Differential linearity error Analog input Analog input current Analog input capacitance Analog input band width Reference voltage input Reference current Reference resistance Offset voltage IREF RREF EOT EOB VREF1 Reference voltage VREF2 VREF3 Digital input Digital input voltage VIH VIL IIH1 Digital input current IIL1 IIH2 IIL2 Digital input characteristics Switching characteristics Maximum operating speed Clock pulse width Fc 20 25 4 24 -2 -15 4 CL = 20pF 6 10 10 1 -1 5 2 30 30 250 5 7 400 500 500 -6- MSPS ns ns ns ns ns ns ns ns ns ns 3 2 DVCC1 = 5.25V VIH = 2.7V VIL = 0.5V VIH = 2.7V VIL = 0.5V -10 -200 -10 -20 2 2 0.8 +10 0 +10 0 V V A A A A pF -16 120 1 1 -10 200 10 10 3.5 3.0 2.5 -7 280 25 25 mA mV mV V V V IIN CIN BW VIN = +4V VIN = +3V + 0.07Vrms -1dB 0 50 10 60 A pF MHz EIL EDL1 EDL2 VIN = +2 to +4V VIN = +2 to +2.5V VIN = +2.5 to +4V -2.0 -0.8 -1 +2.0 +0.8 +21 LSB LSB LSB Symbol n Measurement conditions Min. 10 Typ. 10 Max. 10 Unit bit
Sampling delay
Output delay time
3-state output disable time
3-state output enable time
tPWH tPWL tSH tSL tDLH tDHL tPHZ tPLZ tPZH tPZL
CXA1977R
Item Digital output Digital output voltage Leak current during output off Dynamic characteristics Differential gain error Differential phase error
Symbol
Measurement conditions
Min.
Typ.
Max.
Unit
VOH VOL IOZ
IOH = -300A IOL = +500A
DVCC1, 2 = 4.6V
2.7
3.4 0.5
V V A
DVCC1, 2 = 5.25V, VO = 3.6V
-20
75
DG DP
NTSC 40IRE mod. ramp, Fc = 14.3MSPS Fc = 20MSPS FIN = 1kHz FIN = 1MHz FIN = 2MHz FIN = 7.5MHz
0.5 0.3 55 53 52 49
% deg dB dB dB dB
SNR
Fc = 20MSPS SNR Fc = 20MSPS Fc = 20MSPS
Power supply DVCC1 current IDVCC1 DVCC1 = +5V 8 During power save DVCC2 = +5V 8 During power save DVCC3 = +5V 8 During power save AVCC = +5V 8 During power save 6.0 4.3 0.05 0 8.1 0.34 0.5 0 87 8 During power save 37 9.9 7.3 0.16 0 14.7 0.55 3.2 20 160 59 14.0 12.0 0.30 27 21.1 1.13 6.0 50 239 98 mA mA mA mA mA mA mA A mW mW
DVCC2 current
IDVCC2
DVCC3 current
IDVCC3
AVCC current Power dissipation Pd = A + B A = (IDVCC1 + IDVCC2 + IDVCC3 + IAVCC) x 5V B = | IREF | x 2V 1 2 3 4 5 6 7 8
IAVCC
Pd
+1 < EDL2 +2 (LSB) is two and under. CLK input MINV, LINV, ENABLE, and PS inputs Refer to Timing Diagram (1) Refer to Timing Diagram (2) The load is a bi-state totem-pole output delay time test load circuit. The load is a 3-state output test load circuit. When PS and ENABLE inputs are in high level.
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CXA1977R
Bi-state Totem-pole Output Delay Time Test Load Circuit
Test point
Output from the IC under test CL Note 1) CL = 20pF
3-state Output Test Load Circuit
Test point VCC
Test condition
3.9k S1 Output from the IC under test 1k Note 2) S2 CL = 20pF
S1 Close Open Close
S2 Open Close Close
tPZL tPZH tPLZ tPHZ
CL Note 1)
Note 1) CL includes probe capacitance and parasitic capacitance in Test Board. Note 2) All diodes are IS2076. Error Rate Test Circuit
(Threshold level) DIP SW B A ADDER A+B =C C C A>C COMPA- A RATOR
SG1
VIN
CXA1977R
LATCH
LATCH
COUNTER
(FC/2) - 1kHz
CLK
SG2
FC
DIVIDER
FC/2
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CXA1977R
Notes on Operation 1. Analog ground (AGND) Keep analog ground surface on PCB as wide as possible with impedance and resistance as low as possible. 2. Digital ground (DGND1, DGND2) Upon mounting to PCB keep ground surface as wide as possible with impedance and resistance as low as possible. Moreover, a common analog and digital ground immediately near ADC will help obtain characteristics smoothly. 3. Digital positive power supply (DVcc1, DVcc2, DVcc3) Connect to the digital ground with a ceramic capacitor over 0.1F and as close to the pins as possible. Insert a ceramic capacitor between DVcc2 and DGND1 of TTL output power supply as shortly as possible because noise tends to occur. 4. Analog positive power supply (AVcc) Connect to the analog ground on PCB with a ceramic capacitor over 0.1F as close to the pin as possible. 5. Reference voltage (VREFTS, VREFT, VREF1, VREF2, VREF3, VREFB, VREFBS) These pins provide reference voltage to upper and lower comparators. Voltage between VREFT and VREFB corresponds to input dynamic range. There is a 200 resistance between VREFT and VREFB. By applying 2V to both pins a current of about 10mA flows. When the reference voltage is made unstable by the clock, ADC characteristics are adversely affected. Connect VREFT and VREFB to the analog ground on PCB by means of a tantalum capacitor over 10F and a ceramic capacitor over 0.1F respectively. Also, connect each of VREF1, VREF2 and VREF3 to the analog ground on PCB using a ceramic capacitor over 0.1F. This will provide stability to the characteristics of high frequency. Strictly speaking on reference voltage VREFT side and VREFB side there is a respective about 10mV offset. When there is no problem with the usage of those offset voltages, voltage is applied directly to VREFT, VREFB. In case the reference voltage is to be strictly applied, adjust to obtain an offset voltage of 0V, keeping VREFTS and VREFBS as sense pins and VREFT and VREFB as force pins to form a feedback loop circuit. For details, see the Standard Circuit. 6. Analog input (VINH, VINL) VINH is the input pin for the upper comparator while VINL is the input pin for the lower comparator. Keep the input signal level within the level between VREFT and VREFB. As this IC's analog input capacitance stands at about 50pF, it is necessary to drive with an buffer amplifier having sufficient driving capability. Also, when driving is done with the buffer amplifier of a low output impedance, as A/D converter input capacitance is large, ringing is generated and settling time grows longer. Here a small resistance of about 5 to 30 is connected in series between the buffer amplifier and each of A/D converter's VINH and VINL, as a dumping resistance. This eliminates ringing and shortens settling time. Also keep wiring between buffer amplifier and A/D converter as short as possible.
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CXA1977R
7. Clock input (CLK) TTL input. Clock line wiring should be the shortest possible while distanced from other signal lines to avoid affecting them. This IC is 2-step parallel type A/D converter. Accordingly an external sample-and-hold circuit (SH) is necessary. However the timing between this SH circuit output waveform (A/D converter analog input waveform) and the A/D converter clock timing requires attention. In the relation between A/D converter clock and the A/D converter analog input signal, with the timing TH of the rising edge of A/D converter clock, the upper comparator compares the input signal and the reference voltage to latch the results. After that, with the timing TL of the falling edge of A/D converter clock, the lower comparator compares the input signal and reference signal to latch the results. (Strictly speaking, the sampling delay tSH is in TH and the sampling delay tSL is in TL.) In this A/D converter, the lower comparator features a length of 32mV (16LSB) redundance in relation to the upper comparator. At the timing when the lower comparator compares input signal and reference signal to latch at the timing TL, it is necessary to have the SH output settling performed. But at the timing when the upper comparator compares input signal and reference voltage to latch at the timing TH, as long as the SH output is within the 32mV range to the final settling value, digital correction applies, A/D conversion precisely occurs. As seen from the above, A/D converter clock rise and fall timing versus SH output waveform should be duly considered. For the clock high level time tPWH and low level time tPWL, set to a value in excess of the time indicated for the respective operating conditions. Output data is synchronously with the clock rising edge. For details on timing, refer to the Timing Chart. 8. MINV input (MINV) Digital output polarity inversion control pin of D9 (MSB). TTL input. At open, turns to high level input. For correspondence with analog input voltage and output data code, refer to the Output Formula Chart. 9. LINV input (LINV) Digital output polarity inversion control pin of D8 to D0 (LSB). TTL input. At open, turns to high level input. For correspondence with analog input voltage and output data code, refer to the Output Formula Chart. 10. Output enable (ENABLE) 3-state control pin of digital output (D0 to D9, UNDER, OVER) TTL input. At open, turns to high level input. At that time digital output turns all to high impedance. 11. Power save input (PS) Power save control pin of internal circuit. TTL input. At open, turns to high level input. To set to power save mode, turn both PS and ENABLE to high level input.
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CXA1977R
12. Digital output (D0 to D9) Output pin of D9 (MSB) to D0 (LSB). TTL output. Output data polarity inversion is executed by means of MINV and LINV signals, and they can output in binary, 1'S complement and 2'S complement. Also, by turning ENABLE signal to high level, the output can be turned into high impedance output. However, when the output level is for high impedance output or is in power save mode, the voltage of 3.6V or more must not be applied to prevent the distruction of IC. For correspondence with analog input voltage and output data code, refer to the Output Formula Chart. For the timing, refer to the Timing Chart. 13. Overflow output (OVER) When the input signal exceeds VREFT, overflow signal is output. MINV and LINV have no effect on this pin. Also by turning ENABLE signal to high level, the output can be turned into high impedance output. However, when the output level is for high impedance output or is in power save mode, the voltage of 3.6V or more must not be applied to prevent the distruction of IC. For correspondence with analog input voltage and output data code, refer to the Output Formula Chart. For the timing, refer to the Timing Chart. 14. Underflow output (UNDER) When the input signal turns below VREFB, underflow signal is output. MINV and LINV have no effect on this pin. Also by turning ENABLE signal to high level, the output can be turned into high impedance output. However, when the output level is for high impedance output or is in power save mode, the voltage of 3.6V or more must not be applied to prevent the distruction of IC. For correspondence with analog input voltage and output data code, refer to the Output Formula Chart. For the timing, refer to the Timing Chart.
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CXA1977R
15. TTL to CMOS interface In general, VOH of TTL is approximately 3.7V without load, and it is guaranteed to be 2.7V (Min.). However, it is not enough for VOH of TTL to drive VIH of CMOS,because VIH of CMOS is 3.5V (Min.) TTL VOH (Min.) = 2.7V VOL (Max.) = 0.5V CMOS VIH (Min.) = 3.5V (= 0.7VDD) VIL (Max.) = 1.5V (= 0.3VDD)
When TTL output of ADC is made a connection with CMOS logic circuit, pull-up resistance (Rp) is used. (See chart below). The value of Rp is usually from a few thousand ohm to scores of thousand ohm. The Rp (min.) is decided by Supply voltage of CMOS (VDD) and IOL of ADC (= +500A), while the Rp (max.) is decided by required propagation delay (positive edge) and load capacitance. When Vcc is larger than VDD, it is necessary to pay attention to input equivalent circuit of CMOS, because it may happen that VIH goes over the absolute maximum ratings of CMOS and it brings about LATCH-UP to CMOS circuit.
VCC
VDD Rp
ADC
CMOS
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Output Formula Chart 0 1 (OPEN) 0 1 (OPEN) 0 -- 0 -- 0 0 0 1 (OPEN)
ENABLE
0
MINV
1 (OPEN)
LINV
1 (OPEN)
OUTPUT 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 : 11110 0000000 : 01000 0011111 00110 0011111 00100 0011111 00010 0011111 00001 0011111 : 00000 0011111 : 10110 0000000 11000 0000000 11010 0000000 11100 0000000 11111 0000000 0 0 1 1 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 1 0
OF 9 8 7 6 5 4 3 2 1 0 UF OF 9 8 7 6 5 4 3 2 1 0 UF OF 9 8 7 6 5 4 3 2 1 0 UF OF 9 8 7 6 5 4 3 2 1 0 UF (LSB) (MSB) (LSB) (LSB) (MSB) (MSB) (LSB) (MSB) 0 0 0 0 11110 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 Z Z Z Z : Z : Z Z Z Z Z
4V : : : : : : : : : : 2V
1 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 2 3 : 512 : 1019 1020 1021 1022 1023
: 0100000 : 0111111 0111111 0111111 0111111 0111111
: 00000 0111111 : 10110 0100000 11000 0100000 11010 0100000 11100 0100000 11111 0100000
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0: VOLTAGE LEVEL-LOW 1: VOLTAGE LEVEL-HIGH Z: HIGH IMPEDANCE
OF: OVER FLOW UF: UNDER FLOW
CXA1977R
CXA1977R
Timing Chart (1)
N+1 N Sample-and-hold output TH TL N+2 tSH 1.5V tSL
A/D clock
tPWH
tPWL
1/FC
A/D digital output
1.5V
DATA N-1
DATA N
DATA N + 1
tDLH tDHL
TH is the timing of latching result for the comparator of VIN and VREF in the upper comparators. TL is the timing of latching result for the comparator of VIN and VREF in the lower comparators. Timing Chart (2)
Output waveform of 3-state enable and disable time. ( Enable time = tPZL/tPZH, disable time = tPLZ/tPHZ)
ENABLE signal (Low-level enabling)
3V 1.5V tPZL 1.5V tPLZ 4.5V 1.5V tPZH tPHZ 1.5V 0V 0.3V 0.3V 1.5V VOL VOH 1.5V 0V
Waveform 1 Note)
Waveform 2 Note)
Notes) Waveform 1 indicates the output waveform when internal conditions are set to obtain a low level output, with the exception of when output is disabled by means of the ENABLE signal. Waveform 2 indicates the output waveform when internal conditions are set to obtain a high level output, with the exception of when output is disabled by means of the ENABLE signal.
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CXA1977R
Standard Circuit
VREFB
VREFB
VREFT
VREFT
C5 0.1 C4 10
C6 0.1
C8 0.1 C7 0.1
C10 10 C12 0.1 C14 0.1 C13 0.1
36 35 34 33 32 31 30 29 28 27 26 25
N.C.
N.C.
VREFTS
37 N.C. R1 50 VIN 40 VINH R2 50 C3 0.1 C1 0.1 41 N.C. 42 AVCC 43 N.C. 44 AGND 45 DVCC2 46 UNDER 47 OVER 38 N.C. 39 VINL
VREFBS
VREFB
VREFT
VREF3
VREF2
VREF1
DVCC3
DVCC3
N.C.
PS 24
PS ENABLE CLK MINV LINV C11 0.1
ENABLE 23 CLK 22 MINV 21 LINV 20 N.C. 19 DVCC3 18 DGND2 17 DGND1 16 DVCC1 15 DGND1 14 C9 0.1
D0 (LSB)
DGND1
48 DGND1
D9 (MSB)
N.C. 13
N.C.
D1
D2
D3
D4
1
2
3
4
5
6
D5
D6
7
8
9
10 11 12
D7
D8
5V
UNDER
OVER
D0
D1
D4
D5
D2
D3
D6
D7
D8
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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D9
CXA1977R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 0.2 36 37 7.0 0.1 25 24
(8.0)
A 48 1 0.5 0.08 + 0.08 0.18 - 0.03 0.1 0.1 + 0.2 1.5 - 0.1 12 13
(0.22)
+ 0.05 0.127 - 0.02 0.1
0 to 10
0.5 0.2
NOTE: Dimension "" does not include mold protrusion. DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g
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0.5 0.2

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