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PD- 93844B
IRF7901D1
* Co-Pack Dual N-channel HEXFET(R) Power MOSFET and Schottky Diode * Ideal for Synchronous Buck DC-DC Converters Up to 5A Peak Output * Low Conduction Losses * Low Switching Losses * Low Vf Schottky Rectifier
Q1 S ource Q1 Gate PGND 1 2 3 4
Dual FETKYTM
Co-Packaged Dual MOSFET Plus Schottky Diode Device Ratings (Max.Values)
Q1
8 7 6 5 Pwr Vin Pwr Vin Pwr Vout Pwr Vout
Q2 and Schottky
VDS RDS(on) QG Qsw VSD
30V 38 m 10.5 nC 3.8 nC 1.0V
30V 32 m 18.3 nC 9.0 nC 0.52V
SO-8
Q2 Gate
T op View
Description The FETKYTM family of Co-Pack HEXFET(R)MOSFETs and Schottky diodes offers the designer an innovative, board space saving solution for switching regulator and power management applications. Advanced HEXFET(R)MOSFETs combined with low forward drop Schottky results in an extremely efficient device suitable for a wide variety of portable electronics applications. The SO-8 has been modified through a customized leadframe for enhanced thermal characteristics and multiple die capability making it ideal in a variety of power applications. With these improvements, multiple devices can be used in an application with dramatically reduced board space. Internal connections enable easier board layout design with reduced stray inductance. Absolute Maximum Ratings Parameter Drain-Source Voltage Gate-Source Voltage Continuous Output Current (VGS 4.5V) Pulsed Drain Current Power Dissipation Pulsed Source Current Thermal Resistance Parameter Maximum Junction-to-Ambient Maximum Junction-to-Lead RJA RJL Max. 62.5 25 Units C/W C/W TL = 100C Junction & Storage Temperature Range IDM PD TJ, TSTG ISM 24 2.0 -55 to 150 12 W C A TL = 100C Symbol VDS VGS ID IRF7901D1 30 20 6.2 A Units V
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IRF7901D1
Electrical Characteristics
Parameter Drain-to-Source Breakdown Voltage* Static Drain-Source on Resistance* Drain-Source Leakage Gate-Source Leakage Current* Total Gate Charge* Pre-Vth Gate-Source Charge Post-Vth Gate-Source Charge Gate to Drain Charge Switch Charge* (Qgs2 + Qgd) Output Charge* Gate Resistance Input Capacitance Output Capacitance Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time BVDSS RDS(on)
Q1 - Control FET Q2 - Synch FET & Schottky
Min 30 - 1.0 - - I GSS QG cont QG synch QGS1 QGS2 QGD Q sw Q oss RG C iss C oss C rss td(on) tr td(off) tf - - - - - - - - - - - - - - - -
Typ - 28 - - - - 7.6 6.7 2.0 0.5 1.9 2.4 13.5 3.4 780 430 30 7.2 13.8 14.7 8
Max - 38 - 30 0.15 100 10.5 9.0 - - - 3.8 18.0 - - - - - - - -
Min 30 - 1.0 - - - - - - - - - - - - - - - - - -
Typ - 23 - - - - 15.5 13.5 5.5 0.9 4.7 5.6 9.0 4.3 1810 310 110 10.4 16.4 14.6 5.2
Max Units - 32 - 30 4.3 100 21.0 18.3 - - - 9.0 12.3 - - - - - - - - ns pF nC V m V A mA nA
Conditions VGS = 0V, ID = 250A VGS = 4.5V, ID = 5A VDS = VGS, ID = 250A VDS = 24V, VGS = 0 VDS = 24V, VGS = 0, TJ = 125C VGS = 20V VGS = 5V, VDS = 16V, ID = 5A VGS = 5V, VDS= 100mV, ID = 5A VDS = 16V, ID = 5A
Gate Threshold Voltage* VGS(th) I DSS
VDS = 16V, VGS = 0
VDS = 16V, VGS = 0, f = 1MHz VDD = 16V, ID = 5A, VGS = 5V Clamped inductive load See test diagram Fig 17.
Source-Drain Ratings and Characteristics
Q1 Parameter Diode Forward Voltage*k Reverse Recovery Charge

VSD Qrr
Min - -
Typ 0.7 62.3
Max 1.0 -
Q2 & parallel Schottky Min Typ Max Units Conditions - 0.48 0.52 V IS = 1A, VGS = 0V - 8.9 - nC dl/dt = 700A/us VDS = 16V, VGS = 0V, IS = 5A
m Repetitive rating; pulse width limited by max. junction temperature. Pulse width 300 s; duty cycle 2%. When mounted on 1 inch square copper board, t < 10 sec. *
Combined Q1, Q2 IRMS @ Pwr Vout pins. Calculated continuous current based on maximum allowable junction temperature; switching or other losses will decrease RMS current capability When mounted on IRNBPS2 design kit. Measured as device TJ to Pwr leads (Vin & Vout) Devices are 100% tested to these parameters.
2
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IRF7901D1
Power MOSFET Optimization for DC-DC Converters
Table 1 and Table 2 describes the event during the various charge segments and shows an approximation of losses during that period. Table 1 - Control FET Losses Description Segment Losses Conduction Losses associated with MOSFET on time. IRMS is a function of load 2 P COND = I RMS x R DS (on ) current and duty cycle. Loss Gate Drive Losses associated with charging and discharging the gate of the PIN = VG x QG x Loss MOSFET every cycle. Use the control FET QG. Q Switching Losses during the drain voltage and drain current transitions for every full PQGS 2 VIN x IL x GS 2 x Loss cycle. IG Losses occur during the QGS2 and QGD time period and can be simplified by Q PQGD VIN x IL x GD x using Qswitch. IG
PSWITCH VIN x IL Q SW x IG
Output Loss
Losses associated with the QOSS of the device every cycle when the control FET turns on. Losses are caused by both FETs, but are dissipated by the control FET. Table 2 - Synchronous FET Losses Description Losses associated with MOSFET on time. IRMS is a function of load current and duty cycle. Losses associated with charging and discharging the gate of the MOSFET every cycle. Use the Sync FET QG. Generally small enough to ignore except at light loads when the current reverses in the output inductor. Under these conditions various light load power saving techniques are employed by the control IC to maintain switching losses to a negligible level. Losses associated with the QOSS of the device every cycle when the control FET turns on. They are caused by the synchronous FET, but are dissipated in the control FET.
POUTPUT =
QOSS x VIN x 2
Segment Losses
Conduction Loss Gate Drive Loss Switching Loss
PCOND = IRMS x RDSon
2
PIN = VG x QG x
PSWITCH 0
POUTPUT =
QOSS x VIN x 2
Output Loss
Typical Application The performance of the new Dual FETKYTM has been tested in-circuit using IR's new IRNBPS2 "Dual Output Synchronous Buck Design Kit", operating up to 21Vin and 5A peak output current, with operating voltages from 1Vout to 5Vout.
Pin 1 Q1 Source
Pin 5&6 Pwr Vout Shaded area = Dual FETKY
Pin 7&8 Pwr Vin
Q1
Vin
Pin 2 Q1 Gate
Q2
Schottky
Vout
Pin 4 Q2 Gate Pin 3 PGND
Figure 1: Synchronous Buck dc-dc Topology
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IRF7901D1
Typical Application (Contd.) The Dual FETKY integrates all the power semiconductor devices for DC-DC conversion within one SO-8 package, as shown on page 1. The high side control MOSFET (Q1) is optimized for low combined Qsw and RDS(on). The low side synchronous MOSFET (Q2) is optimized for low RDS(on) and high Cdv/dt immunity. The ultra-low Vf schottky diode is internally connected in parallel with the synchronous MOSFET, for improved deadtime efficiency. For ease of circuit board layout, the Dual FETKY has been internally configured such that it represents a functional block for the power device portion of the synchronous buck DC-DC converter. This helps to minimize the external PCB traces compared to a discrete solution. In-Circuit Efficiency The in-circuit efficiency curves for the Dual FETKY are shown in Figure 2 & 3. The Dual FETKY can achieve up to 96.6% and 94.6% peak efficiency for the 5.0V and 3.3V applications respectively, with excellent maximum load efficiency.
IRF7901D1 Dual FETKYTM performance in Synchronous Buck DC-DC for 3.3V out & 5.0V out @ 300kHz, using IRNBPS2 design kit
97%
IRF7901D1 Dual FETKYTM performance in Synchronous Buck DC-DC for 1.0Vout @ 300kHz, using IRNBPS2 design kit
90% 88% 86%
95%
84%
Efficiency (%)
Efficiency (%)
82% 80% 78% 76% 8.4Vin / 1.0Vout 74% 72% 70% 14Vin / 1.0Vout
93%
91%
10.8Vin / 3.3Vout 14Vin / 3.3Vout 21Vin / 3.3Vout 10.8Vin / 5.0Vout 14Vin / 5.0Vout 21Vin / 5.0Vout 1 1.5 2 2.5 3 3.5 4 4.5 5
89%
1.5
2
2.5
3
3.5
4
4.5
5
Output Current (A)
Output Current (A)
Figure 2. IRF7901D1 Dual FETKYTM electrical efficiency at 3.3Vout & 5.0Vout.
Figure 3. IRF7901D1 Dual FETKYTM electrical efficiency at 1.0Vout.
Q1 - Control FET
2.0
Typical Characteristics Q2 - Synchronous FET & Schottky
1.50
R DS(on) , Drain-to-Source On Resistance
R DS(on) , Drain-to-Source On Resistance
ID = 5.0A VGS = 4.5V
ID = 5.0A VGS = 4.5V
1.5
1.25
(Normalized)
(Normalized)
1.0
1.00
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160
0.75 -60 -40 -20 0 20 40 60 80 100 120 140 160
T J , Junction Temperature (C)
T J , Junction Temperature (C)
Figure 4. Normalized On-Resistance vs Junction Temperature
Figure 5. Normalized On-Resistance vs Junction Temperature
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IRF7901D1
Q1 - Control FET
6.0
Typical Characteristics Q2 - Synchronous FET & Schottky
6.0
ID= 5.0A
ID= 5.0A VDS = 16V
VGS, Gate-to-Source Voltage (V)
4.0
VGS, Gate-to-Source Voltage (V)
4.0 6.0 8.0
VDS = 16V
4.0
2.0
2.0
0.0 0.0 2.0
0.0 0 4 8 12 16
QG, Total Gate Charge (nC)
QG, Total Gate Charge (nC)
Figure 6. Gate-to-Source Voltage vs Typical Gate Charge
RDS(on) , Drain-to -Source On Resistance ( )
0.05
Figure 7. Gate-to-Source Voltage vs Typical Gate Charge
RDS(on) , Drain-to -Source On Resistance ()
0.030
0.025
0.04
0.020
ID = 5.0A
0.03
ID = 5.0A
0.015
0.02 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
0.010 4.0 5.0 6.0 7.0 8.0 9.0 10.0
VGS, Gate -to -Source Voltage (V)
VGS, Gate -to -Source Voltage (V)
Figure 8. Typical R (on) vs Gate-to-Source Voltage
DS
Figure 9. Typical R (on) vs Gate-to-Source Voltage
DS
30
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
20
VGS 10V 8.0V 4.5V 3.5V 3.0V 2.5V 2.0V BOTTOM 0.0V TOP
50
40
30
VGS 10V 8.0V 4.5V 3.5V 3.0V 2.5V 2.0V BOTTOM 0.0V TOP
20 0.0V 250s PULSE WIDTH Tj = 25C 0.0 0.4 0.8 1.2
10 0.0V 250s PULSE WIDTH Tj = 25C 0.0 0.4 0.8 1.2 1.6 2.0
10
0
0
VSD, Source-To-Drain Voltage (V) Voltage (V) DS , Drain-toSource
VSD, Source-To-Drain Voltage (V) VDS , Drain-toSource Voltage (V)
Figure 10. Typical Reverse Output Characteristics
Figure 11. Typical Reverse Output Characteristics
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IRF7901D1
Q1 - Control FET
30
VGS 10V 8.0V 4.5V 3.5V 3.0V 2.5V 2.0V BOTTOM 0.0V TOP
Typical Characteristics Q2 - Synchronous FET & Schottky
50
VGS 10V 8.0V 4.5V 3.5V 3.0V 2.5V 2.0V BOTTOM 0.0V TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
40
20
30
20
10 0.0V 250s PULSE WIDTH Tj = 150C 0.0 0.4 0.8 1.2 1.6 2.0
10
0.0V 250s PULSE WIDTH Tj = 150C 0.0 0.4 0.8 1.2
0
0
VSD, Source-To-Drain Voltage (V) VDS , Drain-toSource Voltage (V)
VSD, Source-To-Drain Voltage (V) VDS , Drain-toSource Voltage (V)
Figure 12. Typical Reverse Output Characteristics
100.00
Figure 13. Typical Reverse Output Characteristics
100.00
ID, Drain-to-Source Current ()
T J = 150C
10.00
ID, Drain-to-Source Current ()
10.00
T J = 150C
1.00
1.00
TJ = 25C VDS = 10V 250s PULSE WIDTH
T J = 25C VDS = 10V 250s PULSE WIDTH
2.5 3.0 3.5 4.0 4.5
0.10 2.0 2.5 3.0
0.10 3.5 4.0 4.5
VGS, Gate-to-Source Voltage (V)
VGS, Gate-to-Source Voltage (V)
Figure 14. Typical Transfer Characteristic
100
Figure 15. Typical Transfer Characteristic
Thermal Response (Z thJA )
D = 0.50 0.20 10 0.10 0.05 0.02 1 0.01 PDM t1 t2 SINGLE PULSE (THERMAL RESPONSE) 0.1 0.00001 0.0001 0.001 0.01 0.1 Notes: 1. Dutyfactor D = t 1/ t 2 2. PeakT J = P DM x Z thJA + T A 1 10 100
t1 , Rectangular Pulse Duration (sec)
Figure 16. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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IRF7901D1
Figure 17. Clamped Inductive Load Test Diagram and Switching waveform.
SO-8 Package Outline
Part Marking Information
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IRF7901D1
SO-8 Tape & Reel Information
Dimensions are shown in millimeters (inches)
T E R M IN A L N U M B E R 1
1 2.3 ( .4 84 ) 1 1.7 ( .4 61 )
8 .1 ( .31 8 ) 7 .9 ( .31 2 )
F E E D D IR E C T IO N
33 0.0 0 (12 .9 92 ) MAX.
14 .4 0 ( .5 6 6 ) 12 .4 0 ( .4 8 8 ) NOTE S : 1 . C O N T R O L LIN G D IM E N S IO N : M IL L IM E T E R . 2 . O U T L IN E C O N FO R M S T O E IA -48 1 & E IA -54 1.
Data and specifications subject to change without notice. This product has been designed and qualified for the consumer market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact informatin.9/01
8
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