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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75P218
4-BIT SINGLE-CHIP MICROCOMPUTER
The PD75P218 is a one-time PROM version that can be written to only once or an EPROM version that allows program writing, erasing, and rewriting, of the PD75218 Note. Since the program can be written by the user, the PD75P218 is suitable for preproduction use during system development, or limited production. Read this material together with the PD75218 materials. Note Under development
FEATURES
* * * * * * *
PD75218 compatible
On-chip 16K-byte mode/32K-byte mode switching function Operates at the same power supply voltage range (2.7 to 6.0 V) as the mask ROM version PD75218. 32640 x 8 bits of PROM 1024 x 4 bits of RAM No pull-down resistor for Port 6 High breakdown voltage display output * S0 to S8, T0 to T9 : On-chip pull-down resistor * S9, T10 to T15 : Open drain
* No power-on reset circuit
Caution No mask-option pull-down resistor is provided.
ORDERING INFORMATION
Part Number Package 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (14 x 20 mm) 64-pin ceramic LCC with window (14 x 20 mm) Quality Grade Standard Standard Standard
PD75P218CW PD75P218GF-3BR PD75P218KB
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The word "PROM" in this document refers to the common parts of the one-time PROM products and EPROM products.
The information in this document is subject to change without notice. Document No. IC-2541A (O.D. No. IC-7962A) Date Published March 1993 P Printed in Japan
1989 (c) NEC CORPORATION 1991
PD75P218
PIN CONFIGURATION (Top View)
S3 S2 S1 S0 P00/INT4 P01/SCK P02/SO P03/SI P10/INT0/VPP P11/INT1 P12/INT2 P13/ TI0 P20 P21 P22 P23/BUZ P30/MD0 P31/MD1 P32/MD2 P33/MD3 P60 P61 P62 P63 P40 P41 P42 P43 PPO X1 X2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD S4 S5 S6 S7 S8 S9 NC VLOAD T15/S10 T14/S11 T13/S12/PH0 T12/S13/PH1 T11/S14/PH2 T10/S15/PH3 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 RESET P53 P52 P51 P50 XT2 XT1
P10/INT0/VPP
P12/INT2
P11/INT1
PD75P218CW mPD75P218CW
P33/MD3
P32/MD2
P31/MD1
P30/MD0
P23/BUZ
P13/TI0
P40
P63
P62
P61
P60
P22
P21
P41 P42 P43 PPO X1 X2 VSS XT1 XT2 P50 P51 P52 P53
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 31 30 29 28 27 26 25 24 23 22 21 20 9 10 11 12 13 14 15 16 17 18 19
P20
P02/SO
P03/SI
P01/SCK P00/INT4 S0 S1 S2 S3 VDD S4 S5 S6 S7 S8 S9
mPD75P218GF-3BR PD75P218GF-3BR mPD75P218KB PD75P218KB
RESET
VLOAD
T14/S11
T10/S15/PH3
T11/S14/PH2
T12/S13/PH1
2
T13/S12/PH0
T15/S10
NC
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
BLOCK DIAGRAM
BASIC INTERVAL TIMER INTBT TI0/P13 TIMER/EVENT COUNTER #0 INTT0 PROGRAM COUNTER (15) ALU CY SP (8) SBS (2)
PORT 0 PORT 1
4 4
P00 - P03 P10 - P13
PORT 2
4
P20 - P23 P30/MD0 P33/MD3 P40 - P43
BANK PORT 3 4
PORT 4 PRO TIMER/PULSE GENERATOR INTTPG SI/P03 SO/P02 SCK/P01 INTSIO SERIAL INTERFACE PROM PROGRAM MEMORY 32640 *x88BITS BITS GENERAL REG. PORT 5
4
4
P50 - P53
PORT 6 DECODE AND CONTROL RAM DATA MEMORY 1024 * 4 BITS 1024 x 4 BITS
4
P60 - P63
10
T0 - T9 T10/S15/PH3 T13/S12/PH0 T14/S11,T15/S10
4 INT0/P10/VPP INT1/P11 INT2/P12 INT4/P00 INTERRUPT CONTROL fx/2N INTW WATCH TIMER CLOCK DIVIDER SYSTEM CLOCK GENERATOR SUB MAIN STAND BY CONTROL CPU CLOCK F INTKS PORTH NC VDD VSS RESET 4 FIP CONTROLLER/ DRIVER
2
10
S0 - S9 VLOAD
PD75P218
BUZ/P23
XT1 XT2 X1 X2
PH0 - PH3
3
PD75P218
1.
1.1
PIN FUNCTIONS
PORT PINS
Input/ output Input I/O I/O Input Input Shared pin INT4 SCK SO SI INT0/VPP INT1 INT2 TI0 I/O - - - BUZ I/O MD0 - MD3 Programmable 4-bit I/O port (PORT3). I/O can be specified bit by bit. 4-bit I/O port (PORT4). Can directly drive LEDs. Data input/output pins for the PROM write and verify (Four low-order bits). Data input/output pins for the PROM write and verify (Four high-order bits). x Input 4-bit I/O port (PORT2). x Input 4-bit input port (PORT1). With noise elimination function Input Function 4-bit input port (PORT0). 8-bit I/O x When reset Input
Pin name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 - P33
P40 - P43
I/O
-
Input
P50 - P53
I/O
-
4-bit I/O port (PORT5). Can directly drive LEDs.
Input
P60 - P63
I/O
-
Programmable 4-bit I/O port (PORT6). I/O can be specified bit by bit. Suitable for key input. 4-bit P-ch open drain high breakdown voltage large current output port (PORTH). Can directly drive LEDs.
Input
PH0 PH1 PH2 PH3
Output
T13/S12 T12/S13 T11/S14 T10/S15
x
High impedance
4
PD75P218
1.2 NON-PORT PINS
Input/ output Shared pin - Note 1 Function High breakdown voltage large current output pin for digit output High breakdown voltage large current output pin for digit/segment output The remainder of the pins can be used as PORTH. High breakdown voltage large current output pin for digit/segment output Static output is also available. High breakdown voltage output pin for segment output Static output is also available. Note 1 High breakdown voltage output pin for segment output Low level When reset Low level
Pin name T0 - T9
T10/S15 T13/S12
Output
PH3 - PH0
Note 2
High impedance
T14/S11, T15/S10
-
S9
S0 - S8
PPO
Output
-
Output for receiving pulse signal for timer/pulse generator
High impedance
TI0
Input
P13
Input for receiving external event pulse signal for timer/ event counter Serial clock I/O Serial data output or serial data I/O Serial data input or normal input Edge detection vectored interrupt input (either rising edge or falling edge detection) Edge detection vectored interrupt input with noise elimination (detection edge selectable) Edge detection testable input (rising edge detection) Fixed frequency output pin (for buzzer or system clock trimming) Crystal/ceramic resonator connection for main system clock generation. When external clock is used, it is applied to X1, and its reserve phase signal is applied to X2. Crystal connection for subsystem clock generation. When external clock is used, it is applied to XT1, and XT2 is open. System reset input (low level active) Operation mode selection pins during the PROM write/verify cycles +12.5 V is applied as the programming voltage during the PROM write/verify cycles Pull-down resistor connection pin of FIP(R) controller/driver Positive power supply. +6 V is applied as the programming voltage during the PROM write/verify cycles GND potential No connection Input Input Input Input
SCK SO SI INT4
I/O I/O Input Input
P01 P02 P03 P00
INT0 INT1 INT2 BUZ X1, X2
Input
P10/VPP P11
Input I/O
P12 P23 -
XT1, XT2
-
RESET MD0 - MD3 VPP
Input I/O
- P30 - P33 P10/INT0
VLOAD VDD
- -
VSS NC
Note 3
- -
Note 1. On-chip pull-down resistor 2. Open drain output 3. When using a printed board with a PD75216A, 75217, or 75218, connect the NC pin to the VPRE.
5
PD75P218
1.3 PIN INPUT/OUTPUT CIRCUITS
The input/output circuit diagram for each PD75P218 pin is shown in Fig. 1-1 in a simplified manner. For the correspondence of the each pin and input/output type number, refer to Table 1-1. Table 1-1 Pins and Input/Output Type Numbers
Pin name P00/INT4 P01/SCK P02/SO P03 - SI P10/INT0/VPP P11/INT1, P12/INT2 P13 - TI0 P20 - P22 P23/BUZ P30/MD0 - P33/MD3 P40 - P43 E E E I/O type B F G B B Pin name P50 - P53 P60 - P63 T0 - T9 T10/S15/PH3 - T13/S12/PH0 T14/S11, T15/S10 S0 - S8 S9 PPO RESET VLOAD I/O type E E I-E I-D I-D I-E I-D D B I-E
Remark I/O type enclosed with a circle indicates Schmitt triggered input.
6
PD75P218
Fig. 1-1 Pin Input/Output Circuit
TYPE A VDD Data Type D P-ch IN Output disable IN/OUT TYPE F
N-ch
Type B
CMOS input buffer
I/O circuit consisting of push-pull output of Type D and Schmitt trigger of Type B TYPE G VDD P-ch output disable Data
TYPE B
P-ch IN/OUT N-ch
IN
Type B Schmitt trigger input with hysteresis I/O circuit that can switch the push-pull output or N-ch open drain output (off for P-ch) TYPE I-D P-ch VDD OUT Data Output disable N-ch N-ch OUT Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch) TYPE E Data Type D Output disable IN/OUT Data TYPE I-E VDD VDD P-ch P-ch VDD
TYPE D VDD Data
P-ch
P-ch OUT Pull-down resistor VLOAD
N-ch Type A
I/O circuit consisting of push-pull output of Type D and input buffer of Type A
7
PD75P218
1.4 PROCESSING OF UNUSED PINS Table 1-2 Recommended Connection of Unused Pins
Pin name P00/INT4 P01/SCK P02/SO P03/SI P10/INT0/VPP P11/INT1, P12/INT2 P13/T10 P20 - P22 P23/BUZ P30/MD0 - P33/MD3 P40 - P43 P50 - P53 P60 - P63 PPO S0 - S9 T15/S10, T14/S11 T0 - T9 T10/S15/PH3 - T13/S12/PH0 XT1 XT2 VLOAD when no on-chip load resistor Connect to VSS or VDD Open Connect to VSS or VDD Open Input state: Connect to VSS or VDD Output state: Open Connect to VSS Recommended connection Connect to VSS Connect to VSS or VDD
8
PD75P218
2. DIFFERENCES BETWEEN THE PD75P218 AND THE PD75P216A, 75217, 75218
Part number Item ROM One-time PROM 16K x 8 512 x 4 segments digits P60 - P63 S0 - S8, T0 - T9 SD9, T10 - T15 Not available On-chip Not available (open drain) INT0/VPP (common use) MD0 - MD3 (common use) Not available (NC) -10 to +70 C 5 V 10 % Bank 0 Bank 0 - 2 Not available Mask ROM 24K x 8 768 x 4 9 - 16 segments 9 - 16 digits Mask-option Mask-option Mask-option Not available On-chip Not available (open drain) INT0/VPP (common use) MD0 - MD3 (common use) Not available (NC) -40 to +70 C Mask ROM 32K x 8 1024 x 4 PROM 32K x 8
PD75P216A
PD75217
PD75218
Note
PD75P218
RAM FIP controller/driver Pull-down resistors
Pin connection
P10
INT0 (common use)
P30 - P33
No common use
VPRE Operating ambient temperature Power supply voltage Stack area 16K-byte mode/32K-byte mode switching function Package
Available -40 to +85 C
2.7 - 6.0 V Bank 0 - 3 Available
64-pin plastic shrink DIP
64-pin plastic shrink DIP 64-pin plastic QFP
64-pin plastic shrink DIP 64-pin plastic QFP 64-pin ceramic LCC with window
Note Under development
9
PD75P218
3. 16K-BYTE MODE/32K-BYTE MODE SWITCHING FUNCTION
16K-byte mode or 32K-byte mode can be selected by setting the stack bank selection register (SBS). The PD75P218 can then be used to evaluate the PD75216A, PD75217, and PD75218. 3.1 DIFFERENCES BETWEEN 16K-BYTE MODE AND 32K-BYTE MODE Table 3-1 16K-byte Mode and 32K-byte Mode Differences
Item Stack operation at subroutine call instruction execution Stack area CALL instruction TCALL instruction by GETI CALLF instruction BRA instruction CALLA instruction Program counter bit 14 0 fixed Corresponds to branch instruction, call instruction 2 machine cycles Undefined operation 3 machine cycles Normal operation 16K-byte Mode 2-byte stack 32K-byte Mode 3-byte stack
Bank 0 3 machine cycles
Bank 0 to bank 3 4 machine cycles
Corresponding mask ROM version
PD75216A (S-DIP, QFP)
PD75217 (S-DIP, QFP) PD75218 (S-DIP, QFP)
10
PD75P218
3.2 16K-BYTE MODE AND 32K-BYTE MODE SWITCHING
16K-byte mode and 32K-byte mode are switched by the stack bank selection register. The stack bank selection register format is shown in Fig. 3-1. The stack bank selection register is set by 4-bit memory manipulation instruction. RESET input sets bit 3 of the stack bank selection register to "1" and changes from 32K-byte mode to 16K-byte mode. When 16K-byte mode is used, manipulating the stack bank selection register is unnecessary. When 32K-byte mode is used, the stack bank selection register must always be initialized to 00xxB
Note 1
at the beginning of the program.
Fig. 3-1 Stack Bank Selection Register Format
Address F84H
3 SBS3
2 SBS2
1 SBS1
0 SBS0
Symbol SBS
Stack area specification 0 0 1 1 0 1 0 1 Memory bank 0 Memory bank 1 Memory bank 2 Memory bank 3
0
Be sure to write 0 to bit 2.
Mode change specification 0 1 32K-byte mode 16K-byte mode Note 2
Caution When using 32K-byte mode, execute a subroutine call instruction and an interrupt enable instruction after the stack bank selection register is set after RESET input. Notes 1. Set the desired value in xx. 2. When the 16K-byte mode is used after RESET input, the stack bank selection register does not have to be manipulated.
11
PD75P218
4. PROM (PROGRAM MEMORY) WRITE AND VERIFY
The PROM contained in the PD75P218 is one-time PROM or EPROM for writing, erasing, and rewriting. Table 4-1 shows the pin functions during the write and verify cycles. Note that it is not necessary to enter an address, because the address is updated by pulsing the X1 clock pins. Table 4-1 PROM Write and Verify Pin Functions
Pin Name VPP X1, X2 Function Normally 2.7 to 6 V; 12.5 V is applied during the write/verify cycles. After a write/verify write, the X1 and X2 clock pins are pulsed. The inverted signal of the X1 should be input to the X2. Note that these pins are also pulsed during a read. Operation mode selection pins during the write/verify cycles 8-bit data input/output pins during the write/verify cycles
MD0 - MD3 P40 - P43 (Four low-order bits) P50 - P53 (Four high-order bits) VDD
Supply voltage Normally 2.7 to 6 V; 6 V is applied during the write/verify cycles.
Cautions 1. The pins not used for write and verify should be processed as follows. Port 0 - 2, Port 6, XT1 S0 - S9, T0 - T15 RESET, PPO, VLOAD

**** Connect to GND (directly connectable)
XT2 ***************************************** Open 2. An opaque film should be placed over the UV erase window of the PD75P218KB except when erasing the EPROM contents. 3. The PD75P218CW/GF does not have a UV erase window, thus the PROM contents cannot be erased with ultraviolet ray. 4.1 PROM WRITE AND VERIFY OPERATION
When +6 V and +12.5 V are applied to the VDD and VPP pins, respectively, the PROM is placed in the write/ verify mode. The operation is selected by the MD0 to MD3 pins, as shown in Table 4-2. Table 4-2 PROM Write and Verify Operation Mode
Operation Mode Specification Operation Mode VPP +12.5 V VDD +6 V MD0 H L L H MD1 L H L x MD2 H H H H MD3 L H H H Clear program memory address to 0 Write mode Verify mode Program inhibit
x: Don't care.
12
PD75P218
4.2 PROM WRITE/VERIFY PROCEDURE
PROMs can be written at high speed using the following procedure: (see the following figure) (1) Connect unused pins to VSS. Set the X1 pin low. (2) Supply 5 volts to the VDD and VPP pins. (3) Wait for 10 s. (4) Select the zero clear program memory address mode. (5) Supply 6 volts to the VDD and 12.5 volts to the VPP pins. (6) Select the program inhibit mode. (7) Write data in the 1 ms write mode. (8) Select the program inhibit mode. (9) Select the verify mode. If the data is correct, proceed to step (10). If not, repeat steps (7), (8) and (9). (10) Perform one additional write (duration of 1 ms x number of writes at (7) to (9)). (11) Select the program inhibit mode. (12) Apply four pulses to the X1 pin to increment the program memory address by one. (13) Repeat steps (7) to (12) until the end address is reached. (14) Select the zero clear program memory address mode. (15) Return the VDD and VPP pins back to + 5 volts. (16) Turn off the power. Fig. 4-1 PROM Write Timing
X repetition Address increment
Write
Verify
Additional write
VPP VPP VDD
VDD+1 VDD VDD
X1
P40 - P43 P50 - P53
Input data
Output data
Input data
MD0 (P30)
MD1 (P31)
MD2 (P32)
MD3 (P33)
X: number of writes performed at (7) to (9)
13
PD75P218
4.3 PROM READ PROCEDURE
The PROM contents can be read in the verify mode by using the following procedure: (see the following figure) (1) Connect unused pins to VSS. Set the X1 pin low. (2) Supply 5 volts to the VDD and VPP pins. (3) Wait for 10 s. (4) Select the clear program memory address mode. (5) Supply 6 volts to the VDD and 12.5 volts to the VPP pins. (6) Select the program inhibit mode. (7) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored in one address. (8) Select the program inhibit mode. (9) Select the clear program memory address mode. (10) Return the VDD and VPP pins back to + 5 volts. (11) Turn off the power. Fig. 4-2 PROM Read Timing
VPP VPP VDD
VDD+1 VDD VDD
X1
P40 - P43 P50 - P53
Output data
Output data
MD0 (P30)
MD1 (P31)
"L"
MD2 (P32)
MD3 (P33)
14
PD75P218
4.4 ERASING METHOD
The program data contents of the PD75P218KB are erased by lighting ultraviolet ray whose wavelength is about 250 nm on the window. The minimum amount of radiation exposure required to erase the contents completely is 15 W*s/cm2 (ultraviolet ray strength times erase time). This corresponds to about 15 to 20 minutes when using a UV lamp on the market (wavelength 254 nm, strength 12 mW/cm2). Cautions 1. The programmed data contents may also be erased if the uncovered window is exposed to direct sunlight or a fluorescent light even for several hours. Thus, to protect the data contents, cover the window with an opaque film. NEC attaches quality-tested shading film to the UV EPROM products for shipping. 2. For normal EPROM erase, the distance between the light source and the window should be 2.5 cm or less. Remark The erase time may be prolonged if the UV lamp is old or if the device window is dirty.
15
PD75P218
5. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (Ta = 25 C)
Parameter Power supply voltage Symbol VDD VLOAD VPP Input voltage Output voltage VI VO VOD High-level output current IOH Other than display pins Display pins Single pin; other than display pins Single pin; S0 - S9 Single pin; T0 - T15 Total of all pins other than display Total of all display pins Low-level output current Operating temperature Storage temperature IOL Single pin Total of all pins Topt Tstg Conditions Ratings -0.3 to +7.0 VDD - 40 to VDD + 0.3 -0.3 to +13.5 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 VDD - 40 to VDD + 0.3 -15 -15 -30 -20 -120 17 60 -40 to +70 -65 to +150 Unit V V V V V V mA mA mA mA mA mA mA C C
Operating Power Supply Voltage (Ta = -40 to +70 C)
Parameter CPU
Note 1
Conditions
MIN.
Note 2
MAX. 6.0 6.0 6.0 6.0
Unit V V V V
Display controller Timer/pulse generator Other hardwares
Note 1
4.5 4.5 2.7
Notes 1. The CPU does not include the system clock oscillator, the display controller, or the timer/pulse generator. 2. Varies according to the cycle time. See AC Characteristics.
16
PD75P218
Main System Clock Configurations (Ta = -40 to +70 C, V DD = 2.7 to 6.0 V)
Resonator Ceramic resonator Recommended constants Parameter
Note 1
Conditions VDD = Oscillator operating voltage range After VDD reaches the minimum oscillator operating voltage range
MIN. 2.0
TYP.
MAX. 6.2
Unit MHz
X1
X2
Oscillation (fXX) frequency
Note 2
4
ms
C1
C2
Oscillation stabilization time
Note 1
Crystal resonator
2.0
4.19
6.2
MHz
X1
X2
Oscillation frequency (fXX)
Note 2
VDD = 4.5 to 6.0 V
10 30 2.0 6.2
ms ms MHz
C1
C2
Oscillation stabilization time
Note 1
External clock
X1
X2
X1 input frequency (fX) X1 input highand low-level width (tXH, tXL) 81 250 ns
mPD74HCU04
Subsystem Clock Configurations (Ta = -40 to +70 C, V DD = 2.7 to 6.0 V)
Resonator Crystal resonator Recommended constants Parameter
Note 1
Conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
XT1
XT2 330 kW
Oscillation frequency (fXT)
Note 2
VDD = 4.5 to 6.0 V
1.0
2 10
s s kHz
C3
C4
Oscillation stabilization time XT1 input frequency (fXT) 32
External clock
100
XT1
XT2 Open
XT1 input highand low-level width (tXTH, tXTL)
5
15
s
Notes 1. The oscillator frequency and input frequency indicate only the oscillator characteristics. Refer to the AC Characteristics for the instruction execution time. 2. The oscillation stabilization time is the time required for the oscillation to stabilize after VDD is applied and reaches the VDD spec or after STOP mode is released. Capacitance (Ta = 25 C, V DD = 0 V)
Parameter Input capacitance Output capacitance Other than display output Display output Input/Output capacitance CIO Symbol CIN COUT f = 1 MHz Unmeasured pins returned to 0 V Conditions MIN. TYP. MAX. 15 15 Unit pF pF
35 15
pF pF
17
PD75P218
Recommended Oscillation Circuit Constants Main System Clock: Ceramic Resonator (Ta = -40 to +70 C)
Frequency (MHz) 2.00 - 2.44 Capacitance (pF) MIN. 30 On-chip 2.45 - 3.50 30 On-chip 2.51 - 6.00 30 On-chip 2.45 - 3.50 30 On-chip 2.51 - 6.00 30 On-chip 2.0 4.0 4.19 6.0 47 33 MAX. 30 On-chip 30 On-chip 30 On-chip 30 On-chip 30 On-chip 47 33 2.7 6.0 3.3 3.0 Oscillation voltage (V) MIN. 2.7 MAX. 6.0
Manufacturer Murata
Part number CSAxxxMG CSTxxxMT CSAxxxMG093 CSTxxxMGW093 CSAxxxMGU CSTxxxMGWU CSAxxxMG CSTxxxMGW CSAxxxMG CSTxxxMGW
Kyocera
KBR - 2.0MS KBR - 4.0MWS KBR - 4.19MWS KBR - 6.0MWS
18
PD75P218
DC Characteristics (Ta = -40 to +70 C, V DD = 2.7 to 6.0 V)
Parameter High-level input voltage Symbol VIH1 VIH2 VIH3 VIH4 Conditions All except ports 0, 1, 6; X1, X2, XT1, RESET Port 0, 1, RESET X1, X2, XT1 Port 6 VDD = 4.5 to 6.0 V MIN. 0.7VDD 0.75VDD VDD - 0.4 0.65VDD 0.7VDD Low-level input voltage VIL1 VIL2 VIL3 High-level output voltage VOH All except ports 0, 1, 6; X1, X2, XT1, RESET Port 0, 1, 6, RESET X1, X2, XT1 All outputs 0 0 0 VDD = 4.5 to 6.0 V, IOH = -1 mA VDD - 1.0 IOH = -100 A Low-level output voltage VOL Port 4, 5 All outputs VDD = 4.5 to 6.0 V, IOL = 15 mA VDD = 4.5 to 6.0 V, IOL = 1.6 mA IOL = 400 A High-level input leakage current Low-level input leakage current High-level output leakage current Low-level output leakage current ILOL2 Display output current IOD ILOL1 All except display outputs Display outputs S0-S9 T0-T15 On-chip pull-down resistor
Note 1
TYP.
MAX. VDD VDD VDD VDD VDD 0.3VDD 0.2VDD 0.4
Unit V V V V V V V V V V
VDD - 0.5 0.4 2.0 0.4 0.5 3 20
V V V
ILIH1 ILIH2 ILIL1 ILIL2 ILOH
All except X1, X2, XT1 X1, X2, XT1 All except X1, X2, XT1 X1, X2, XT1 All outputs
VIN = VDD
A A A A A A A
mA mA
VIN = 0 V
-3 -20
VOUT = VDD
3
VOUT = 0 V
-3
VOUT = VLOAD = VDD - 35 V VDD = 4.5 to 6.0 V VOD = VDD - 2 V VOD - VLOAD = 35 V VDD = 5 V 10 % VDD = 3 V 10 % HALT mode
Note 2 Note 3
-10 -3 -15 25 -5.5 -22 70 6.5 0.85 1350 450 4.0 0.55 900 300 100 20 5 0.5 0.1 135 18.0 2.5 4000 1350 12.0 1.5 2700 900 300 60 15 20 10
RL IDD1
Display outputs 6.0 MHz crystal oscillator
k mA mA
Power supply current IDD2
VDD = 5 V 10 % VDD = 3 V 10 %
A A
mA mA
IDD1
4.19 MHz crystal oscillator C1 = C2 = 15 pF
VDD = 5 V 10 % VDD = 3 V 10 % HALT mode
Note 2 Note 3
IDD2
VDD = 5 V 10 % VDD = 3 V 10 %
A A A A A A A
IDD3 IDD4 32kHz crystal oscillator
Note 4
VDD = 3 V 10 % HALT mode STOP mode VDD = 3 V 10 % VDD = 3 V 10 %
IDD5
XT1 = 0 V STOP mode
VDD = 5 V 10 % VDD = 3 V 10 %
Notes 1. Does not include pull-down resistor current. 2. Value during high-speed operation and when the processor clock control (PCC) register is set to 0011. 3. Value during low-speed operation and when the PCC register is set to 0000. 4. Value when the system clock control register (SCC) is set to 1001, generation of the main system clock pulse is stopped, and the CPU is operated by the subsystem clock pulse.
19
PD75P218
AC Characteristics (Ta = -40 to +70 C, V DD = 2.7 to 6.0 V)
Parameter
Note 1
Symbol tCY
Conditions Main system clock Subsystem clock VDD = 4.5 to 6.0 V
MIN. 0.67 2.6 114
TYP.
MAX. 32 32
Unit
s s s
CPU clock cycle time (minimum instruction execution time = 1 machine cycle) TI0 input frequency fTI
122
125
VDD = 4.5 to 6.0 V
0 0
0.6 165
MHz kHz
TI0 input low- and high-level width SCK cycle time
tTIH, tTIL tKCY
VDD = 4.5 to 6.0 V
0.83 3
s s s s s s s
ns
VDD = 4.5 to 6.0 V
Input Output Input Output
0.8 0.95 3.2 3.8 0.4
SCK low- and high-level width
tKH, tKL
VDD = 4.5 to 6.0 V
Input
Output tKCY/2-50 Input 1.6
s
ns ns ns 300 1000 ns ns
Output tKCY/2-150 SI setup time (to SCK ) SI hold time (from SCK ) SCK SO output delay time Interrupt inputs low- and high-level width tSIK tKSI tKSO VDD = 4.5 to 6.0 V 100 400
tINTH, tINTL
INT0 INT1 INT2,4
Note 2
s s s s
2tCY 10 10
RESET low-level width
tRSL
20
PD75P218
Notes 1. The CPU clock () cycle time is determined by the oscillator frequency of the connected resonator, the system clock control register (SCC), and the processor clock control register (PCC). The right chart shows the cycle time tCY characteristics for power supply voltage
Cycle time tCY ( m s)
40 32 30 6 5 4 3
tCY vs VDD
(Main system clock)
VDD during the main system clock operation. 2. 2tCY or 128/fXX, depending on the setting of the interrupt mode register (IM0).
Guaranteed operating range
2
1
0.5
0
1
2
3
4
5
6
Power supply voltage VDD (V)
21
PD75P218
AC Timing Test Points (Except X1, XT1)
0.75 VDD Test points 0.2 VDD
0.75 VDD 0.2 VDD
Clock Timing
1/fX tXL tXH
X1 input
VDD - 0.4 V 0.4 V
1/fXT tXTL tXTH
XT1 input
VDD - 0.4 V 0.4 V
TI0 Timing
1/fT1 tTIL tTIH
TI0
22
PD75P218
Serial Transfer Timing
tKCY tKL tKH
SCK
tSIK
tKSI
SI
Input data
tKSO
SO
Output data
Interrupt Input Timing
tINTL
tINTH
INT0, 1, 2, 4
RESET Input Timing
tRSL
RESET
23
PD75P218
Data Memory STOP Mode Low Voltage Data Retention Characteristics (Ta = -40 to +70 C)
Parameter Data retention voltage Data retention current
Note 1
Symbol VDDDR IDDDR tSREL tWAIT
Conditions
MIN. 2.0
TYP.
MAX. 6.0
Unit V
VDDDR = 2.0 V 0 Release by RESET input Release by interrupt request
0.1
10
A s
Release signal SET time Oscillation stabilization time Note 2
217/fx
Note 3
ms ms
Notes 1. Does not include pull-down resistor current. 2. The oscillation stabilization WAIT time is the time during which the CPU operation is stopped to prevent unstable operation while the oscillation is started. 3. The WAIT time depends on the setting of the basic interval timer mode register (BTM) according to the following table.
WAIT time BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 (fXX = 6.0 MHz) 0 1 1 1 220/fXX 217/fXX 215/fXX 213/fXX (approx. 175 ms) (approx. 21.8 ms) (approx. 5.46 ms) (approx. 1.37 ms) (fXX = 4.19 MHz) 220/fXX 217/fXX 215/fXX 213/fXX (approx. 250 ms) (approx. 31.3 ms) (approx. 7.82 ms) (approx. 1.95 ms)
Data Retention Timing (STOP mode is released by RESET input)
Internal reset operation HALT mode STOP mode Data retention mode Operation mode
VDD VDDDR Execution of STOP instruction RESET
tSREL
tWAIT
Data Retention Timing (STOP mode is released by interrupt signal)
HALT mode STOP mode Data retention mode Operation mode
VDD VDDDR Execution of STOP mode Standby release signal (Interrupt request)
tSREL
tWAIT
24
PD75P218
DC Programming Characteristics (Ta = 25 5 C, V DD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
Parameter High-level input voltage Symbol VIH1 VIH2 Low-level input voltage VIL1 VIL2 Input leakage current High-level output voltage Low-level output voltage VDD power supply current VPP power supply current ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Conditions All except X1, X2 X1, X2 All except X1, X2 X1, X2 VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD - 1.0 0.4 30 30 MIN. 0.7VDD VDD - 0.5 0 0 TYP. MAX. VDD VDD 0.3VDD 0.4 10 Unit V V V V
A
V V mA mA
Cautions 1. 2.
VPP must not exceed +13.5 V, including overshoot. VDD is to be applied prior to VPP and to be removed after VPP is removed.
AC Programming Characteristics (Ta = 25 5 C, V DD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
Parameter Address setup time Note 2 (to MD0 ) MD1 setup time Data setup time (to MD0 ) (to MD0 ) Symbol tAS TM1S tDS TAH tDH tDF tVPS tVDS tPW tOPW tM0S tDV tM1H tM1R tPCR tXH, tXL fX tI (to MD1 ) (from MD1 ) (to MD0 ) tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR
Note 1
Conditions
MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2
TYP.
MAX.
Unit
tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR - - - - - - - tACC tOH - - During program read cycle During program read cycle During program read cycle During program read cycle During program read cycle MD0 = MD1 = VIL tM1H + tM1R 50 s
s s s s s
130 ns
Address hold time Note 2 (from MD0 ) Data hold time (from MD0 )
MD0 data output float delay time VPP setup time VDD setup time (to MD3 ) (to MD3 )
s s
1.0 1.05 21.0 ms ms
Initialized program pulse width Additional program pulse width MD0 setup time (to MD1 )
s
1
MD0 data output delay time MD1 hold time MD1 recovery time (to MD0 ) (from MD0 )
s s s s s
2 2 10 0.125 4.19 2 2 2 2 2 0 2 2 130
Program counter reset time X1 input low- and high-level width X1 input frequency Initial mode set time MD3 setup time MD3 hold time MD3 setup time
MHz
s s s s s
ns
Address Note 2 Data output delay time Address Note 2 Data output hold time MD3 hold time (from MD0 )
s s
MD3 Data output float delay time
Notes 1. These symbols correspond to those of the PD27C256A. 2. The internal address signal is incremented by the rising edge of the fourth X1 pulse; it is not connected to an external pin.
25
PD75P218
Program Memory Write Timing
tVPS VPP VPP VDD tVDS VDD VDD+1 VDD tXH
X1 P40 - P43 P50 - P53 tI MD0 tPW MD1 tPCR MD2 tM3S MD3 tM3H tM1R tM0S tOPW tXL Input data tDS tDH tAH tAS Input data
Input data tDS tOH
Output data
tDV
tDF
tM1S
tM1H
Program Memory Read Timing
tVPS VPP VPP VDD tVDS VDD VDD+1 VDD
tXH
X1 tXL tHAD P40 - P43 P50 - P53 tI MD0 tDV tM3HR Output data Output data tDFR tDAD
MD1 tPCR MD2 tM3SR MD3
26
PD75P218
6. PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mil)
64 33
1 A
32
K L
J I
F D
G
H
N
M
C
B
M
R
NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM MILLIMETERS A B C D F G H I J K L M N R 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010+0.004 -0.003 0.007 0~15 P64C-70-750A,C-1
27
PD75P218
64 PIN PLASTIC QFP (14x20)
A B
51 52
33 32
detail of lead end
C
D
S
64 1
20 19
F
G
H
IM
J K
P
N L P64GF-100-3B8,3BE,3BR-1 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 23.6 0.4 20.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.40 0.10 0.20 1.0 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.12 2.7 0.1 0.1 3.0 MAX. INCHES 0.929 0.016 0.795+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.016 +0.004 -0.005 0.008 0.039 (T.P.) 0.071-0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.005 0.106 0.004 0.004 0.119 MAX.
+0.008
28
M
55
Q
PD75P218
64 PIN CERAMIC WQFN
A B K Q
T 64
W S
D
C
U
H
I
M
1 J R
E
F
G
X64KW-100A-2 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K Q R S T U W MILLIMETERS 20.0 0.4 19.0 13.2 14.0 0.4 1.64 2.14 3.556 MAX. 0.7 0.10 0.10 1.0 (T.P.) 1.0 0.2 C 0.25 1.0 1.0 R 3.0 12.0 0.8 0.2 INCHES 0.787+0.017 -0.016 0.748 0.520 0.551 0.016 0.065 0.084 0.140 MAX. 0.028+0.004 -0.005 0.004 0.039 (T.P.) 0.039+0.009 -0.008 C 0.010 0.039 0.039 R 0.118 0.472 0.031 -0.008
+0.009
29
PD75P218
7. RECOMMENDED SOLDERING CONDITIONS
The following conditions (See table below) must be met when soldering this product. Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (IEI-1207). TYPE OF SURFACE MOUNT DEVICE
PD75P218GF-3BR
Soldering Process Wave Soldering Soldering Conditions Solder temperature: 260 C or lower, Flow time: 10 seconds or less, Exposure limit Note: 7 days (10 hour pre-baking is required at 125 C afterwards) Number of flow processes: 1 Peak temperature of package surface: 230 C or lower Reflow time: 30 seconds or less (210 C or higher), Number of reflow processes: 1 Exposure limit Note: 7 days (10 hour pre-baking is required at 125 C afterwards) Peak temperature of package surface: 215 C or lower Reflow time: 40 seconds or less (200 C or higher), Number of reflow processes: 1 Exposure limit Note: 7 days (10 hour pre-baking is required at 125 C afterwards) Pin temperature: 300 C or lower, Time: 3 seconds or less (Per side of the package) Symbol WS60-107-1
Infrared Ray Reflow
IR30-107-1
VPS
VP15-107-1
Partial Heating Method
-
Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25 C and relative humidity at 65 % or less. Caution Do not apply more than one soldering method at any one time, except for "Partial heating method". TYPE OF THROUGH HOLE DEVICE
PD75P218CW
Soldering Process Wave Soldering (only lead part) Partial Heating Method Soldering Conditions Solder temperature: 260 C or lower, Flow time: 10 seconds or less Pin temperature: 260 C or lower, Time: 10 seconds or less
Caution This wave soldering should be applied only to lead part, and do not jet molten solder on the surface of package.
30
PD75P218
APPENDIX DEVELOPMENT TOOLS
The following development tools are provided for the development of a system which employs the
PD75P218.
Language processor
RA75X relocatable assembler This program converts symbolic source code for the PD75000 series of microcomputers into executable absolute address object code. There are also functions such as generating a symbol table and optimizing branch instructions automatically. Host machine OS PC-9800 series MS-DOSTM Ver. 3.10 to Ver. 3.30C PC DOSTM (Ver. 3.1) Distribution media 3.5-inch 2HD 5-inch 2HD 5-inch 2HC Part number
S5A13RA75X S5A10RA75X S7B10RA75X
IBM PC series
PROM programming tools
Hardware PG-1500 The PG-1500 PROM programmer is used together with an accessory board and optional program adapter. It allows the user to program a single chip microcomputer containing PROM and typical 256K-bit to 1M-bit PROMs from a keyboard or a remote control. PROM programmer adapter dedicated to PD75P218CW. Connect the programmer adapter to PG-1500 for use. PA-75P218GF PROM programmer adapter dedicated to PD75P218GF. Connect the programmer adapter to PG-1500 for use. PA-75P218KB PROM programmer adapter dedicated to PD75P218KB. Connect the programmer adapter to PG-1500 for use. Software PG-1500 controller This program enables the host machine to control the PG-1500 through the serial and parallel interfaces. Host machine OS PC-9800 series MS-DOS Ver. 3.10 to Ver. 3.30C PC DOS (Ver. 3.1) Distribution media 3.5-inch 2HD 5-inch 2HD 5-inch 2HC Part number
PA-75P216ACW
S5A13PG1500 S5A10PG1500 S7B10PG1500
IBM PC series
31
PD75P218
Debugging tools
Hardware IE-75000-R Note 1 The IE-75000-R is an in-circuit emulator available for the 75X series. This emulator is used together with the emulation probe to develop application systems of the PD75P218. For efficient debugging, the emulator is connected to the host machine and PROM programmer. The IE-75000-R-EM is an emulation board for the IE-75000-R and IE-75001-R. The IE-75000-R contains the emulation board. The emulation board is used together with the IE-75000-R or IE75001-R to evaluate the PD75P218. The IE-75001-R is an in-circuit emulator available for the 75X series. This emulator is used together with the IE-75000-R-EMNote 2 emulation board and emulation probe to develop application systems of the PD75P218. For efficient debugging, the emulator is connected to the host machine and PROM programmer. Emulation probe for the PD75P218CW. Connect this probe to the IE-75000-R or IE-75001-R for use. Emulation probe for the PD75P218GF. Connect this probe to the IE-75000-R or IE-75001-R for use. A 64-pin conversion socket, the EV-9200G-64, attached to the probe facilitates the connection of the probe with the user system. This program enables the host machine to control the IE-75000-R or IE-75001-R on the host machine through the RS-232-C interface. Host machine OS PC-9800 series MS-DOS Ver. 3.10 to Ver. 3.30C IBM PC series PC DOS (Ver. 3.1) Distribution media 3.5-inch 2HD 5-inch 2HD 5-inch 2HC Part number
IE-75000-R-EM Note 2
IE-75001-R
EP-75216ACW-R
EP-75216AGF-R
EV-9200G-64 Software IE control program
S5A13IE75X S5A10IE75X S7B10IE75X
Notes 1. Provided only for maintenance purposes. 2. The IE-75000-R-EM is an option. Remark NEC is not responsible for the operation of the IE control program and assembler unless it runs on any host machine with the operation system listed above.
32
Configuration of Development Tools
In-circuit emulator Emulation probe IE-75000-R IE-75001-R Note 1 RS-232-C IE control program IE-75000-R-EM EP-75216ACW-R EP-75216AGF-R
Centronics interface
Host machine
Note 2
User system
PC-9800 series IBM PC series (Symbolic debugging possible)
PG-1500 controller PROM programmer PG-1500
PROM version
PD75P216ACW m PD75P216ACW m PD75P218CW/GF/KB PD75P218CW/GF/KB
Programmer adapter Relocatable assembler PA-75P216ACW PA-75P218GF PA-75P218KB Notes 1. IE-75001-R is not provided with IE-75000-R-EM (option). 2. EV-9200G-64
PD75P218
33
PD75P218
[MEMO]
34
PD75P218
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an antistatic container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
35
PD75P218
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92.6
FIP R is a trademark of NEC Corporation. MS-DOSTM is a trademark of Microsoft Corporation. PC DOSTM is a trademark of IBM Corporation.
36

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