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CD40174BC * CD40175BC Hex D-Type Flip-Flop * Quad D-Type Flip-Flop October 1987 Revised July 1999 CD40174BC * CD40175BC Hex D-Type Flip-Flop * Quad D-Type Flip-Flop General Description The CD40174BC consists of six positive-edge triggered Dtype flip-flops; the true outputs from each flip-flop are externally available. The CD40175BC consists of four positiveedge triggered D-type flip-flops; both the true and complement outputs from each flip-flop are externally available. All flip-flops are controlled by a common clock and a common clear. Information at the D inputs meeting the set-up time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. The clearing operation, enabled by a negative pulse at Clear input, clears all Q outputs to logical "0" and Q s (CD40175BC only) to logical "1". All inputs are protected from static discharge by diode clamps to VDD and VSS. Features s Wide supply voltage range: s Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74 LS s Equivalent to MC14174B, MC14175B s Equivalent to MM74C174, MM74C175 3V to 15V s High noise immunity: 0.45 VDD (typ.) Ordering Code: Order Number CD40174BCM CD40174BCN CD40175BCM CD40175BCN Package Number M16A N16E M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagrams Pin Assignments for DIP and SOIC CD40174B CD40175B Top View Top View (c) 1999 Fairchild Semiconductor Corporation DS005987 www.fairchildsemi.com CD40174BC * CD40175BC Truth Table Inputs Clear L H H H H H = HIGH Level L = LOW Level X = Irrelevant = Transition from LOW-to-HIGH level NC = No change Note 1: Q for CD40175B only Outputs D X H L X X Q L H L NC NC Q (Note 1) H L H NC NC Clock X H L www.fairchildsemi.com 2 CD40174BC * CD40175BC Absolute Maximum Ratings(Note 2) (Note 3) DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) 260C 700 mW 500 mW -0.5V to +18V -0.5V to VDD +0.5VDC -65C to +150C Recommended Operating Conditions (Note 3) DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) 3V to 15 VDC 0V to VDD VDC -40C to +85C Note 2: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of "Recommended Operating Conditions" and "Electrical Characteristics" provide conditions for actual device operation. Note 3: VSS = 0V unless otherwise specified. DC Electrical Characteristics (Note 3) CD40174BC/CD40175BC Symbol IDD Parameter Quiescent Device Current VOL LOW Level Output Voltage VOH HIGH Level Output Voltage VIL LOW Level Input Voltage VIH HIGH Level Input Voltage IOL LOW Level Output Current (Note 4) IOH HIGH Level Output Current (Note 4) IIN Input Current Conditions VDD = 5V, VIN = VDD or VSS VDD = 10V, VIN = VDD or VSS VDD = 15V, VIN = VDD or VSS VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.4V VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V VDD = 5V, VO = 4.6V VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V Note 4: IOH and IOL are tested one output at a time. -40C Min Max 4 8 16 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.52 1.3 3.6 -0.52 -1.3 -3.6 -0.30 0.30 3.5 7.0 11.0 0.44 1.1 3.0 -0.44 -1.1 -3.0 4.95 9.95 14.95 Min +25C Typ Max 4 8 16 0.05 0.05 0.05 5 10 15 1.5 3.0 4.0 +85C Min Max 30 60 120 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 Units A A A V V V V V V V V V V V V mA mA mA mA mA mA 0.88 2.25 8.8 -0.88 -2.25 -8.8 -10-5 10-5 -0.30 0.30 0.36 0.9 2.4 -0.36 -0.9 -2.4 -1.0 1.0 A A 3 www.fairchildsemi.com CD40174BC * CD40175BC AC Electrical Characteristics Symbol tPHL, tPLH Parameter Propagation Delay Time to a Logical "0" or Logical "1" from Clock to Q or Q (CD40175 Only) tPHL Propagation Delay Time to a Logical "0" from Clear to Q tPLH Propagation Delay Time to a Logical "1" from Clear to Q (CD40175 Only) tSU Time Prior to Clock Pulse that Data must be Present tH Time after Clock Pulse that Data Must be Held tTHL, tTLH Transition Time (Note 5) Conditions VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Min Typ 190 75 60 180 70 60 230 90 75 45 15 13 -11 -4 -3 100 50 40 130 45 40 120 45 40 15 5.0 5.0 15 5.0 5.0 2.0 5.0 6.0 50 50 50 3.5 10 12 10 5.0 130 15 7.5 Max 300 110 90 300 110 90 400 150 120 100 40 35 0 0 0 200 100 80 250 100 80 250 100 80 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s s s MHz MHz MHz pF pF pF TA = 25C, CL = 50 pF, RL = 200k and tr = tf = 20 ns, unless otherwise specified tWH, tWL Minimum Clock Pulse Width VDD = 5V VDD = 10V VDD = 15V tWL Minimum Clear Pulse Width VDD = 5V VDD = 10V VDD = 15V tRCL Maximum Clock Rise Time VDD = 5V VDD = 10V VDD = 15V tfCL Maximum Clock Fall Time VDD = 5V VDD = 10V VDD = 15V fCL Maximum Clock Frequency VDD = 5V VDD = 10V VDD = 15V CIN CPD Input Capacitance Power Dissipation Clear Input Other Input Per Package (Note 6) Note 5: AC Parameters are guaranteed by DC correlated testing. Note 6: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application note, AN-90. www.fairchildsemi.com 4 CD40174BC * CD40175BC Switching Time Waveforms tr = tf = 20 ns 5 www.fairchildsemi.com CD40174BC * CD40175BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body Package Number M16A www.fairchildsemi.com 6 CD40174BC * CD40175BC Hex D-Type Flip-Flop * Quad D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
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