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Integrated Circuit Systems, Inc.
ICS9147-22
Pentium/ProTM System and Cyrix Clock Chip
General Description
The ICS9147-22 is a Clock Synthesizer chip for Pentium and PentiumPro plus Cyrix CPU based Desktop/Notebook systems that will provide all necessary clock timing. Features include four CPU, seven PCI and eight SDRAM clocks. Two reference outputs are available equal to the crystal frequency, plus the IOAPIC output powered by VDDL. Additionally, the device meets the Pentium powerup stabilization, which requires that CPU and PCI clocks be stable within 2ms after power-up. High drive PCICLK and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30 pF loads. CPUCLK outputs typically provide better than 1V/ns slew rate into 20 pF loads while maintaining 50 5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. The ICS9147-22 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V supply.
Features
Generates system clocks for CPU, IOAPIC, SDRAM, PCI, plus 14.318 MHz (REF0:1), USB, Super I/O Supports single or dual processor systems Supports Intel 60, 66.8MHz, Cyrix 55, 75MHz plus 83.3 and 68MHz (Turbo of 66.6) speeds. Synchronous clocks skew matched to 250ps window on CPU, SDRAM and 500ps window on PCI clocks CPU clocks to PCI clocks skew 1-4ns (CPU early) Two fixed outputs, 48MHz and 24 MHz Separate 2.5V and 3.3V supply pins - 2.5V or 3.3V output: CPU, IOAPIC - 3.3V outputs: SDRAM, PCI, REF, 48/24 MHz No power supply sequence requirements 48 pin 300 mil SSOP

Pin Configuration
Block Diagram
48-Pin SSOP Power Groups
VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK (0:5) VDD3 = SDRAM (0:7), VDD4 = 48MHz, 24MHz VDDL = IOAPIC, CPUCLK (0:3)
Pentium is a trademark on Intel Corporation. 9147-22 Rev A 072597P
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9147-22
Pin Descriptions
PIN NUMBER 1 2 3, 10, 17, 24, 31, 31, 37, 43 4 5 6, 47 7, 15 8 9, 11, 12, 13, 14, 16 18 19 20 21 22 23 25, 28,34 26, 27, 29, 30, 32, 33, 35, 36 38, 39, 41, 42 40, 46 44 45 48 PIN NAME REF1 REF0 GND X1 X2 N/C VDD2 PCICLK_F PCICLK (0:5) FS0 FS1 FS2 VDD4 48MHz 24MHz VDD3 SDRAM (0:7) CPUCLK (0:3) VDDL PD# IOAPIC VDD1 TYPE OUT OUT PWR IN OUT PWR OUT OUT IN IN IN PWR OUT OUT PWR OUT OUT PWR IN OUT PWR DESCRIPTION Reference clock output Reference clock output Ground (common) Crystal or reference input, nominally 14.318 MHz. Includes internal load cap to GND and feedback resistor from X2. Crystal output, includes internal load cap to GND. Pins are not internally connected Supply for PCICLKF, and PCICLK (0:5) Free running PCI clock PCI clocks Frequency select 0 input1 Frequency select 1 input1 Frequency select 2 input1 Supply for 48MHz and 24MHz clocks 48MHz driver output for USB clock 24MHz driver output for Super I/O clock Supply for SDRAM (0:7) SDRAMs clock at CPU speed CPUCLK clock output, powered by VDDL Supply for CPUCLK (0:3) + IOAPIC Power down stops all clocks low and disables oscillator and internal VCO's.2 IOAPIC clock output, powered by VDDL at crystal frequency Supply for REF (0:1), X1, X2
Note 1: Internal pull-up resistor of nomimally 100K to 120K at 3.3V on indicated inputs. Note 2: The PD# input pin has a protection diode clamp to the VDDL power supply. If VDDL is not connected to VDD, (ie VDDL=2.5V, VDD=3.3V) then this input must have a series resistor if the logic high is connected to VDD. This input series resistor provides current limit for the clamp diode. For a pullup to VDD it should be 1Kohm or more from the PD# pin to VDD. If the PD# pin is being driven by logic powered by 3.3V, then a 100 series resistor will be suffcient.
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ICS9147-22
Functionality
VDD = 3.3V 5% VDDL = 2.5V 5% or 3.3V 5%, TA = 0 to 70 Crystal (X1, X2) = 14.31818 MHz
FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPUCLK, SDRAM (MHz) 8.33 75 83.3 68.5 55 75 60 66.8 PCICLK (MHz) 1/2 CPU 30 33.3 1/2 CPU 1/2 CPU 1/2 CPU 1/2 CPU 1/2 CPU
Power Management Functionality
PD# CPUCLK Outputs Stopped Low Running PCICLK(0:5) Outputs Stopped Low Running PCICLK_F, REF, 24/48MHz and SDRAM Stopped Low Running Crystal OSC Off Running VCO
0 1
Off Running
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ICS9147-22
Technical Pin Function Descriptions
VDD(1,2,3,4) This is the power supply to the internal core logic of the device as well as the clock output buffers for REF(0:1), PCICLK, 48/24MHz and SDRAM(0:7). This supply operates at 3.3 volts. Clocks from the listed buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the Clocks, please consult the DC parameter table in this data sheet. VDDL This is the power supply for the CPUCLK and IOAPIC output buffers. The voltage level for these outputs may be 2.5 or 3.3 volts. Clocks from the buffers that each supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels of these Clocks, please consult the DC parameter table in this Data Sheet. GND This is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. X1 This input pin serves one of two functions. When the device is used with a Crystal, X1 acts as the input pin for the reference signal that comes from the discrete crystal. When the device is driven by an external clock signal, X1 is the device input pin for that reference clock. This pin also implements an internal Crystal loading capacitor that is connected to ground. See the data tables for the value of this capacitor. Also includes feedback resistor from X2. X2 This Output pin is used only when the device uses a Crystal as the reference frequency source. In this mode of operation, X2 is an output signal that drives (or excites) the discrete Crystal. The X2 pin will also implement an internal Crystal loading capacitor that is connected to ground. See the Data Sheet for the value of this capacitor. CPUCLK (0:3) These Output pins are the Clock Outputs that drive processor and other CPU related circuitry that requires clocks which are in tight skew tolerance with the CPU clock. The voltage swing of these Clocks is controlled by the Voltage level applied to the VDDL2 pin of the device. See the Functionality Table for a list of the specific frequencies that are available for these Clocks and the selection codes to produce them. SDRAM(0:7) These Output Clocks are use to drive Dynamic RAMs and are low skew copies of the CPU Clocks. The voltage swing of the SDRAMs output is controlled by the supply voltage that is applied to VDD3 of the device, operating at 3.3 volts. 48MHz This is a fixed frequency Clock output at 48MHz that is typically used to drive USB devices. 24MHz This pin is a fixed frequency clock output typically used to drive Super I/O devices. IOAPIC This Output is a fixed frequency Output Clock that runs at the Reference Input (typically 14.31818MHz) . Its voltage level swing is controlled by VDDL and may operate at 2.5 or 3.3volts. REF(0:1) The REF Outputs are fixed frequency Clocks that run at the same frequency as the Input Reference Clock X1 or the Crystal (typically 14.31818MHz) attached across X1 and X2. PCICLK_F This Output is equivalent to PCICLK(0:5) and is FREE RUNNING. PCICLK (0:5) These Output Clocks generate all the PCI timing requirements for a Pentium/Pro based system. They conform to the current PCI specification. They run at 1/2 CPU frequency, or CPU/2.5; see frequency table. FS0,1,2 These Input pins control the frequency of the Clocks at the CPU, PCICLK and SDRAM output pins. See frequency table. PD# This input pin stops all clocks in the low state and powers down the oscillator and VCOs.
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ICS9147-22
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 3.7 V, TA = 0 70 C unless otherwise stated
DC Characteristics
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current SYMBOL VIL VIH IIL IIH IOL1a IOL1b Output High Current IOH1a IOH1b IOL2a Output Low Current IOL2b Output High Current IOH2a IOH2b Output Low Voltage VOL1a VOL1b Output High Voltage VOH1a VOH1b VOL2a Output Low Voltage VOL2b Output High Voltage Supply Current Supply Current
Note 1:
VOH2a VOH2b IDD IDDPD
TEST CONDITIONS Latched inputs and Fulltime inputs Latched inputs and Fulltime inputs VIN = 0V (Fulltime inputs) VIN=VDD (Fulltime inputs) VOL = 0.8V; CPU, SDRAM, 48MHz; VDDL = 3.3V VOL = 0.8V; CPU; VDDL = 2.5V VOH = 2.0V; CPU, SDRAM, 48MHz; VDDL = 3.3V VOH = 2.0V; CPU; VDDL = 2.5V VOL = 0.8V; 24, PCI, REF, IOAPIC; VDDL = 3.3V VOL = 0.8V; IOAPIC; VDDL = 2.5V VOH = 2.0V for REF, PCI, 24MHz & IOAPIC at VDDL = 3.3V VOH = 2.0V; IOAPIC; VDDL = 2.5V IOL = 10mA; CPU, SDRAM, 48MHz; VDDL = 3.3V IOL = 10mA; CPU; VDDL=2.5V IOH = -10mA; CPU, SDRAM, 48MHz; VDDL = 3.3V IOH = -10mA; CPU; VDDL=2.5V IOL = 10mA; for REF, PCI, 24MHz & IOAPIC at VDDL = 3.3V IOL = 10mA; IOAPIC; VDDL = 2.5V IOH = -10mA; for REF, PCI, 24MHz & IOAPIC at VDDL = 3.3V IOH = -10mA; IOAPIC; VDDL = 2.5V @66.6 MHz; all outputs unloaded Power Down
MIN 0.7VDD -28.0 -5.0 19.0 19.0 -
TYP -10.5 30.0 30.0 -26.0 -12.5
MAX 0.2VDD 5.0 -
UNITS V V A A mA mA
-16.0 -9.5 -
mA mA mA mA
16.0 16.0 -
25.0 25.0 -40.0 -13.0
-14.0 -4.0 0.4 0.4 -
mA mA V V V V
-
0.3 0.3
2.4 1.95 -
2.8 2.1 0.3 0.3
0.4 0.4 180 500
V V V V mA A
2.4 1.6 -
2.8 2.1 120 300
Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9147-22
Electrical Characteristics at 3.3V
VDD = 3.0 3.7 V, TA = 0 70 C unless otherwise stated
PARAMETER Rise Time1 Rise Time1 Fall Time Rise Time1 Fall Time1 Rise Time1 Fall Time1
1 ,3
SYMBOL Tr1a Tr1b Tf1 Tr2 Tf2 Tr3 Tf3 Tr4 Tr4a Tf4 Tr5 Tf5
Rise Time1,3 Rise Time1 Fall Time1 ,3 Rise Time1 Fall Time1 Duty Cycle Jitter, Cycle to Cycle1 Jitter, One Sigma1 Jitter, Absolute1 , Jitter, Jitter, Jitter, Jitter, One Sigma Absolute1 One Sigma1 Absolute1
1 1
Dt Tjc-c Tj1s1 Tjab1 Tj1s1a Tjab1a Tj1s2 Tjab2 Tj1s3 Tjab3
Jitter, One Sigma1 Jitter, Absolute1 Input Frequency Logic Input Capacitance1 Crystal Oscillator Capacitance 1 Power-on Time1 Clock Skew1 Clock Skew1 Clock Skew Clock Skew
1 1,2 1
AC Characteristics TEST CONDITIONS 20pF load, 0.8 to 2.0V CPU, 48MHz; VDD = 3.3V 20pF load, 0.8 to 2.0V CPU; VDDL @ 2.5V 20pF load, 2.0 to 0.8V CPU, 48MHz; 30pF load SDRAM 0.8 to 2.0V 30pF load SDRAM 2.0 to 0.8V 30pF load PCI 0.8 to 2.0V 30pF load PCI 2.0 to 0.8V 20pF load, 0.8 to 2.0V 24MHz, REF1 & IOAPIC 20pF load, 0.8 to 2.0V , IOAPIC with VDDL = 2.5V 20pF load, 2.0 to 0.8V 24MHz, REF1 & IOAPIC Load = 45pF 0.8 to 2.0V REF0 VDD = 3.3V Load = 45pF 2.0 to 0.8V, REF0 VDD = 3.3V 20pF load @ VOUT=1.4V CPU, VDDL = 3.0 to 3.7V CPU; Load=20pF, SDRAM Load = 30pF CPU; Load=20pF, SDRAM Load = 30pF CPU; Load=20pF VDDL=2.5V CPU; Load=20pF VDDL=2.5V PCI; Load=30pF PCI; Load=30pF REF1, 48/24MHz Load=20pF, REF0 CL = 45pF REF1, 48/24MHz Load=20pF, REF0 CL = 45pF Logic input pins X1, X2 pins From VDD=1.6V to 1st crossing of 66.6 MHz VDD supply ramp < 40ms CPU to CPU; Load=20pF; @1.4V (Same VDD) SDRAM to SDRAM; Load=30pF @ 1.4V PCI to PCI; Load=30pF; @1.4V CPU(20pF) to PCI (30pF); @1.4V (CPU is early) SDRAM (30pF @3.3V) to CPU (20pF @2.5V) (2.5V CPU is late)
MIN -
TYP 0.9 1.5 0.8 1.0 0.9 1.2 1.1 0.83 2.2 0.81 1.6 1.6
MAX 1.5 2.0 1.4 1.6 1.5 2.0 1.9 1.4 2.6 1.3 2.0 2.0 55 300 150 250 200 500 150 500 3 5 16.0 4.5 250 250 500 4 400
UNITS ns ns ns ns ns ns ns ns ns ns ns ns % ps ps ps ps ps ps ps % % MHz pF pF ms ps ps ps ns ps
45 -250 -500 -500 -5 12.0 1
50 200 50 100 80 1 2 14.318 5 18 2.5 150 150 300 2.6 250
Fi CIN CINX ton Tsk1 Tsk2 Tsk3 Tsk4 Tsk4
Clock Skew1
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. Note 2: Includes VDDL = 2.5V Note 3: VDD3 = 3.3V
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ICS9147-22
SSOP Package
SYMBOL A A1 A2 B C D E e H h L N
X
COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .006 .0085 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100
VARIATIONS AC AD MIN. .620 .720
D NOM. .625 .725
N MAX. .630 .730 48 56
This table in inches
Ordering Information
ICS9147F-22 ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
Example:
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