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Integrated Circuit Systems, Inc.
ICS9147-14
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9147-14 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro. Two bidirectional I/O pins (FS1,FS2) are latched at power-on to the functionality table, with FS0 selectable in real-time to toggle between conditions.
Features
High drive PCICLK and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30 pF loads. CPU outputs typically provide better than 1V/ns slew rate into 20 pF loads while maintaining 50 5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. Seperate buffers supply pins VDDL1 allow for 3.3V or reduced voltage swing (from 2.9 to 2.5V) for CPU (0:3) and IOAPIC outputs.
Block Diagram
Four copies of CPU clock Twelve SDRAM (3.3V TTL), usable asAGP clocks Seven copies of PCICLK clock (synchronous with CPU clock/2 or CPU/2.5 for 75 and 83.3 MHz CPU) CPU clocks to PCICLK clocks skew 1-4ns, center 2.6ns. One IOAPIC clock @14.31818 MHz Two copies of Ref. clock @14.31818 MHz Ref. 14.31818 MHz Xtal oscillator input Separate VDDL1 for four CPU and single IOAPIC output buffers to allow 2.5V output (or Std. Vdd) One each 48/ 24MHz (3.3V TTL) 3.3V outputs: SDRAM, PCI, REF, 48/24MHz. 2.5V or 3.3V outputs: CPU, IOAPIC. 20 ohm CPU clock output impedance 20 ohm PCI clock output impedance 1.5ns rise time (30 pF loading) 250 ps CPU, PCI clock skew 350ps (cycle by cycle) CPU jitter 2ms Power up clock stable time 45-55% Clock duty cycle 48 pin 300 mil SSOP package 3.0V 3.7V supply range w/2.5V compatible outputs
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2, 24MHz, 48MHz VDD2 = PCICLKF, PCICLK(0:5) VDD3 = SDRAM (0;11) VDDL1 = CPUCLK (0:3)
9147-14 Rev B 071897P
48-Pin SSOP
* Internal Pull-up Resistor of 300K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9147-14
Pin Descriptions
PIN NUMBER PIN NAME TYPE DESCRIPTION
1 2 3,9,22,33,39,45 4 5 16,23,24, 27,48 6,14 7 8 10, 11, 12, 13 15 17, 18, 20, 21, 28, 29, 31, 32, 34, 35,37,38 19,30,36 25 26 40, 41, 43, 44 42 46 47
VDD1 REF0 GND X1 X2 N/C VDD2 PCICLK_F FS1* PCICLK0 FS2* PCICLK(1:4) PCICLK5
SDRAM (0:11) VDD3 24MHz 48MHz FS0* CPUCLK(0:3) VDDL1 REF1 IOAPIC
PWR OUT PWR IN OUT PWR OUT IN OUT IN OUT OUT OUT PWR OUT OUT IN OUT PWR OUT OUT
Ref (0:2), XTAL, 24MHz, 48MHz power supply 14.318 Mhz reference clock. Ground Crystal input has internal load cap and feedback resistor from X2 Crystal output nominally 14.318MHz. Has internal load cap Pins are not internally connected Supply for PCICLK_F and PCICLK (0:5) Free running PCI clock Frequency select pin. * PCI clock output. Frequency select pin. * PCI clock outputs PCI clock output.
SDRAM clock outputs. Supply for SDRAM (0:11) 24MHz output clock 48MHz output clock Frequency select pin CPU clock outputs, powered by VDD1 Supply for CPU (0:3) and IOAPIC clock, can be 2.5 or 3.3V 14.318 Mhz reference clock. IOAPIC clock output. Powered by VDDL1.
* Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 3.3v10% 0-70c Crystal (X1, X2 = 14.3181MHz
FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPU, SDRAM(MHz) 50.0 75.0 33.3 68.5 55.0 75.0 60.0 66.8 PCICLK (MHz) 25.0 32.0 16.65 34.25 27.5 37.5 30.0 33.4 REF, IOAPIC (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
Functionality
2
ICS9147-14
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V DD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 3.7 V, TA = 0 70 C unless otherwise stated
DC Characteristics PARAMETER Input Low Voltage Input High Voltage Output Low Current1 Output High Current1 Output Low Current1 Output High Current1 Output Low Current1 Output High Current1 Output Low Voltage1 Output High Voltage1 Output Low Voltage1 Output High Voltage1 Output Low Voltage1 Output High Voltage1 Supply Current Pullup Resistor1 SYMBOL VIL VIH IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 VOL1 VOH1 VOL2 VOH2 VOL3 VOH3 IDD RPU1 TEST CONDITIONS Latched inputs Latched inputs VOL=0.8V; for SDRAM, PCICLK VOH=2.0V; for SDRAM PCICLK VOL=0.8V; 24, 48 CLKs, CPU, REF & IOAPIC VOH=2.0V; 24, 48 CLKs, CPU, REF & IOAPIC VOL=0.8V; for CPU at VDDL = 2.5V VOH = 1.7V; for CPU at VDDL = 2.5V IOL = 10mA; for PCICLK, SDRAM IOH = -10mA; for SDRAM, PCICLK IOL = 8mA; for fixed CLKs, CPU, REF & IOAPIC IOH = -8mA; for fixed CLKs, CPU, REF & IOAPIC IOL = 5mA; for CPU at VDDL = 2.5V IOH = -5mA; for CPU at VDDL = 2.5V @66.6 MHz; all outputs unloaded FS0, FS1 FS2 inputs MIN 2.0 19.0 16.0 10.0 2.4 2.4 2.1 150 TYP 30.0 -26.0 25.0 -22.0 18.0 -14.0 0.3 2.8 0.3 2.8 0.25 2.25 70 300 MAX 0.8 -16.0 -14.0 -8.0 0.4 0.4 0.4 120 450 UNITS V V mA mA mA mA mA mA V V V V mA mA mA K ohm
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9147-14
Electrical Characteristics at 3.3V
VDD = 3.0 3.7 V, TA = 0 70 C unless otherwise stated
AC Characteristics
PARAMETER Rise Time1 Fall Time1 Rise Time1 Fall Time1 Rise Time Fall Time
1
SYMBOL Tr1 Tf1 Tr2 Tf2 Tr3 Tf3 Tr4 Tf4 Dt DT2 Tjis1 Tjab1 Tjc-c Tjis2 Tjab2 Fi CIN CINX ton Tsk1 Tsk2 Tsk3
TEST CONDITIONS 20pF load, 0.8 to 2.0V CPU, IOAPIC, Fixed & REF 20pF load, 2.0 to 0.8V CPU, IOAPIC, Fixed & REF 20pF load, 20% to 80% CPU, IOAPIC, Fixed & REF 20pF load, 80% to 20% CPU, IOAPIC, Fixed& REF 20pF load, 0.8 to 2.0V PCI, SDRAM 20pF load, 2.0 to 0.8V PCI, SDRAM 20pF load, 0.4 to 2.0V , CPU and IOAPIC with VDDL = 2.5V 20pF load, 2.0 to 0.4V, CPU and IOAPIC with VDDL = 2.5V 20pF load @ VOUT=1.4V All clocks except REF 20pF load @ VOUT=1.4V REF outputs CPU & PCICLK Clocks; Load=20pF, SDRAM; Load = 30pF CPU & PCICLK Clocks; Load=20pF, SDRAM; Load = 30pF CPU Fixed CLK; Load=20pF Fixed CLK; Load=20pF Logic input pins X1, X2 pins From VDD=1.6V to 1st crossing of 66.6 MHz VDD supply ramp < 40ms CPU to CPU or PCI to PCI; Load=20pF; @1.4V (Same VDD) SDRAM to SDRAM; Load=20pF; @1.4V CPU to PCICLK; Load=20pF; @1.4V (CPU is early)
MIN 45 40 -250 -5 12.0 1
TYP 0.9 0.8 1.5 1.4 0.9 0.8 50 50 50 200 1 2 14.318 5 18 2.5 150 300 2.1
MAX 1.5 1.4 2.5 2.4 1.5 1.4 3.0 2.0 55 60 150 250 350 3 5 16.0 4.5 250 500 4
UNITS ns ns ns ns ns ns ns ns % % ps ps ps % % MHz pF pF ms ps ps ns
1
Rise Time
1
Fall Time1 Duty Cycle1 Duty Cycle1 Jitter, One Sigma1 Jitter, Absolute1 Jitter, Cycle to Cycle Jitter, One Sigma Jitter, Absolute1 Input Frequency1 Logic Input Capacitance1 Crystal Oscillator Capacitance 1 Power-on Time1 Clock Skew1 Clock Skew1 Clock Skew1
1
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
4
ICS9147-14
Shared Pin Operation Input/Output Pins
Pins 7, 8 and 26 on the ICS9147-14 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the devices internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
Fig. 1
5
ICS9147-14
Fig. 2a
Fig. 2b
6
ICS9147-14
SSOP Package
SYMBOL A A1 A2 B C D E e H h L N
X
COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100
VARIATIONS AC MIN. .620
D NOM. .625
N MAX. .630 48
Ordering Information
ICS9147F-14
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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