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Integrated Circuit Systems, Inc.
ICS9147-09
Frequency Generator & Integrated Buffers for 686 Series CPUs
General Description
The ICS9147-09 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro,AMD or Cyrix processors. Four bidirectional I/O pins (FS0, FS1, FS2, BSEL) are latched at power-on to the functionality table. The Six BUS clocks can be selected as either synchronous at 1/2 CPU speed or asynchronous at 32MHz selected by BSEL latched input.The inputs provide for tristate and test mode conditions to aid in system level testing.These multiplying factors can be customized for specific applications. Glitch-free stop clock controls provided for CPU. High drive BUS and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30 pF loads. CPU outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 505% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. Seperate buffer supply pin VDDL allows for nominal 3.3V voltage or reduced voltage swing (from 2.9 to 2.5V) for CPUL (1:2) and IOAPIC outputs.
Features
Total of 15 CPU speed clocks: - Two copies of CPU clock with VDDL (2.5 to 3.3V) - Twelve (12) SDRAM (3.3v) plus one CPUH/AGP (3.3V) clocks Six copies of BUS clock (synchronous with CPU clock/2 or asynchronous 32 MHz) 250ps output skew window for CPU andSDRAM clocks and 500ps window BUS clocks. CPU clocks to BUSclocks skew 1-4ns (CPU early) Two copies of Ref. clock @14.31818 MHz (One driven by VDDL as IOAPIC) One 48 MHz (3.3 V TTL) for USB support and single 24 MHz. Separate VDDL for CPUL (1:2) clock buffers and IOAPIC to allow 2.5V output (or Std. Vdd) 3.0V 3.7V supply range w/2.5V compatible outputs 48-pin SSOP package

Block Diagram
Pin Configuration
48-Pin SSOP
Pentium is a trademark of Intel Corporation 9147-09 Rev A 10/2897P
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9147-09
Pin Descriptions
PIN NUMBER REF 2 FS1 3, 9, 16, 22, 27, 33, 39, 45 4 5 41 8, 10, 11, 12, 14, 15 FS0 23 24 47 BSEL 1, 6, 13, 19, 30, 36, 48 17, 18, 20, 21, 28, 29, 31, 32, 34, 35, 37, 38 40 42, 43 7, 25, 26 46 FS2 44 IOAPIC IN OUT Logic input frequency select Bit 2*. Input latched at Poweron. Reference clock (14.318MHz) powered by VDDL, operating 2.5 to 3.3V. VDD3 SDRAM (1:12) CPUH/AGP CPUL (1:2) N/C 48M IN PWR OUT OUT OUT -- OUT CPU_STOP# PD# 24M IN IN IN OUT Logic input frequency select Bit0.*. Input latched at Poweron. Halts CPU Clocks at Logic "0" level when low. Internal Pull-up Powers down chip, active low. Internal Pull-up 24MHz fixed clock.* Logic input* for selecting synchronous or asynchronous BUS frequency- see table above. Input latched at Poweron.* 3.3 volt core logic and buffer power SDRAM clocks at CPU speed. See select table for frequency. CPU clock operates at SDRAM VDD level (3.3V nom), for AGP etc. CPU clocks .See select table for frequency. Operates at down to 2.5V controlled by VDDL pin. Pins not internally connected. 48 MHz fixed clock output*. GND X1 X2 VDDL BUS (1:5) BUS6 IN PWR IN OUT PWR OUT OUT Logic input frequency select Bit1*. Input latched at Poweron. Ground. Crystal input. Nominally 14.318 MHz. Has internal load cap Crystal output. Has internal load cap and feedack resistor to X1 2.5 or 3.3V buffer power for CPUL and IOAPIC output buffers. BUS clock outputs. see select table for frequency BUS clock output. See select table for frequency.* PIN NAME TYPE OUT Reference clock output* DESCRIPTION
* Bidirectional input/output pins, input logic level determined at internal power-on-reset are latched. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS9147-09
Functionality with (14.31818 MHz input)
Address Select CPUL (1:2) CPUH SDRAM (1:12) (MHz) 60 66.8 50 55 75 68.5 83.3 Tristate BUS (1:6) (MHz) BSEL=1 BSEL=0 30 33.4 25 27.5 37.5 34.3 41.65 Tristate 32 32 32 32 32 32 32 Tristate 24M (MHz) (MHz) 24 24 24 24 24 24 24 Tristate 48M (MHz) (MHz) 48 48 48 48 48 48 48 Tristate
FS2 0 0 0 0 1 1 1 1
FS1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1
**Test: is the frequency applied to the X1 input. Can be crystal or tester generated clock overriding crystal at X1 pin.
Clock Enable Configuration
PD# 1 1 0 CPUSTOP# 1 0 X CPUL (1:2) CPUH Running Stop Low Stop Low SDRAM BUS (1:6) (1:12) Running Running Running Running 24MHz 48MHz REF Running Running Running Running Running Running
Stop Low Stop Low Stop Low Stop Low Stop Low
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ICS9147-09
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 3.7 V, TA = 0 70 C unless otherwise stated
DC Characteristics
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current SYMBOL VIL VIH IIL IIH IOL1a IOL1b Output High Current Output Low Current Output High Current Output Low Voltage IOH1a IOH1b IOL2 IOH2 VOL1a VOL1b Output High Voltage Output Low Voltage Output High Voltage Supply Current Power Down Current Pull-up Resistor VOH1a VOH1b VOL2 VOH2 IDD Ipd Rpu TEST CONDITIONS Latched inputs and Fulltime inputs Latched inputs and Fulltime inputs VIN = 0V (Fulltime inputs) VIN=VDD (Fulltime inputs) VOL = 0.8V; CPU, SDRAM IOAPIC, REF, BUS; VDD2 = 3.3V VOL = 0.8V; CPUL, IOAPIC; VDD2 = 2.5V VOH = 2.0V; CPU, SDRAM IOAPIC, REF, BUS; VDD2 = 3.3V VOH = 2.0V; CPUL, IOAPIC; VDD2 = 2.5V VOL = 0.8V; for fixed 24, 48 VOH = 2.0V; for fixed 24, 48 IOL = 10mA; CPU, SDRAM IOAPIC REF, BUS;VDD2 = 3.3V IOL = 10mA; CPUL, IOAPIC; VDD2=2.5V IOH = -10mA; CPU, SDRAM, IOAPIC, REF, BUS; VDD = 3.3V IOH = -10mA; CPUL, IOAPIC; VDD2=2.5V IOL = 8mA; for fixed 24, 48MHz CLKs IOH = -8mA; for fixed 24, 48MHz CLKs @66.6 MHz; all outputs unloaded PD#=0 CPUSTOP#; PD# 2.4 1.95 2.4 20 16.0 MIN 0.7VDD -28.0 -5.0 19.0 19.0 TYP -10.5 30.0 30.0 -26.0 -12.5 25.0 -22.0 0.3 0.3 2.8 2.1 0.3 2.8 120 5.0 40 0.4 180 20.0 80 -16.0 -9.5 -14.0 0.4 0.4 MAX 0.2VDD 5.0 UNITS V V A A mA mA mA mA mA mA V V V V V V mA A Kohms
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9147-09
Electrical Characteristics at 3.3V
VDD = 3.0 3.7 V, TA = 0 70 C unless otherwise stated
PARAMETER Rise Time
1
SYMBOL Tr1 Tf1 Tr3 Tf3 Tr4 Tf4 Dt DT2 Tjis1
Fall Time1 Rise Time1 Fall Time1 Rise Time1 Fall Time1 Duty Cycle1 Duty Cycle1 Jitter, One Sigma1
Jitter, Absolute1 Jitter, One Sigma1 Jitter, Absolute1 Jitter, Cycle to Cycle1 Jitter, Cycle to Cycle1 Input Frequency Ratio of nominal to output frequency Logic Input Capacitance 1 Crystal Oscillator Capacitance1, 2 Power-on Time1 Clock Skew Window1 Clock Skew Window1 Clock Skew Window1 Clock Skew Window1 Clock Skew Window1
1
Tjab1 Tjis2 Tjab2 Tcc1 Tcc2 Fi Fout1 CIN CINX ton Tsk1 Tsk2 Tsk3 Tsk4 Tsk5
AC Characteristics TEST CONDITIONS 20pF load, 0.8 to 2.0V CPU, SDRAM, BUS & REF 20pF load, 2.0 to 0.8V CPU, SDRAM, BUS & REF 20pF load, 0.8 to 2.0V fixed 20 & 48 clocks 20pF load, 2.0 to 0.8V fixed 20 & 48 clocks 20pF load, 0.4 to 2.0V , CPUL with VDDL = 2.5V 20pF load, 2.0 to 0.4V, CPUL with VDDL = 2.5V 20pF load @ VOUT=1.4V All clocks except 48MHz and REF 20pF load @ VOUT=1.4V 48MHz and REF outputs CPU & BUS Clocks; Load=20pF, SDRAM; Load = 30pF, VDDL = 3.3 or 2.5V FOUT=25 MHz, BSEL=1 CPU & BUS Clocks; Load=20pF, SDRAM; Load = 30pF, VDDL = 3.3 or 2.5V FOUT25 MHz, BSEL=1 Fixed CLK; Load=20pF Fixed CLK; Load=20pF CPU Clocks, Load=20pF BSEL=1 CPU Clocks, Load=20pF BSEL=1 VDDL=2.5V With input driven at 14.31818MHz to 20.0, 48.0MHz Logic input pins X1, X2 pins From VDD=1.6V to 1st crossing of 66.6 MHz VDD supply ramp < 40ms CPU to CPU or SDRAM; Load=20pF; @1.4V (Same VDD) BUS to BUS, SDRAM to SDRAM; Load=20pF; @1.4V CPU to BUS; Load=20pF; @1.4V (CPU is early) CPUL to BUS, VDDL=2.5V Vth=1.25, CPUL (BUS Vth=1.4V) SDRAM, CPUH (@3.3V, Vth=1.4V) to CPUL (@2.5V Vth=1.25V) Load=20pF (2.5V CPUL is late)
MIN 47 40 -
TYP 0.9 0.8 0.9 1.1 2.0 1.6 52 50 50
MAX 1.5 1.4 1.5 1.5 2.5 2.5 57 60 150
UNITS ns ns ns ns ns ns % % ps
-250 -5
1 2 14.318 -0.1 5 4 2.5 150 300 2.1 1.50 600
250 3 5 250 350 16.0 +1 6 4.5 250 500 4.6 3.0 850
ps % % ps ps MHz ppm pF pF ms ps ps ns ns ps
12.0 -1 2 1.6 0.50 100
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9147-09
Shared Pin Operation Input/Output Pins
Pins 2, 15, 46 and 47 on the ICS9147-09 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the devices internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
Test Mode Operation
The ICS9147-09 includes a production test verification mode of operation. This requires that the FS2 and FS1 pins be programmed to a logic high and the FS0 pin be programmed to a logic low(see Shared Pin Operation section). In this mode the device will output the following frequencies.
Pin REF, IOAPIC 48MHz 24MHz CPU, SDRAM BSEL=1 BSEL=0 Frequency REF REF/2 REF/4 REF2 REF/4 REF/3
BUS BUS
Note: REF is the frequency of either the crystal connected between the devices X1and X2, or, in the case of a device being driven by an external reference clock, the frequency of the reference (or test) clock on the devices X1 pin.
Fig. 1
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ICS9147-09
Fig. 2a
Fig. 2b
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ICS9147-09
Recommended PCB Layout for ICS9147-09
NOTE: This PCB Layout is based on a 4 layer board with an internal Ground (common) and VDD plane. Placement of components will depend on routing of signal trace. The 0.1uf Capacitors should be placed as close as possible to the Power pins. Placement on the backside of the board is also possible. The Ferrite Beads can be replaced with 10-15ohm Resistors. For best results, use a Fixed Voltage Regulator between the main (board) VDD and the different VDD planes. 8
ICS9147-09
SSOP Package
SYMBOL A A1 A2 B C D E e H h L N
X
COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100
VARIATIONS AC AD MIN. .620 .720
D NOM. .625 .725
N MAX. .630 .730 48 56
Ordering Information
ICS9147F-09
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS = Standard Device
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ADVANCE INFORMATION documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

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