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FEATURES 750 kHz/1 MHz Throughput Rate 1 s/750 ns Conversion Time 12-Bit No Missed Codes Over Temperature 67 dB SNR at 100 kHz Input Frequency Low Power--250 mW typ Fast Bus Access Time--57 ns max APPLICATIONS Digital Signal Processing Speech Recognition and Synthesis Spectrum Analysis DSP Servo Control
LC2MOS 12-Bit, 750 kHz/1 MHz, Sampling ADC AD7886
FUNCTIONAL BLOCK DIAGRAM
VDD R3 VIN1 10k R4 VIN2 10k +5REF R1 9k SUM R2 6.3k VREF 4096 RESISTOR DAC AGND - + T/H 3.5k R5 CLOCK OSCILLATOR AND TIMER CONTROL TIMER BUSY CS RD CONVST
4-BIT LATCH 15 COMPARATORS AND 4-BIT FLASH LOGIC DB11 4-BIT LATCH THREE STATE OUTPUTS DB0
4-BIT LATCH SEGMENT SELECT
AD7886
VSS DGND
GENERAL DESCRIPTION
The AD7886 is a 12-bit ADC with a sample-and-hold amplifier offering high speed performance combined with low power dissipation. The AD7886 is a triple pass flash ADC that uses 15 comparators in a 4-bit flash technique to achieve 12-bit accuracy in 1 s/750 ns conversion time. An on-chip clock oscillator provides the appropriate timing for each of the three conversion stages, eliminating the need for any external clocks. Acquisition time of the sample-and-hold amplifier gives a resulting throughput rate of 750 kHz/1 MHz.* The AD7886 operates from 5 V power supplies. Pin-strappable inputs offer a choice of three analog input ranges: 0 V to 5 V, 0 V to 10 V or 5 V. In addition to the traditional dc accuracy specifications such as linearity, offset and full-scale errors, the AD7886 is also specified for dynamic performance parameters, including harmonic distortion and signal-to-noise ratio. The AD7886 has a high speed digital interface with three-state data outputs. Conversion control is provided by a CONVST input. Data access is controlled by CS and RD inputs, standard microprocessor signals. The data access time of less than 57 ns means that the AD7886 can interface directly to most modern microprocessors, including DSP processors.
*Contact your local salesperson for further information on the 1 MHz version.
The AD7886 is fabricated in Analog Devices' Linear Compatible CMOS process, a mixed technology process that combines precision bipolar circuits with low power CMOS logic. The AD7886 is available in both a 28-pin DIP and a 28-pin leaded chip carrier.
PRODUCT HIGHLIGHTS
1. Fast 1.33 s/1 s Throughput Time. Fast throughput time makes the AD7886 suitable for a wide range of data acquisition applications. 2. Dynamic Specifications for DSP Users. The AD7886 is specified for ac parameters, including signal-to-noise ratio, harmonic distortion and intermodulation distortion. Key digital timing parameters are also tested and guaranteed over the full operating temperature range. 3. Fast Microprocessor Interface. Standard control signals, CS and RD, and fast bus access times make the AD7886 easy to interface to microprocessors. 4. Low Power. LC2MOS fabrication process gives low power dissipation of 250 mW.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1997
= +5 V 5%, = -5 V O V, V AD7886-SPECIFICATIONS (V otherwise noted. VSpecifications5%, A6ND = DGND =version.) = -3.5 V, connected as shown in Figure 2. All Specifications T to T unless apply for 750 kHz
DD SS REF MIN MAX
Parameter DYNAMIC PERFORMANCE2 Signal-to-Noise Ratio3 (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Intermodulation Distortion (IMD) Second Order Terms Third Order Terms ACCURACY Resolution Integral Linearity TMIN to TMAX Minimum Resolution for Which No Missing Codes Are Guaranteed Unipolar Offset Error @ +25C TMIN to TMAX Bipolar Offset Error @ +25C TMIN to TMAX Unipolar Gain Error @ +25C TMIN to TMAX Bipolar Gain Error @ +25C TMIN to TMAX ANALOG INPUT Unipolar Input Current Bipolar Input Current REFERENCE INPUT VREF Input Reference Current R1, Resistance R2, Resistance R2/R1 Ratio
J Version1
K, B Versions1
T Version1
Units
Test Conditions/Comments
65 -75 -77 -80 -80
67 -75 -77 -80 -80
65 -75 -77 -80 -80
dB min dB typ dB typ dB typ dB typ
VIN = 100 kHz Sine Wave, fSAMPLE = 750 kHz VIN = 100 kHz Sine Wave, fSAMPLE = 750 kHz VIN = 100 kHz Sine Wave, fSAMPLE = 750 kHz fa = 96 kHz, fb = 103 kHz, fSAMPLE = 750 kHz
12
12 2 12 5 5 5 5 5 5 5 +5
12 2 12 5 5 5 5 5 5 5 5 1.5 0.75 -3.5 -10 9 6.3 0.7
Bits LSB max Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max
12 5 5 5 5 5 5 5 5 1.5 0.75 -3.5 -10 9 6.3 0.7
Input Range: 0 V to 5 V or 0 V to 10 V Input Range: 5 V Input Range: 0 V to 5 V or 0 V to 10 V Input Range: 5 V
1.5 0.75 -3.5 -10 9 6.3 0.7
mA max mA max
Input Ranges: 0 V to 5 V or 0 V to 10 V Input Range: 5 V 2% For Specified Performance 25% 25% 0.1%
Volts mA max k nom k nom nom
POWER SUPPLY REJECTION
VDD Only, (FS Change) VSS Only, (FS Change) LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN4 LOGIC OUTPUTS DB11-DB0, BUSY Output High Voltage, VOH Output Low Voltage, VOL DB11-DB0 Floating-State Leakage Current Floating-State Output Capacitance4 POWER REQUIREMENTS VDD VSS IDD ISS Power Dissipation 0.5 0.5 0.5 0.5 0.5 0.5 LSB typ LSB typ VSS = -5 V, VDD = +4.75 V to +5.25 V VDD = +5 V, VSS = -4.75 V to -5.25 V VDD = 5 V 5% VDD = 5 V 5% VIN = 0 V to VDD
2.4 0.8 10 10
2.4 0.8 10 10
2.4 0.8 10 10
V min V max A max pF max
4 0.4 10 15
4 0.4 10 15
4 0.4 10 15
V min V max pA max pF max
ISOURCE = 200 A ISINK = 1.6 mA
+5 -5 35 -35 250 350
+5 -5 35 -35 250 350
+5 -5 35 -35 250 350
V nom V nom mA max mA max mW typ mW max
5% for Specified Performance 5% for Specified Performance Typically 25 mA, CONVST = CS = RD = VDD Typically 25 mA, CONVST = CS = RD = VDD CONVST = CS = RD = VDD
NOTES I Temperature ranges are as follows: J, K Versions: 0C to +70C; B Version: -40C to +85C; T Version: -55C to + 125C. 2 Applies to all three input ranges, V IN = 0 to FS, pk-to-pk V. 3 SNR calculation includes distortion and noise components. 4 Sample tested @ +25C to ensure compliance. Specifications subject to change without notice.
-2-
REV. B
AD7886 TIMING CHARACTERISTICS1 (V
Parameter t1 t2 t3 t4 t5 t6 t7 3 t8 t9 3 t10 t11 t12 t13 tCONV
DD
= +5 V
5%, VSS = -5 V
5%, AGND = DGND = 0 V)
Limit at Limit at TMIN, TMAX TMIN, TMAX (J, K Versions) (B Version) 50 1 0 0 60 100 57 10 50 20 10 10 100 0 0 250 1.333 950 1000 50 1 0 0 60 100 57 10 50 20 10 10 100 0 0 250 1.333 950 1000
Limit at TMIN, TMAX (T Version) 50 1 0 0 75 100 70 10 60 14 0 10 100 0 0 250 1.333 950 1000
Units ns min Fs max ns min ns min ns min ns max ns max ns min ns max ns min ns min ns min ns max ns min ns min ns typ s min ns typ ns max
Conditions/Comments CONVST Pulse Width CS to RD Setup Time CS to RD Hold Time RD Pulse Width CONVST to BUSY Propagation Delay, (CL = 10 pF) Data Access Time After RD Bus Relinquish Time After RD Data Setup Time Prior to BUSY, (CL = 20 pF) Data Setup Time Prior to BUSY, (CL = 100 pF) Bus Relinquish Time After CONVST CS High to CONVST Low BUSY High to RD Low BUSY High to CONVST Low, SHA Acquisition Time Sampling Interval Conversion Time
NOTES 1 Timing specifications in bold print are 100% production tested. All other times are sample tested at +25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 t6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 3 t7 and t9 are derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the load capacitor, C L. This means that the times, t7 and t9, quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications subject to change without notice.
I OL
TO OUTPUT PIN
+2.1V CL
IOH
VIN1, VIN2, SUM, +5REF to AGND . . . . . . -15 V to +15 V VREF to AGND . . . . . . . . . . . . . . . . VSS -0.3 V to VDD +0.3 V Digital Inputs to DGND CS, RD, CONVST . . . . . . . . . . . . . . -0.3 V to VDD +0.3 V Digital Outputs to DGND DB0 to DB11, BUSY . . . . . . . . . . . . . -0.3 V to VDD +0.3 V Operating Temperature Range Commercial (J, K Versions) . . . . . . . . . . . . . . 0C to +70C Industrial (B Version) . . . . . . . . . . . . . . . . -40C to +85C Extended (T Version) . . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . .-65C to + 150C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300C Power Dissipation (Any Package) to +75C . . . . . . 1000 mW Derates above +75C by . . . . . . . . . . . . . . . . . . . . 10 mW/C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 If VSS is open circuited with V DD and AGND applied, the V SS pin will be pulled positive, exceeding the Absolute Maximum Ratings. If this possibility exists, a Schottky diode from V SS to DGND (cathode end to GND) ensures that the
Figure 1. Load Circuit for Bus Access and Relinquish Time
ABSOLUTE MAXIMUM RATINGS 1, 2
(TA= +25C unless otherwise noted) VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to -7 V AGND to DGND . . . . . . . . . . . . . . . . . -0.3 V to VDD +0.3 V
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7886 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
-3-
AD7886
ORDERING GUIDE
Model1, 2 AD7886JD AD7886KD AD7886JP AD7886KP AD7886BD AD7886TD
Temperature Range 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -55C to +125C
SNR (dBs) 65 67 65 67 67 65
Integral Nonlinearity (LSBs) 2.0 2.0 2.0 2.0
Package Option3 D-28 D-28 P-28A2 P-28A2 D-28 D-28
NOTES 1Contact your sales office for availability of AD7886BD, AD7886TD and 1 MHz version. 2 Analog Devices reserves the right to ship J-Leaded Ceramic Chip Carrier (JLCCC) in lieu of PLCC packages. 3 D = Ceramic DIP; P = Plastic Leaded Chip Carrier.
PIN FUNCTION DESCRIPTION
DIP Pin Number
Mnemonic
Description Positive Power Supply, +5 V 5%. Both VDD pins must be tied together. Negative Power Supply, -5 V 5%. Both VSS pins must be tied together. Analog Ground. Both AGND pins must be tied together. Digital Ground.
Power Supply 10 & 19 VDD 15 & 24 VSS 16 & 23 AGND 5 DGND
Analog and Reference Inputs 17 & 18 VIN Analog Inputs, VIN1 and VIN2. The part can be pin strapped for any one of three analog input ranges; Range 0 V to 5 V 0 V to 10 V 5 V 20 21 22 +5REF SUM VREF Pin Strap Connect VIN2 to VIN1 Connect VIN2 to GND Connect VIN2 to +5 V Signal Input VIN1 & VIN2 VIN1 VIN1
+5 V Reference input. This input is used in conjunction with SUM and VREF inputs to scale an external +5 V reference to -3.5 V, the required reference for the part (see Figure 2). Summing Point. This input is used in conjunction with +5REF and VREF inputs to scale an external +5 V reference to -3.5 V, the required reference for the part (see Figure 2). Voltage Reference Input. The AD7886 is specified with VREF = -3.5 V. Three-state data outputs. These outputs are controlled by CS and RD. DB11 is the Most Significant Bit (MSB). BUSY Output indicates converter status. BUSY is low during conversion. Chip Select Input. The device is selected when this input is low. Read Input. This active low signal, in conjunction with CS, is used to enable the output data three-state drivers. Conversion Start Input. This input is used to start conversion.
Interface and Control 1-4, DB7-DB4 6-9, DB3-DB0 25-28 DB11-DB8 11 BUSY 12 CS 13 RD 14 CONVST
-4-
REV. B
AD7886
PIN CONFIGURATIONS DIP
DB4 DB5
PLCC
28 DB8 27 DB9 26 DB10 25 DB11 24 VSS
DGND DB3 DB2 DB1 DB0 5 6 7 8 9 25 DB11 24 VSS
DB7 DB10 DB6 DB8 DB9
DB7 DB6 DB5 DB4 DGND DB3 DB2 DB1 DB0
1 2 3 4 5 6 7 8 9
4
3
2
1
28
27
26
AD7886
TOP VIEW (Not to Scale)
23 AGND 22 VREF 21 SUM 20 +5REF 19 VDD 18 VIN2 17 VIN1 16 AGND 15 VSS
AD7886
TOP VIEW (Not to Scale)
23 AGND 22 VREF 21 SUM 20 +5REF 19 VDD
VDD 10 BUSY 11
VDD 10 BUSY 11 CS 12 RD 13 CONVST 14
12
CS
13
RD
14
CONVST
15
VSS
16
AGND
17
VIN1
18
VIN2
TERMINOLOGY
Unipolar Offset Error
The ideal first code transition should occur when the analog input is 1 LSB above AGND. The deviation of the actual transition from that point is termed the offset error.
Bipolar Zero Error
result. The 12 bits of data are then stored internally in a threestate output latch.
REFERENCE INPUT
The ideal midscale transition (i.e., 0111 1111 1111 to 1000 0000 0000) for the +5 V range should occur when the analog input is at zero volts. Bipolar zero error is the deviation of the actual transition from that point.
Gain Error
In the unipolar mode, gain error is measured with respect to the first and last code transition points. The ideal difference between these points is FS-2 LSBs. For bipolar applications, the gain error is measured from the midscale transition to both the first and last code transitions. The ideal difference in this case is FS/2-1 LSB. The gain error is defined as the deviation between the ideal difference, given above, and the measured difference. For the bipolar case, there are two gain errors; the figure in the specification page represents the worst case. Ideal FS depends on the +5REF input; for the 0 V to 5 V input, ideal FS = +5REF and for the 0 V to 10 V and +5 V ranges, ideal FS = 2 x + 5REF.
CONVERTER DETAILS
The AD7886 operates from a 3.5 V reference, which must be provided at the VREF input. Two on-chip resistors for use with an external amplifier can be used for deriving 3.5 V from standard 5 V references. Figure 2 shows an example with the AD586 which a is a high performance voltage reference exhibiting excellent stability performance, 5 ppm/C max. The external amplifier serves a second function of force/sensing the VREF input. Force/sensing minimizes error contributions from
+V +VIN VOUT +5V +5REF R1 9k SUM R2 6.3k VREF
AD586
GND
AD7886*
AD707 - +
-3.5V
The AD7886 is a triple-pass flash ADC that uses 15 comparators in a 4-bit flash technique to perform the 12-bit conversion procedure. Each of the 4096 quantization levels is realized internally with a precision resistor DAC. The fifteen comparators first compare the analog input voltage to the VREF/16 voltages of the resistor array. This determines the four most significant bits and selects 1 out of 16 voltage segments. The comparators are then switched to 15 subvoltages on that segment to determine the next four bits and select 1 out of 256 voltage segments. A further switching of the comparators to another 15 subvoltages produces the complete 12-bit conversion REV. B -5-
C1 10F
TO DAC AGND C2 0.1F
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 2. Typical Reference Circuitry
AD7886
this amplifier typically by 20 MHz which is much greater than the Nyquist limit of the ADC; as a result, it can be used for undersampling applications. The track-and-hold amplifier acquires the input signal to 12-bit accuracy in less than 333 ns. The overall throughput time is equal to the conversion time plus the track/ hold amplifier acquisition time, which is 1.333 s for the AD7886.
+V + 5V AIN VIN1 0 TO 5V OR 0 TO 10V VDD
VIN2**
AGND
The operation of the track/hold amplifier is essentially transparent to the user. The track-to-hold transition occurs at the start of conversion on the falling edge of CONVST. The conversion procedure does not start until the rising edge of CONVST. The width of the CONVST pulse low time determines the track-to hold settling time. The track/hold reverts back to the track mode at the end of conversion when BUSY has returned high.
0 TO 5V ANALOG INPUT RANGE 3.5k 10k
+VIN VOUT + 5V
AD7886*
+ 5REF
AD586
GND SUM
AD707 - +
- 3.5V VREF
VIN1 VIN2 0 TO 5V
-
10k
VSS C1 10F C2 0.1F - 5V
+
TO COMPARATORS
0 TO 10V ANALOG INPUT RANGE 3.5k 0 TO 10V 10k
*ADDITIONAL PINS OMITTED FOR CLARITY **0 TO 5V RANGE: CONNECT VIN2 TO VIN1 0 TO 10V RANGE: CONNECT VIN2 TO AGND
Figure 4. Unipolar Operation
OUTPUT CODE
VIN1 VIN2
-
10k
+
TO COMPARATORS
11...111 11...110
5V ANALOG INPUT RANGE 3.5k
11...101 11...100
5V +5V
VIN1 VIN2
10k
-
10k
00...011
1LSB =
FS 4096
+
TO COMPARATORS
00...010 00...001
Figure 3. Analog Input Range Configurations
00...000
ANALOG INPUT RANGES
1
2
3
FS
The AD7886 has three user selectable analog input ranges: 0 V to 5 V, 0 V to 10 V and 5 V. Figure 3 shows how to configure the two analog inputs (VIN1 and VIN2) for these ranges.
UNIPOLAR OPERATION
VIN, INPUT VOLTAGE (LSBS) FS - 1LSB
Figure 5. Ideal Input/Output Transfer Characteristic for Unipolar Operation
Figure 4 shows a typical unipolar circuit for the AD7886. The ideal input/output characteristic is shown in Figure 5. The designed code transitions occur on integer multiples of 1 LSB. The output code is natural binary with 1 LSB = FS/4096. FS is either +5 V or +10 V, depending on how the analog inputs are configured.
-6-
REV. B
AD7886
OFFSET AND GAIN ADJUSTMENT BIPOLAR OPERATION
In most digital signal processing (DSP) applications, offset and full-scale errors have little or no effect on system performance. Offset error can usually be eliminated in the analog domain by ac coupling. Full-scale errors do not cause problems as long as the input signal is within the full dynamic range of the ADC. For applications requiring that the input signal range match the full analog input dynamic range of the ADC, offset and fullscale errors must be adjusted to zero.
UNIPOLAR OFFSET AND GAIN ERROR ADJUSTMENT
Bipolar operation is achieved by providing a +10 V span on the VIN1 input while offsetting the VIN2 input by +5 V. A typical circuit is shown in Figure 7. The output code is offset binary. The ideal input/output transfer characteristic is shown in Figure 8. The LSB size is (10/4096) V = 2.44 mV.
+ 5V
VDD
If absolute accuracy is an application requirement, offset and gain can be adjusted to zero. Offset error must be adjusted before gain error. Zero offset is achieved by adjusting the offset of the op amp driving the analog input (i.e., A1 in Figure 6). For zero offset error, apply a voltage of 1 LSB to AIN and adjust the op amp offset until the ADC output code flickers between 0000 0000 0000 and 0000 0000 0001. 0 V to 5 V Range: 1 LSB = 1.22 mV 0 V to 10 V Range: 1 LSB = 2.44 mV For zero gain, error apply an analog input voltage equal to FS-1 LSB (last code transition) at AIN and adjust R3 until the ADC output code flickers between 1111 1111 1110 and 1111 1111 1111. 0 V to 5 V Range: FS-1 LSB = 4.99878 V 0 V to 10 V Range: FS-1 LSB = 9.99756 V
+ 5V AIN 0 TO 5V OR 0 TO 10V
AIN 5V +V +VIN VOUT VIN1 VIN2 AGND + 5V + 5REF
AD586
GND SUM
AD707 - +
- 3.5V
AD7886*
VREF VSS
C1 10F
C2 0.1F - 5V
AD845 +
A1 VIN1 VDD
-
VIN2**
OUTPUT CODE
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 7. Bipolar Operation
+V AGND +VIN VOUT + 5V + 5REF R1 82k SUM
11...111 11...110 11...101 10...010 10...001 - FS +1LSB 2
AD586
GND
AD707
R3 5k
- +
- 3.5V
-1LSB +1LSB + FS - 1LSB 2 FS = 10V 1LSB = FS 4096
V REF
10...000 01...111 01...110
AD7886*
R2 56k C1 10F C2 0.1F VSS
01...101 00...001 00...000
- 5V *ADDITIONAL PINS OMITTED FOR CLARITY **0 TO 5V RANGE: CONNECT VIN2 TO VIN1 0 TO 10V RANGE: CONNECT VIN2 TO AGND
VIN, INPUT VOLTAGE - LSBs
Figure 6. Unipolar Operation with Gain Error Adjust
Figure 8. Ideal Input/Output Characteristics for Bipolar Operation
REV. B
-7-
AD7886
BIPOLAR OFFSET AND GAIN ADJUSTMENT
In applications where absolute accuracy is important, offset and gain error can be adjusted to zero. Offset is adjusted by trimming the voltage at the VIN1 or VIN2 input when the analog input is at zero volts. This can be achieved by adjusting the offset of an external amplifier used to drive either of these inputs (see A1 in Figure 9). The trim procedure is as follows: Apply zero volts at AIN and adjust the offset of A1 until the ADC output code flickers between 0111 1111 1111 and 1000 0000 0000. Gain error can be adjusted at either the first code transition (ADC negative full scale) or the last code transition (ADC positive full scale). Adjusting the reference, as in Figure 9, will trim the positive gain error only. The trim procedure is as follows: Apply a voltage of 4.99756 V, (FS/2-1 LSB) at AIN and adjust R3 until the output code flickers between 1111 1111 1110 and 1111 11111111. If the first code transition needs adjusting, a gain trim must be included in the analog signal path. The trim procedure will then consist of applying an analog signal of -4.99756 V (-FS/2+1 LSB) and adjusting the trim until the output code flickers between 0000 0000 0000 and 0000 0000 0001.
+ 5V AIN 5V
Data read operations are controlled by the CS and RD inputs. These digital inputs, when low, enable the AD7886's threestate output latches. Note, these latches cannot be enabled during conversion. In applications where CS and RD are tied permanently low, as in Figure 11, the data bus will go into the three-state condition at the start of conversion and return to its active state when conversion is complete. Tying CS and RD permanently low is useful when external latches are used to store the conversion results. The data bus becomes active before BUSY returns high at the end of conversion, so that BUSY can be used as a clocking signal for the external latches. A typical DSP application would have a timer connected to the CONVST input for precise sampling intervals. BUSY would be connected to the interrupt of a microprocessor that would be asserted at the end of every conversion. The microprocessor would then assert the CS and RD inputs and read the data from the ADC. For applications where both data reading and conversion control need to be managed by a microprocessor, a CONVST pulse can be decoded from the address bus. One decoding possibility is that a write instruction to the ADC address starts a conversion, and a read instruction reads the conversion result.
TRACK-TO-HOLD TRANSITION
AD845 +
A1 VIN1 VIN2 VDD
t 13
CONVST
t1
CONVERSION START HOLD TO TRACK TRANSITION
t12 t 10 t2 t4
-
CS
+V AGND +VIN VOUT + 5V + 5REF R1 82k R3 5k R2 56k SUM
t3
RD
t5 t CONV
t11 t7
DATA VALID
AD586
GND
BUSY
AD707 - 3.5V - VREF +
t6
DATA HIGH IMPEDANCE
AD7886*
C1 10F C2 0.1F VSS - 5V
Figure 10. Conversion Start and Data Read Timing Diagram
TRACK-TO-HOLD TRANSITION
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 9. Bipolar Operation with Gain Error Adjust
CONVST
t 13 t1
CONVERSION START
TIMING AND CONTROL
Conversion start is controlled by the CONVST input (see Figures 10 and 11). A high to low going edge on the CONVST input puts the track/hold amplifier into the hold mode. The ADC conversion procedure does not begin until a rising CONVST pulse edge occurs. The width of the CONVST pulse low time determines the track-to-hold settling time. The BUSY output, which indicates the status of the ADC, goes low while conversion is in progress. At the end of conversion BUSY returns high, indicating that new data is available on the AD7886's output latches. The track/hold amplifier returns to the track mode at the end of conversion and remains there until the next CONVST pulse. Conversion starts must not be attempted while conversion is in progress as this will cause erroneous results.
t5
BUSY
t 12 t CONV
HOLD TO TRACK TRANSITION
DATA VALID
t9
DATA
t8
HIGH IMPEDANCE
Figure 11. Conversion Start and Data Read Timing Diagram, (CS = RD = 0 V)
-8-
REV. B
AD7886
AD7886 DYNAMIC SPECIFICATIONS The AD7886 is specified for dynamic performance specifications as well as traditional dc specifications such as integral and differential nonlinearity. These ac specifications are required for signal processing applications such as speech recognition, spectrum analysis and high speed modems. These applications require information on the ADC's effect on the spectral content of the input signal. Hence, the parameters for which the AD7886 is specified include SNR, harmonic distortion, intermodulation distortion and peak harmonics. These terms are discussed in more detail in the following sections.
Signal-to-Noise Ratio (SNR)
Figure 13 shows a typical plot of effective number of bits versus frequency for a sampling frequency of 750 kHz. Input frequency range for this particular graph was limited by the test equipment to FS/4. The effective number of bits typically falls between 10.9 and 11.2, corresponding to SNR figures of 67.38 dB and 69.18 dB.
12
EFFECTIVE NUMBER OF BITS
11.5
SNR is the measured signal-to-noise ratio at the output of the ADC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (FS/2), excluding dc. SNR is dependent upon the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to noise ratio for a sine wave input is given by SNR = (6.02N + 1.76) dB (1) where N is the number of bits. Thus, for an ideal 12-bit converter, SNR = 74 dB. The output spectrum from the ADC is evaluated by applying a sine wave signal of very low distortion to the VIN input, which is sampled at a 750 kHz sampling rate. A Fast Fourier Transform (FFT) plot is generated from which the SNR data can be obtained. Figure 12 shows a typical 2048 point FFT plot with an input signal of 100 kHz and a sampling frequency of 750 kHz.
11
10.5 SAMPLING FREQUENCY = 750kHz TA = 25 C 10 0 INPUT FREQUENCY FS/4
Figure 13. Effective Number of Bits vs. Frequency
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7886, THD is defined as
THD = 20 log V 2 +V 3 +V 4 +V 5 +V 6 V1
2 2 2 2 2
(3)
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonic. The THD is also derived from the FFT plot of the ADC output spectrum.
Intermodulation Distortion (IMD)
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa - fb) while the third order terms include (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb). Using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental, expressed in dBs. In this case, the input consists of two, equal amplitude, low distortion sine waves. Figure 14 shows a typical IMD plot for the AD7886.
Peak Harmonic or Spurious Noise
Figure 12. AD7886 FFT Plot
The SNR obtained from this graph is 68 dB. It should be noted that the harmonics are taken into account when calculating the SNR.
Effective Number of Bits
The formula given in Equation 1 relates the SNR to the number of bits. Rewriting the formula, as in Equation 2, it is possible to obtain a measure of performance expressed in effective number of bits (N).
N= SNR -1.76 6.02
(2)
The effective number of bits for a device can be calculated directly from its measured SNR. REV. B
Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to FS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification will be
-9-
AD7886
determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, the peak will be a noise peak.
TIMER PA2 PA0 ADDRESS BUS
ADDR ENCODE MEN EN
CONVST CS
TMS320C10
INT DEN
AD7886*
BUSY RD DB11 DB0
D15 D0 DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY
Figure 14. AD7886 IMD Plot
MICROPROCESSOR INTERFACING
Figure 15. AD7886-TMS320C10 Interface
The AD7886 is designed to interface to microprocessors as a memory mapped device. Its CS and RD control inputs are common to all memory peripheral interfacing. Figures 15 to 21 demonstrate typical interfaces for the AD7886.
AD7886-TMS320C10/TMS32020
TIMER A15 ADDRESS BUS A0
Figures 15 and 16 show typical interfaces for the TMS320C10 and the TMS32020 DSP processors. An external timer controls conversion start to the processor. At the end of each conversion, the ADC's BUSY output interrupts the microprocessor. The conversion result can then be read from the ADC with the following instruction: IN D,ADC (ADC = ADC address)
AD788S ADSP-2100/TMS320C25/DSP56000
ADDR ENCODE IS EN
CONVST CS
TMS32020
INTn STRB R/W
AD7886*
BUSY RD DB11 DB0
Some of the faster DSP processors have data access times outside the capabilities of the AD7886. Interfacing to such processors requires the use of either a single WAIT state or external latches. Examples are shown in Figures 17, 18 and 19. The use of a single WAIT state for the TMS320C25 and the ADSP-2100 interfaces extends the read instruction to the ADC by one processor CLK OUT cycle. In the DSP56000 example, the ADC's data is first clocked into 74HC374 latches before being read by the processor. The AD7886's CS and RD inputs are tied permanently low, and the rising edge of BUSY updates the latches at the end of conversion. Both methods of overcoming the very fast data access time required by these processors are interchangeable, i.e., a WAIT state can be used for the DSP56000, eliminating the need for latches or vice or versa, for the other two interfaces. For all three interfaces, an external timer controls conversion start; the processor is interrupted at the end of each conversion by the ADC's BUSY output. The following instruction then reads data from the ADC: ADSP-2100 - MR = DM(ADC) TMS320C25 - IN D,ADC DSP56000 - MOVEP Y:ADC,XO Assuming the ADC is memory mapped into the top 64 locations in Y memory space. (ADC = ADC address) -10-
D15 D0
DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. AD7886-TMS32020 Interface
REV. B
AD7886
TIMER CLK OUT DMA13 DMA0 ADDR ENCODE DMS DMACK EN + 5V Q CLR CONVST CS ADDRESS BUS
AD7886-MC68000
AD7886*
74HC74 D
CLK BUSY RD DB11 DB0
ADSP-2100
IRQn DMRD
Applications requiring conversions to be initiated by the microprocessor rather than an external timer may decode a CONVST signal from the address bus. An example is given in Figure 20 with the MC68000 processor. A write instruction starts conversion while a read instruction reads the data when conversion is complete. A delay at least as long as the ADC conversion time must be allowed between initiating a conversion and reading the ADC data into the processor. In Figure 20, BUSY is used to drive the processor into a WAIT state if the processor attempts to read data before conversion is complete. Conversion is initiated with a write instruction to the ADC: Move.W D0,ADC (ADC = ADC address) Data is transferred to the processor with a read instruction; BUSY will force the processor to WAIT for the end of conversion if a conversion is in progress. Move.W ADC,DO
A15
DMD15 DATA BUS DMD0 *ADDITIONAL PINS OMITTED FOR CLARITY
(ADC = ADC address)
Figure 17. AD7886-ADSP-2100 Interface
A15 A0 ADDRESS BUS TIMER
ADDRESS BUS A0 ADDR ENCODE AS EN CS
TMS320C25
IS READY MSC STRB R/W INT
ADDR ENCODE EN
CONVST CS
CONVST
G2
AD7886*
R/W DTACK RD BUSY
RD BUSY DB11 DB0
D11 DATA BUS D0
AD7886* MC68000
DB11 DB0
D15 D0 DATA BUS *ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 18. AD7886-TMS320C25 Interface
A15 A0 X/Y DS ADDRESS BUS ADDR ENCODE CONVST CS RD TIMER
Figure 20. AD7886-MC68000 Interface
AD7886-Z-80/8085A
EN1 EN2
For 8-bit processors, an external latch is required to store four bits of the conversion result (4 LSBs in Figure 21). The data is then read in two bytes: one read from the ADC and a second from the latch. Figure 21 shows a typical interface suitable for the Z-80 or the 8085A. Not shown in the Figure is the 8-bit latch needed to demultiplex the 8085A common address/data bus. The following LOAD instruction reads the conversion result into the HL register pair: For the 8085A-LHLD For the Z-80-LDHL (ADC) (ADC = ADC address) (ADC) (ADC = ADC address)
IRQ
BUSY
AD7886*
RD OE Q11 CLK D11 D0 DB11 DB0
DSP56000
Q0
2X 74HC374
D23 DATA BUS D0 *ADDITIONAL PINS OMITTED FOR CLARITY
This is a two byte read instruction. The first byte to be read has to be the high byte (DB11 to DB4). At the end of the first read operation, the rising edge of CS and RD clocks the 4 LSBs into 74HC374 latches. The second byte (4 LSBs) is then read from these latches.
Figure 19. AD7886-DSP56000 Interface
REV. B
-11-
AD7886
A15 A0 ADDRESS BUS ADDR ENCODE MREQ RD INT EN RD BUSY
DATA ACQUISITION BOARD
TIMER
CONVST CS
Figure 23 shows a typical data acquisition circuit designed for a microprocessor environment. The corresponding PC board layout and silkscreen are shown in Figures 24 to 26. The analog input to the AD7886 is buffered with an AD845 op amp. A component grid is provided near the analog input on the PC board that may be used for an antialiasing filter or any other conditioning circuitry. To facilitate this option, a link (labeled LK4) is required on the analog input. An AD586 voltage reference and an AD707 op amp provide the appropriate reference biasing required by the AD7886. The ADC's data outputs are buffered with 74HC374 latches. These provide data bus isolation and improve data access time. Data access time is reduced to under 30 ns, allowing interfacing to virtually any microprocessor, including the high speed DSP processors. Data format can be either a complete parallel load for 16-bit processors or a two-byte load for 8-bit processors. INTERFACE CONNECTIONS There are two connectors labeled SKT3 and SKT4. SKT3 is a 96-contact (3-row) connector, which is directly compatible with the ADSP-2100 evaluation board prototype expansion connector. The expansion connector on the ADSP-2100 board has eight decoded chip enable outputs labeled ECE1 to ECE8. ECE6 is used to select the AD7886 data acquisition board. To avoid selecting on-board RAM sockets at the same time, LK6 on the ADSP-2100 board must be removed. In addition, the ADSP-2100 expansion connector has four interrupts labeled EIRQ0 to EIRQ3. The AD7886's BUSY output connects to EIRQ0. SKT3 pinout is shown in Figure 23. Data format to the ADSP-2100 connector is left justified, i.e., DB11 of the conversion result is connected to DMD15 of the connector. DMD3 to DMD0 are always zero. SKT4 is a 22-way (2 row) pin-header connector. This connector contains all the signal contacts as SKT3 with the exception of EDMACK and the 4 trailing zeros of the 16-bit data word. Only the 12-bit conversion results go to SKT4. The pinout is shown in Figure 22.
DB0 DB2 DB4 DB6 DB8 DB10 BUSY CS NC VCC 22 20 18 16 14 12 10 8 6 4 2 21 19 17 15 13 11 9 7 5 3 1 DB1 DB3 DB5 DB7 DB9 DB11 OUT1 OUT2 RD VCC DGND
OE
CLK D3 D0
AD7886*
DB3 DB0 DB11 DB4
Z-80 8085A
Q3 Q0
74HC374
D7 D0 DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. AD7886-Z-80/8085A Interface
APPLICATION HINTS Good printed circuit (PC) board layout is as important as the circuit design itself in achieving high speed A/D performance. The AD7886's comparators are required to make bit decisions on an LSB size of 1.22 mV. To achieve this, the designer has to be conscious of noise in both the ADC itself and in the preceding analog circuitry. Switching mode power supplies are not recommended as the switching spikes will feed through to the comparator, causing noisy code transitions. Other causes of concern are ground loops and digital feedthrough from microprocessors. These are factors that influence any ADC, and a proper PC board layout that minimizes these effects is essential for best performance.
LAYOUT HINTS
Ensure that the layout for the printed circuit board has the digital and analog signal lines separated as much as possible. Take care not to run any digital track alongside an analog signal track. Guard (screen) the analog input with AGND. Establish a single point analog ground (star ground) separate from the logic system ground at the AD7886 AGND or as close as possible to the AD7886. Connect all other grounds and the AD7886 DGND to this single analog ground point. Do not connect any other digital grounds to this analog ground point. Because low impedance analog and digital power supply common returns are essential to low noise operation of the ADC, make the foil width for these tracks as wide as possible. The use of ground planes minimizes impedance paths and also guards the analog circuitry from digital noise. The circuit layout of Figures 25 and 26 have both analog and digital ground planes that are kept separated and only joined together at the AD7886 AGND.
NOISE
Keep the input signal leads to VIN and signal return leads from AGND as short as possible to minimize input noise coupling. In applications where this is not possible, use a shielded cable between the source and the ADC. Reduce the ground circuit impedance as much as possible since any potential difference in grounds between the signal source and the ADC appears as an error voltage in series with the input signal. -12-
DGND
NC = NO CONNECT
Figure 22. SKT4 Pinout
REV. B
AD7886
POWER SUPPLY CONNECTIONS
The PC board requires two analog power supplies and one 5 V digital supply. Connections to the analog supply are made directly to the PC board as shown on the silkscreen in Figure 24. The connections are labeled V+ and V-, and the range for both of these supplies is 12 V to 15 V. Connection to the 5 V digital supply is made through either of the two connectors (SKT3 or SKT4). The +5 V analog supplies required by the AD7886 are generated from voltage regulators on the V- and V+ power supplies.
LINK OPTIONS
these latches are not required, they may be removed and the data digital paths shorted out, i.e., latch inputs Dx shorted to outputs Qx using wire links in the latch sockets. When using the latches, the AD7886 control inputs, CS and RD, must be tied low via links 2 and 3. The latches are updated by the rising edge of the BUSY signal at the end of every conversion. Data is then read by asserting the latch output enable signals. The alternative is to remove the latches and assert the ADC's control inputs from either of the connectors, SKT3 or SKT4, as outlined in the data sheet. Latches Included Insert Link 2 Insert Link 3
LK4 Analog Input Option
There are five link options, labeled LK1 to LK5, which must be set before using the board.
LK1 Input Range Select
Latches Removed Remove Link 2 Remove Link 3
The AD7886 can accommodate three possible analog input ranges: 0 V to 5 V, 0 to 10 V and +5 V. The link options are as follows: 0 V to 5 V 0 V to 10 V 5 V Use Link C Use Link B Use Link A
LK4 connects the analog input to a component grid or to a buffer amplifier that drives the ADC input.
LK5
LK2 and LK3 Control Input Options
The evaluation board includes two latches to increase the data access time when interfacing to the faster DSP machines. If
SKT3 96-WAY CONNECTOR + 5V DMD15 DMD8 ECE6 (OUT1) O/P EDMACK B6 LK5 GND + 5V C20 0.1F + 5V VCC Q7 74HC374 Q0 IC8 D7 D0 C19 10F +V IN OUT 78L05 IC5 GND VDD DB11 DB4 VREF + 5V
+ 5V
Data format can be 16-bits parallel or two bytes for 8-bit processors. There are two data enable controls for the 74HC374 latches, labeled OUT1 and OUT2. OUT1 enables the 8 MSBs (IC8), and OUT2 enables the 4 LSBs (IC9). Link options are: for 16-bit format, include LK5, for a two byte read format, remove LK5.
C8 0.1F
C7 10F C14 0.1F
+V C13 10F VOUT IC4 AD707 +VIN +V C6 0.1F C5 10F
A31 B11 B18 C22
VDD
+ 5REF
SUM - + -V C10 0.1F C11 10F C16 0.1F C15 10F
AD586 IC3
GND
CLK C23 0.1F
IC1 AD7886
DB3 DB0 VIN1
C11 B20 B27
OUT2 DMD7 DMD0
VCC D7 74HC374 D4 IC9 D3 O/P D2 Q7 D1 D0 Q0 GND CLK
+V VIN2 A B DGND LK1 C4 0.1F C3 10F
BUSY
C AGND - AD845 + -V C2 0.1F IC2 LK4 SKT2
A9 C14 C13 C12 A32/B32/ C32
EIRQ0 CS RD CONVST
CS RD AGND VSS - 5V C10/C18 0.1F C9/C17 10F
C1 10F
ANALOG INPUT
CONVST VSS LK2 LK3 -V IN OUT
DIGITAL GND
79L05 IC6
GND CONVST SKT1
Figure 23. Data Acquisition Circuit Using the AD7886
REV. B
-13-
AD7886
COMPONENT LIST
IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8, IC9
AD7886, 12-Bit Sampling ADC AD845, Op Amp AD586, Precision Voltage Reference AD707, Op Amp MC78L05, + 5 V Regulator MC79L05, -5 V Regulator 74HC04, Hex Inverter 74HC374, Octal Latches with Three-State Outputs
C1, C3, C5, C7, C9, C11, C13, C15 C17, C19, C21 C2, C4, C6, C8, C10, C12, C14, C16, C18, C20, C22, C23 SKT1, SKT2 SKT3 SKT4
10 F Capacitors
0.1 F Capacitors BNC Sockets 96-Contact (3 Row) Eurocard Connector 22-Way (2 Row) Pin Header and Socket
Figure 24. PC Board Silkscreen for Figure 23
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REV. B
AD7886
Figure 25. PC Board Component Side Layout for Figure 23
Figure 26. PC Board Solder Side Layout for Figure 23
REV. B
-15-
AD7886
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Pin Ceramic DIP (D-28)
C1485b-10-4/91
28-Pin PLCC (P-28A)
0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07)
26 25
0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07)
0.025 (0.63) 0.015 (0.38) 0.021 (0.53) 0.013 (0.33)
4 5 PIN 1 IDENTIFIER
TOP VIEW
(PINS DOWN) 11 12 19 18
0.050 (1.27) BSC
0.032 (0.81) 0.026 (0.66)
0.430 (10.92) 0.390 (9.91)
0.020 (0.50) R
0.456 (11.58) SQ 0.450 (11.43) 0.495 (12.57) SQ 0.485 (12.32)
0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16)
-16-
REV. B
PRINTED IN U.S.A.

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