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| 74F899 9-Bit Latchable Transceiver February 1989 Revised August 1999 74F899 9-Bit Latchable Transceiver with Parity Generator/Checker General Description The 74F899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction. It has a guaranteed current sinking capability of 24 mA at the A-bus and 64 mA at the B-bus. The 74F899 features independent latch enables for the A-to-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. Features s Latchable transceiver with output sink of 24 mA at the A-bus and 64 mA at the B-bus s Option to select generate parity and check or "feed-through" data/parity in directions A-to-B or B-to-A s Independent latch enables for A-to-B and B-to-A directions s Select pin for ODD/EVEN parity s ERRA and ERRB output pins for parity checking s Ability to simultaneously generate and check parity s May be used in systems applications in place of the 74F543 and 74F280 s May be used in system applications in place of the 74F657 and 74F373 (no need to change T/R to check parity) Ordering Code: Order Number 74F899SC 74F899QC Package Number M28B V28A Package Description 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagrams Pin Assignment for SOIC Pin Assignment for PCC Logic Symbol (c) 1999 Fairchild Semiconductor Corporation DS010195 www.fairchildsemi.com 74F899 Input Loading/Fan-Out HIGH/LOW Pin Names Description U.L. HIGH/LOW A0-A7 B0-B7 APAR BPAR ODD/EVEN GBA, GAB SEL LEA, LEB ERRA, ERRB Data Inputs/ Data Outputs Data Inputs/ Data Outputs A Bus Parity Input/Output B Bus Parity Input/Output Parity Select Input Output Enable Inputs Mode Select Input Latch Enable Inputs Error Signal Outputs 1.0/1.0 150/40 1.0/1.0 600/106.6 1.0/1.0 150/40 1.0/1.0 600/106.6 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA -3 mA/24 mA 20 A/-0.6 mA -12 mA/64 mA 20 A/-0.6 mA -3 mA/24 mA 20 A/-0.6 mA -12 mA/64 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA -1 mA/20 mA Pin Descriptions Pin Names A0-A7 B0-B7 APAR, BPAR ODD/EVEN GBA, GAB SEL LEA, LEB ERRA, ERRB A Bus Data Inputs/Data Outputs B Bus Data Inputs/Data Outputs A and B Bus Parity Inputs ODD/EVEN Parity Select, Active LOW for EVEN Parity Output Enables for A or B Bus, Active LOW Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode Latch Enables for A and B Latches, HIGH for Transparent Mode Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs Description Functional Description The 74F899 has three principal modes of operation which are outlined below. These modes apply to both the A-to-B and B-to-A directions. * Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEB (LEA) is HIGH and the Mode Select (SEL) is LOW, the parity generated from B[0:7] (A[0:7]) can be checked and monitored by ERRB (ERRA). * Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is HIGH. Parity is still generated and checked as ERRA and ERRB in the feed-through mode (can be used as an interrupt to signal a data/parity bit error to the CPU). * Independent Latch Enables (LEA and LEB) allow other permutations of generating/checking (see Function Table). www.fairchildsemi.com 2 74F899 Function Table Inputs Operation GAB H H H GBA H L L SEL LEA LEB X L L X L H X H H Busses A and B are 3-STATE. Generates parity from B[0:7] based on O/E (Note 1). Generated parity APAR. Generated parity checked against BPAR and output as ERRB. Generates parity from B[0:7] based on O/E. Generated parity APAR. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. Generates parity from B latch data based on O/E. Generated parity APAR. Generated parity checked against latched BPAR and output as ERRB. BPAR/B[0:7] APAR/A0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB. BPAR/B[0:7] APAR/A[0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. L L H H L L H H L H Generates parity for A[0:7] based on O/E. Generated parity BPAR. Generated parity checked against APAR and output as ERRA. Generates parity from A[0:7] based on O/E. Generated parity BPAR. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. Generates parity from A latch data based on O/E. Generated parity BPAR. Generated parity checked against latched APAR and output as ERRA. APAR/A[0:7] BPAR/B[0:7] Feed-through mode. Generated parity checked against APAR and output as ERRA. L H H H H APAR/A[0:7] BPAR/B[0:7] Feed-through mode. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. H = HIGH Voltage Level Note 1: O/E = ODD/EVEN L = LOW Voltage Level X = Immaterial H H H L L L L H H X X H L H H L L H H L H L H X L Functional Block Diagram 3 www.fairchildsemi.com 74F899 Absolute Maximum Ratings(Note 2) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) Twice the Rated IOL (mA) 4000V -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 10% VCC 5% VCC 5% VCC VOL Output LOW Voltage 5% VCC 10% VCC VTH VOLV VOLP IIL IIH IBVI IBVIT ICEX VID IOD IIL IIH+ IOZH Input Threshold Voltage Negative Ground Bounce Voltage Positive Ground Bounce Voltage Input Low Current Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown (I/O) Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input Low Current Output Leakage Current Current 4.75 3.75 -0.6 70 1.45 1.0 1.0 -0.6 5.0 7.0 0.5 50 0.55 V 10% VCC 2.5 2.4 2.0 2.7 2.7 0.5 V Min 2.0 0.8 -1.2 Typ Max Units V V V Min VCC Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -3 mA IOH = -15 mA (Bn, BPAR) IOH = -1 mA IOH = -3 mA IOL = 20 mA (An, APAR, ERRA, ERRB) IOL = 24 mA (An, APAR, ERRA, ERRB) 0.55 V V V mA A A mA A V A mA A Max Max Max Max Max 0.0 0.0 Max Max IOL = 64 mA (Bn, BPAR) 0.1V, Sweep Edge Rate must be > 1V/50 ns Observed on "quiet" output during simultaneous switching of remaining outputs Observed on "quiet" output during simultaneous switching of remaining outputs VIN = 0.5V VIN = 2.7V VIN = 7.0V (ODD/EVEN, GBA, GAB, SEL, LEA, LEB) VIN = 5.5V (An, Bn, APAR, BPAR) VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V VI/O = 2.7V (An, Bn, APAR, BPAR) Conditions www.fairchildsemi.com 4 74F899 DC Electrical Characteristics Symbol IIL+ IOZL IOS Parameter Output Leakage Current Output Short-Circuit Current -60 -100 IZZ ICCH ICCL ICCZ Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Min (Continued) Typ Max -650 -150 Units A VCC Max Max VI/O = 0.5V Conditions (An, Bn, APAR, BPAR) VOUT = 0V (An, APAR, ERRA, ERRB) VOUT = 0V (Bn, BPAR) VOUT = 5.25V VO = HIGH VO = LOW, GAB = LOW, GBA = HIGH, VIL = LOW VO = HIGH Z mA -225 500 132 178 160 155 210 190 A mA mA mA Max 0.0V Max Max Max AC Electrical Characteristics TA = +25C Symbol Parameter Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tS(H) tS(L) tH(H) tH(L) tW Propagation Delay An, APAR to Bn, BPAR Propagation Delay An, Bn to BPAR, APAR Propagation Delay An, Bn to ERRA, ERRB Propagation Delay ODD/EVEN to ERRA, ERRB Propagation Delay ODD/EVEN to APAR, BPAR Propagation Delay APAR, BPAR to ERRA, ERRB LEA/LEB to ERRA /ERRB Propagation Delay SEL to APAR, BPAR Propagation Delay LEB to An, APAR Propagation Delay LEA to Bn, BPAR Output Enable Time GBA or GAB to An, APAR or Bn, BPAR Output Disable Time GBA or GAB to An, APAR or Bn, BPAR Setup Time, HIGH or LOW An, Bn to LEA, LEB Hold Time, HIGH or LOW An, Bn to LEA, LEB Pulse Width for LEA, LEB 5.0 5.0 0 0 6.0 1.6 1.8 -1.7 -1.5 2.0 5.0 5.0 0 0 6.0 ns ns ns Figure 12, Figure 13 Figure 12, Figure 13 Figure 14 1.0 1.0 4.0 4.0 7.0 7.0 1.0 1.0 8.0 8.0 ns Figure 8, Figure 9 4.0 4.0 7.5 7.5 7.5 7.5 4.5 4.5 4.5 4.5 5.5 5.5 9.5 9.7 3.0 3.0 3.5 3.5 3.5 3.5 1.0 1.0 6.0 7.0 7.0 8.0 6.5 7.5 4.5 6.5 VCC = +5.0V CL = 50 pF Typ 7.5 8.5 12.0 12.5 12.0 12.5 7.5 8.0 7.5 8.5 9.0 9.5 13.0 Max 13.0 13.0 17.0 17.0 17.0 17.0 11.0 11.0 11.5 11.5 13.0 13.0 17.5 17.5 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 4.0 4.0 7.5 7.5 7.5 7.5 4.5 4.5 4.5 4.5 5.5 5.5 7.5 7.5 3.0 3.0 3.5 3.5 3.5 3.5 1.0 1.0 Max 14.0 14.0 18.0 18.0 18.0 18.0 12.0 12.0 12.5 12.5 14.0 14.0 18.0 18.0 11.0 11.0 11.0 11.0 11.0 11.0 11.0 11.0 ns Figure 8, Figure 9 ns ns ns Figure 1 Figure 2 Figure 3 Units Figure Number ns Figure 4 ns Figure 5 ns Figure 6 ns Figure 7 ns ns ns Figure 10 Figure 11 Figure 11 5 www.fairchildsemi.com 74F899 AC Path An, APAR Bn, BPAR (Bn, BPAR An, APAR) FIGURE 1. An BPAR (Bn APAR) FIGURE 2. An ERRA (Bn ERRB) FIGURE 3. www.fairchildsemi.com 6 74F899 AC Path (Continued) O/E ERRA O/E ERRB FIGURE 4. O/E BPAR (O/E APAR) FIGURE 5. APAR ERRA (BPAR ERRB) FIGURE 6. 7 www.fairchildsemi.com 74F899 AC Path (Continued) FIGURE 7. ZH, HZ FIGURE 8. ZL, LZ FIGURE 9. www.fairchildsemi.com 8 74F899 AC Path (Continued) SEL BPAR (SEL APAR) FIGURE 10. LEA BPAR, B[0:7] (LEB APAR, A[0:7]) FIGURE 11. TS(H), TH(H) LEA APAR, A[0:7] (LEB BPAR, B[0:7]) FIGURE 12. 9 www.fairchildsemi.com 74F899 AC Path (Continued) TS(L), TH(L) LEA APAR, A[0:7] (LEB BPAR, B[0:7]) FIGURE 13. FIGURE 14. www.fairchildsemi.com 10 74F899 Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M28B 11 www.fairchildsemi.com 74F899 9-Bit Latchable Transceiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 12 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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