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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1:5 Clock Distribution Chip
The MC100LVEL/100EL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible with the EL14 but is designed to operate in ECL or PECL mode for a voltage supply range of -3.0V to -3.8V ( or 3.0V to 3.8V). If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01F capacitor. The VBB output is designed to act as the switching reference for the input of the LVEL14 under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current. The LVEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.
MC100LVEL14 MC100EL14
20 1
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04
* * * * * *
50ps Output-to-Output Skew Synchronous Enable/Disable Multiplexed Clock Input 75k Internal Input Pulldown Resistors >2000V ESD Protection VEE Range of -3.0V to -5.5V
PIN DESCRIPTION PIN CLK SCLK EN SEL VBB Q0-4 FUNCTION Diff Clock Inputs Scan Clock Input Sync Enable Clock Select Input Reference Output Diff Clock Outputs
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
VCC 20
EN 19
VCC 18
NC 17
SCLK CLK 16 15 1 D Q 0
CLK 14
VBB 13
SEL 12
VEE 11
FUNCTION TABLE CLK L H X X X SCLK X X L H X SEL L L H H X EN L L L L H Q L H L H L*
* On next negative transition of CLK or SCLK
1 Q0 2 Q0 3 Q1 4 Q1 5 Q2 6 Q2 7 Q3 8 Q3 9 Q4 10 Q4
7/95
(c) Motorola, Inc. 1996
4-1
REV 1
MC100LVEL14 MC100EL14
ABSOLUTE MAXIMUM RATINGS1
Symbol VEE VI Iout TA Power Supply (VCC = 0V) Input Voltage (VCC = 0V) Output Current Continuous Surge Characteristic Rating -8.0 to 0 0 to -6.0 50 100 -40 to +85 Unit VDC VDC mA C V
Operating Temperature Range
VEE Operating Range1,2 -5.7 to -4.2 1. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet. 2. Parametric values specified at: 100EL Series: -4.20V to -5.50V 10EL Series: -4.94V to -5.50V
DC CHARACTERISTICS (VEE = VEE(min) - VEE(max); VCC = GND1)
-40C Symbol VOH VOL VOHA VOLA VIH VIL IIL Characteristic Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current CLK Others Min -1085 -1830 -1095 -- -1165 -1810 -300 0.5 Typ -1005 -1695 -- -- -- -- -- Max -880 -1555 -- -1555 -880 -1475 -- Min -1025 -1810 -1035 -- -1165 -1810 -300 0.5 0C to 85C Typ -955 -1705 -- -- -- -- -- Max -880 -1620 -- -1610 -880 -1475 -- Unit mV mV mV mV mV mV A VIN = VIL(max) Condition VIN = VIH(max) or VIL(min) VIN = VIH(max) or VIL(min)
1. This table replaces the three tables traditionally seen in ECL 100K data books. The same DC parameter values at VEE = -4.5V now apply across the full VEE range of -3.0V to -5.5V. Outputs are terminated through a 50 resistor to -2.0V except where otherwise specified on the individual data sheets.
MOTOROLA
4-2
ECLinPS and ECLinPS Lite DL140 -- Rev 3
MC100LVEL14 MC100EL14
MC100LVEL14 AC/DC CHARACTERISTICS (VEE = -3.8V to -3.0V; VCC = GND)
-40C Symbol IEE Characteristic Power Supply Current 100LVEL 100EL Output Ref Voltage 100LVEL 100EL -1.43 -1.38 Min Typ 32 32 Max 40 40 -1.30 -1.26 150 520 470 470 720 770 770 200 50 0 0 150 -2.0 -1.8 230 -0.4 -0.4 500 0 0 150 -2.1 -1.9 230 -0.4 -0.4 500 550 500 500 -1.38 -1.38 Min 0C Typ 32 32 Max 40 40 -1.27 -1.26 150 750 800 800 200 50 0 0 150 -2.1 -1.9 230 -0.4 -0.4 500 580 530 530 680 680 680 -1.35 -1.38 Min 25C Typ 32 32 Max 40 40 -1.25 -1.31 -1.26 -1.38 150 780 830 830 200 50 0 0 150 -2.1 -1.9 230 -0.4 -0.4 500 ps 630 580 580 Min 85C Typ 34 34 Max 42 42 -1.19 -1.26 150 830 880 880 200 50 V ps Unit mA
VBB IIH tPLH tPHL tSKEW tS tH VPP VCMR
Input High Current Prop Delay CLK to Q (Diff) CLK to Q (SE) SCLK to Q
Part-to-Part Skew Within-Device Skew1 Setup Time EN Hold Time EN
Minimum Input Swing CLK
ps ps ps mV V
Common Mode Range2 VPP < 500mV VPP 500mV Output Rise/Fall Times Q (20% - 80%)
tr tf
1. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions. 2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = -3.3V. Note for PECL operation, the VCMR(min) will be fixed at 3.3V - |VCMR(min)|.
MC100EL14 AC/DC CHARACTERISTICS (VEE = -4.2V to -5.5V; VCC = GND)
-40C Symbol IEE Characteristic Power Supply Current 100LVEL 100EL Output Ref Voltage 100LVEL 100EL -1.43 -1.38 Min Typ 32 32 Max 40 40 -1.30 -1.26 150 520 470 470 720 770 770 200 50 0 0 150 -3.2 -3.0 230 -0.4 -0.4 500 0 0 150 -3.3 -3.1 230 -0.4 -0.4 500 550 500 500 -1.38 -1.38 Min 0C Typ 32 32 Max 40 40 -1.27 -1.26 150 750 800 800 200 50 0 0 150 -3.3 -3.1 230 -0.4 -0.4 500 580 530 530 680 680 680 -1.35 -1.38 Min 25C Typ 32 32 Max 40 40 -1.25 -1.31 -1.26 -1.38 150 780 830 830 200 50 0 0 150 -3.3 -3.1 230 -0.4 -0.4 500 ps 630 580 580 Min 85C Typ 34 34 Max 42 42 -1.19 -1.26 150 830 880 880 200 50 V ps Unit mA
VBB IIH tPLH tPHL tSKEW tS tH VPP VCMR
Input High Current Prop Delay CLK to Q (Diff) CLK to Q (SE) SCLK to Q
Part-to-Part Skew Within-Device Skew1 Setup Time EN Hold Time EN
Minimum Input Swing CLK
ps ps ps mV V
Common Mode Range2 VPP < 500mV VPP 500mV Output Rise/Fall Times Q (20% - 80%)
tr tf
1. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions. 2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = -4.5V. Note for PECL operation, the VCMR(min) will be fixed at 5.0V - |VCMR(min)|.
ECLinPS and ECLinPS Lite DL140 -- Rev 3
4-3
MOTOROLA
MC100LVEL14 MC100EL14
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE E
-A20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0 7 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0 7 0.395 0.415 0.010 0.029
-B-
P 10 PL 0.010 (0.25)
M
B
M
1
10
D
20 PL
J
M
0.010 (0.25)
T
A
S
B
S
F R X 45 C -TG
18 PL SEATING PLANE
K
M
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MOTOROLA 4-4
*MC100LVEL14/D*
MC100LVEL14/D ECLinPS and ECLinPS Lite DL140 -- Rev 3

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