View STA400A_72164.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STA400A
XMRADIO SDARS CHANNEL DECODER
FRONT END INTERFACE s TWO INTERNAL 10 BIT A/D CONVERTERS s TWO QPSK DEMODULATORS FOR SATELLITE BRANCH s ONE MULTICARRIER DEMODULATOR FOR TERRESTRIAL BRANCH s SATELLITE SYMBOL FREQUENCY: 1.64 MBAUD s TERRESTRIAL SYMBOL FREQUENCY: 2.99 MBAUD s DIGITAL ROOT RAISED COSINE NYQUIST FILTER: 15% ROLL-OFF s FFT LENGTH: 768 SUB-CARRIERS s FULL DIGITAL CARRIER AND FREQUENCY RECOVERY AND TRACKING LOOPS s FREQUENCY INVERSION COMPENSATION FOR HIGH-SIDE/LOW-SIDE MIXER INJECTION s LOCK DETECTORS, C/N INDICATOR, ON CHIP BER ESTIMATORS s TWO DIGITAL AGCs: INTERNAL SIGNAL POWER ESTIMATION AND FILTERING s 1 BIT PDM AGCs CONTROL SIGNAL OUTPUTS TDM DECODING AND MANAGEMENT s SATELLITE AND TERRESTRIAL FRAME SYNCHRONIZATION s SATELLITE PHASE AMBIGUITY RESOLUTION s TDM DEMULTIPLEXING s PRIME RATE CHANNEL (PRC) DEMULTIPLEXING s EXTERNAL MEMORY CONTROLLING FORWARD ERROR CORRECTION s VITERBI DECODER: K=7, R=1/3 s SATELLITE DEPUNCTURING: RATE 3/4 s TERRESTRIAL DEPUNCTURING: RATE 3/5 s CONVOLUTIONAL TIME DEINTERLEAVER OVER 4.7 SEC s BLOCK DEINTERLEAVER OVER 2 RS BLOCKS s REED-SOLOMON DECODER: (255,223). UP TO 16 BYTES CORRECTION CAPABILITY.
September 2003
(R)
TQFP144 ORDERING NUMBER: STA400A
T H I S D E V I C E C A N B E S O L D O N LY TO CUSTOMERS THAT HAVE SIGNED A LICENSE AGREEMENT WITH XM SATELLITE RADIO.
s s
ENERGY DISPERSAL DESCRAMBLER SAT-SAT AND TERR-SAT DIVERSITY COMBINING
BACK END INTERFACE s TWO PAYLOAD CHANNEL BITSTREAM INTERFACES s PAYLOAD CHANNEL SELECTION LOGIC s DESIGNED TO WORK WITH THE STA450A SERVICE AND SOURCE DECODER LOW POWER TECHNOLOGY s 1.8V, 0.18m TECHNOLOGY s 3.3V CAPABLE I/Os CONTROL s IIC-BUS SLAVE CONTROL INTERFACE s DEVICE ADDRESS: 1101010 DESCRIPTION The SDARS is a satellite transmission system based on two geostationary satellites on the East and West coasts of the Continental United States (CONUS). In the urban areas, where the line of sight reception of the satellites is difficult or not possible, the service is covered by terrestrial repeaters adopting a MultiCarrier Modulation scheme. Designed for digital radio receivers compatible with the XMRadio SDARS System, the STA400A Channel Decoder integrates all the functions to demodu1/117
LOCK_M
MAI1
MAO1
MAO2
MADD[11:0]
MDQ[7:0]
MDQM
MWE
CAS
RAS
MCS1
MCS0
MCKE
MBS1
TAGC
Terr AGC
TREFM TREFP TADCREF TINCM TVCMO
MBS0
SCL
MCLKO
CLKD
INTR
SDA
TEST_EN
BIST_EN
MCLKON
SCAN_EN
FTESTEN
FTESTOUT[15:0]
2/117
External Memory Controller
Terr.FIFO
BER Meas.
STA400A
IF2TA_P
IF2TA_N
10 bit ADC Terrestrial Multi Carrier Demodulator
FIFO Sat.FIFO
IF2TD[9:0]
Terr.TDM Synch. and Descrambling
Sat/Sat Weighting & Combining Depuncturing Viterbi Decoder
ADCSEL
Figure 1. Channel Decoder Block Diagram
Satellite 1 QPSK Demodulator
FIFO
Sat1 TDM Synch. and Descrambling
Terr./Sat. Combining RS Decoder
IF2SD[7:0]
TDM Demux
FEC
FIFO
Sat1&2 Weighting Factor Calculation
IF2SA_N
IF2SA_P
8 bit ADC
PCBS1 PCDC1
FIFO
PC Bitstream Interface #1
PRC Demux Controller
PC Port #1
PCSD1 PCFS1 PCTS_EF1
SREFM SREFP SADCREF SINCM SVCMO
Satellite 2 QPSK Demodulator
Sat2 TDM Synch. and Descrambling
SAGC
PCBS2 PCDC2 PCSD2 PCFS2 PCTS_EF2
Sat AGC
TDM Decoding TDM Management
LOCK_S1
PC Bitstream Interface #2
PC Port #2
LOCK_S2
MFP_CLK
MRESET
XTI/MCLK
late and decode the incoming satellite and terrestrial signals after the RF Front-End down-convertions: Analogto-Digital conversions, satellite and terrestrial demodulations, AGCs, frame synchronization and demultiplexing, Viterbi decoding, time and spatial diversity combining, Reed-Solomon decoding and deinterleaving, Prime Rate Channel (PRC) demultiplexing, Payload Channel (PC) selection. At the end of the demodulation and decoding processes a configurable serial data stream is made available to STA450A, the Service/Source Decoder, via the PC BitStream interface.
XTO
Clock Distribution
Microprocessor Interface
Test Interface
STA400A
Figure 2. Pin Connection (Top view)
FTESTOUT5 VDD3 VSS FTESTOUT4 FTESTOUT3 FTESTOUT2 FTESTOUT1 FTESTOUT0 MWE CAS RAS VDD VSS MDQ7 MDQ6 MDQ5 MDQ4 MDQ3 MDQ2 MDQ1 MDQ0 MDQM MCS1 MCS0 VDD3 VDD VSS MCKE MBS1 MBS0 MADD11 MADD10
140 139 138 137 135 134 136 133 132 131 126 129 130 128 127 125 124 123 122 121 120 119 118 117 116 115 114 113 112 109 111 110
144
143
142
FTESTOUT10 FTESTOUT11 FTESTOUT12 FTESTOUT13 FTESTOUT14 FTESTOUT15 VDD VDD3 VSS TREFM TREFP TADCREF TINCM IF2TA_P IF2TA_N TVCMO AVDD AGND SVCMO IF2SA_N IF2SA_P SINCM SADCREF SREFP SREFM AVDD AGND MRESET TAGC SAGC VSS XTO XTI/MCLK ADCSEL MCLKO MCLKON
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
69 67 64 60 56 51 50 43 44 38 37 39 40 41 42 45 46 47 48 49 53 54 52 55 57 58 59 61 62 63 65 66 68 70 71 72
141
FTESTOUT9 FTESTOUT8 FTESTOUT7 FTESTOUT6
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
MFP_CLK VSS MADD9 MADD8 MADD7 MADD6 VDD3 VSS MADD5 MADD4 MADD3 MADD2 MADD1 MADD0 NC NC MAI1 VDD VSS NC MAO2 MAO1 PCBS1 PCDC1 VSS PCSD1 PCFS1 VDD3 VDD PCTS_EF1 PCBS2 PCDC2 PCSD2 PCFS2 PCTS_EF2 BIST_EN
PIN DESCRIPTION
Pin N [1:6] 7,40,55, 67,80,91, 115,129, 8,39,66, 81,102, 116,139 Pin Name FTESTOUT[10:15] VDD Type O PWR Function Configurable Functional Test Output 1.8V Positive Supply Voltage PAD Description 2mA Output Driver
VDD3
PWR
3.3V Positive Supply Voltage
9,31,41, VSS 54,68,84, 90,101,107 ,114,128, 138
GND
Digital Ground
IF2SD7 IF2SD6 IF2SD5 IF2SD4 IF2SD3 IF2SD2 IF2SD1 IF2SD0 VDD3 VDD VSS SCL SDA TEST_EN SCAN_EN
LOCK_S1 LOCK_S2 VDD3 VDD VSS IF2TD9 IF2TD8 IF2TD7 IF2TD6 IF2TD5 IF2TD4 IF2TD3 IF2TD2 IF2TD1 IF2TD0 FTESTEN INTR VSS VDD CLKD LOCK_M
3/117
STA400A
PIN DESCRIPTION (Continued)
Pin N 10 Pin Name TREFM Type Analog Vref Analog Vref Function Terr. ADC Reference Negative Voltage. Bottom of the reference ladder (driven or filtered). Terr. ADC Reference Positive Voltage. Top of the reference ladder (driven or filtered). PAD Description Analog Pad Buffer (1)
11 12 13 14 15 16 17,26 18,27 19 20 21 22 23 24 25
TREFP TADCREF TINCM IF2TA_P IF2TA_N TVCMO AVDD AGND SVCMO IF2SA_N IF2SA_P SINCM SADCREF SREFP SREFM
Analog Pad Buffer (1) Analog Pad Buffer (1) Analog Pad Buffer (1) Analog Pad Buffer (1) Analog Pad Buffer (1) Analog Pad Buffer (1)
Analog Terr. ADC Reference Adjust (external resistor Terminal to determine Ipol) Analog Output Analog Input Analog Input Terr. ADC Internal Common-Mode output for bypassing Terr. 2nd IF Differential Input - Positive Terr. 2nd IF Differential Input - Negative
Analog Terr. ADC Internal Common Mode (filtered) Terminal PWR GND Analog Positive Supply Voltage (1.8V) Analog Ground
Analog Sat. ADC Internal Common Mode Terminal (filtered) Analog Input Analog Input Analog Output Sat. 2nd IF Differential Input - Negative Sat. 2nd IF Differential Input - Positive Sat. ADC Internal Common-Mode output for bypassing
Analog Pad Buffer (1) Analog Pad Buffer (1) Analog Pad Buffer (1) Analog Pad Buffer (1) Analog Pad Buffer (1) Analog Pad Buffer (1) Analog Pad Buffer (1)
Analog Sat. ADC Reference Adjust (external resistor Terminal to determine Ipol) Analog Vref Analog Vref I O O O I I Sat. ADC Reference Positive Voltage. Top of the reference ladder (driven or filtered). Sat. ADC Reference Negative Voltage. Bottom of the reference ladder (driven or filtered). Master Reset Terr. AGC Control Signal Sat. AGC Control Signal XTAL Output XTAL Input or Master Clock Input Selection between Internal or External ADC 0=Internal
28 29 30 32 33 34
MRESET TAGC SAGC XTO XTI/MCLK ADCSEL
Schmitt Trigger Buffer 2mA Output Driver 2mA Output Driver Oscillator Buffer Analog Pad Buffer (2) Buffer with Pull-Down
4/117
STA400A
PIN DESCRIPTION (Continued)
Pin N 35 36 37 38 [42:51] 52 53 56 57 [58:65] 69 70 71 72 73 74 75 76 77 78 79 82 83 85 86 87 88 89,93,94 92 Pin Name MCLKO MCLKON LOCK_S1 LOCK_S2 IF2TD[9:0] FTESTEN INTR CLKD LOCK_M IF2SD[7:0] SCL SDA TEST_EN SCAN_EN BIST_EN PCTS_EF2 PCFS2 PCSD2 PCDC2 PCBS2 PCTS_EF1 PCFS1 PCSD1 PCDC1 PCBS1 MAO1 MAO2 NC MAI1 I Type O O O O I I O O O I I I/O I I I O O O O O O O O O O O O Function Master Clock Output Inverted Master Clock Output Satellite Dem1 Lock Indicator Satellite Dem2 Lock Indicator Terr. 2nd IF Digital Input Functional Test Enable (1=enable) Interrupt Divided Master Clock Terrestrial Demodulator Lock Indicator Sat. 2nd IF Digital Input IIC-bus Serial Clock IIC-bus Serial Data ATPG Test Enable (1=Enabled) Scan Enable (1=Enabled) RAM Bilt In Self Test Enable (1=Enabled) Payload Channel TSCC Sync2/ErrorFlag 2 (432 msec) Payload Channel PRC Frame Sync 2 Payload Channel Serial Data 2 Payload Channel Data Clock 2 Payload Channel Byte Sync2 (RS Symbol) Payload Channel TSCC Sync1/ ErrorFlag1 (432 msec) Payload Channel PRC Frame Sync1 Payload Channel Serial Data 1 Payload Channel Data Clock 1 Payload Channel Byte Sync1 (RS Symbol) Mobile Adapter Output #1 Mobile Adapter Output #2 Not Connected. Mobile Adapter Input Buffer with Pull-Down PAD Description 4mA Output Driver 4mA Output Driver 2mA Output Driver 2mA Output Driver Input Pad Buffer. High Drive. Buffer with Pull-Down 2mA Output Driver 2mA Output Driver 2mA Output Driver Input Pad Buffer. High Drive Schmitt Trigger Buffer Schmitt Trigger BiDir Buffer. 4mA Driver Buffer with Pull-Down Buffer with Pull-Down Buffer with Pull-Down 2mA Output Driver 2mA Output Driver 2mA Output Driver 2mA Output Driver 2mA Output Driver 2mA Output Driver 2mA Output Driver 2mA Output Driver 2mA Output Driver 2mA Output Driver 2mA Output Driver 2mA Output Driver
5/117
STA400A
PIN DESCRIPTION (Continued)
Pin N [95:100] [103:106] 108 [109:110] [111:112] 113 [117:118] 119 [120:127] 130 131 132 [133:137] [140:144] Pin Name MADD[0:5] MADD[6:9] MFP_CLK MADD[10:11] MBS[0:1] MCKE MCS[0:1] MDQM MDQ[0:7] RAS CAS MWE FTESTOUT[0:4] FTESTOUT[5:9] Type O O O O O O O O I/O O O O O O Function External Memory Address External Memory Address TDM Master Frame Clock External Memory Address External Memory Block Selection External Memory Clock Enable External Memory Chip Select External Memory Data Mask External Memory Data Input Output External Memory Row Address Strobe External Memory Column Address Strobe External Memory Write Enable Configurable Functional Test Output Configurable Functional Test Output PAD Description 2mA Output Driver 2mA Output Driver 2mA Output Driver 2mA Output Driver 2mA Output Driver 2mA Output Driver 2mA Output Driver 2mA Output Driver BiDir Buffer. 2mA Driver 2mA Output Driver 2mA Output Driver 2mA Output Driver 2mA Output Driver 2mA Output Driver
1. Direct connection to core 2. Connected to the internal oscillator buffer via 460 Ohm series resistor
ABSOLUTE MAXIMUM RATINGS
Symbol VDD, AVDD VDD3 Vi Vo Via Voa Tstg Toper Tj 1.8V Power supply Voltage 3.3V Power Supply Voltage Voltage on input pin Voltage on output pin Voltage on analog input pin Voltage on analog output pin Storage Temperature Operative Ambient Temperature Operative Junction Temperature Parameter Value -0.5 to 2.5 -0.5 to 4 -0.5 to (Vdd3 + 0.5) -0.5 to (Vdd3 + 0.5) -0.8 to (AVdd + 0.8) -0.8 to (AVdd + 0.8) -55 to +150 -40 to +85 -40 to +125 Unit V V V V V V C C C
THERMAL DATA
Symbol Rj-amb Parameter Thermal Resistence junction to ambient(1) Value 40 Unit C/W
Notes: 1. according to JEDEC specification on a 4 layers board
6/117
STA400A
DC ELECTRICAL CHARACTERISTCS: (Tamb = -40 to +85C, VDD = AVDD = 1.65 to 1.95V, VDD3 = 3.0 to 3.6V unless otherwise specified).
Symbol VDD VDD3 AVDD IDD Parameter 1.8V Supply Voltage 3.3V Supply Voltage 1.8V Analog Supply Voltage VDD Power Supply Current MCLK = 23.92MHz; sat1, sat2 & terr arms active; VDD=1.95V MCLK = 23.92MHz; sat1, sat2 & terr arms active; VDD3=3.6V MCLK = 23.92MHz; VIN=0.75Vpp; fIN=6.095MHz; AVDdsat=1.95V MCLK = 23.92MHz; VIN=0.75Vpp; fIN=2.99MHz; AVDdterr =1.95V MCLK = 23.92MHz; VDD = 1.8V; VDD3 = 3.3V Vi = 0V Vi = VDD3 Vo = 0V or VDD3 Vi = VDD3 Vi = 0V Vi = VDD3 30 50 50 0.8 2 0.8 1.3 0.3 Iol = XmA Ioh = XmA 2.8 1.2 1.9 2.1 200 Leakage<1A 4000 1.35 2 0.8 0.2 Conditions Min 1.65 3.0 1.65 Typ 1.8 3.3 1.8 130 Max 1.95 3.6 1.95 160 Unit V V V mA
IDD3 IAVDDsat
VDD3 Power Supply Current AVDdsat Power Supply Current
45 16
90 20
mA mA
IAVDDterr
AVDdterr Power Supply Current
16
20
mA
Pd Iil Iih IOZ Ipd Rpu Rpd Vil Vih Vilhyst Vihhyst Vhyst Vol Voh Cin Cout Cio Ilatchup VESD
Power Dissipation Low level input leakage current 1) High level input leakage current 1) Tristare output leakage current 2) Pull-down current Equivalent pull-up resistance 7) Equivalent pull-down resistance 7) Low level input voltage High level input voltage Low level threshold input falling High level threshold input rising Schmitt trigger hysteresis3) Low level output voltage 4,5) High level output voltage 4,5) Input capacitance 3) Output Capacitance 3) I/O (bi-directional) capacitance 3) I/O Latch-up current Electrostatic Protection 6)
350 1 1 1 110
mW A A A A K k V V V V V V V pF pF pF mA V
Note 1: Performed on all the input pins excluded the pull-down ones Note 2: Performed on the I/O pins in tristate mode Note 3: Guaranteed by Design Note 4: take into account 200mV voltage drop in supply lines and Input/Output levels for frequency > 20MHz. Note 5. X is the source/sink current under worst case conditions (X = 2 to 4 mA) Note 6: Human body Model Note 7. Guaranteed by Ipd measurements
7/117
STA400A
ADC ELECTRICAL CHARACTERISTCS: (Tamb = -40 to +85C, VDD =1.8V, AVDD = 1.65 to 1.95V, VDD3 = 3.3V unless otherwise specified ADC Analog Input
Symbol IF2xA_P, IF2xA_N XINCM Rin (1) Cin BW Parameter Voltage Range Internal Common Mode Input Resistance 2) Input Capacitance 2) Analog Bandwidth 2) @75MHz 0.375 35 800 200 Conditions Min Typ 0.75 0.625 Max Unit Vpp V k fF MHz
ADC Reference Voltage
Symbol XREFP XREFM Parameter Top internal voltage reference Bottom internal voltage reference Conditions Min Typ 0.75 50mV 0 Max Unit V V
ADC Accuracy
Symbol DNL INL Parameter Differential Non-Linearity Integral Non-Linearity Conditions Tamb = 25C ; AVDD = 1.8V Tamb = 25C; AVDD = 1.8V Min -1.5 -2.0 Typ 0.9 1.5 Max 1.5 2.0 Unit LSB LSB
ADC Dynamic Characteristics
Symbol SNR SINAD Parameter Signal to Noise Ratio 2) Signal to Noise and 2) Distortion Ratio Conditions Fs = 75Msps, Fin = 15MHz; AVDD = 1.8V Fs = 75Msps, Fin = 15MHz AVDD = 1.8V Min Typ 57 56 Max Unit dB dB
THD ENOB
Total Harmonic Distortion 2) Fs = 75Msps, Fin = 15MHz AVDD = 1.8V Effective number of bit 2) Fs = 10Msps, Fin = 10MHz AVDD = 1.8V
57 9.5
dB bit
Note1: Input resistance from conversion frequency fC: RIN = (35K x 75MHz)/fC Note2: Guaranteed by Design
MASTER CLOCK INPUT ELECTRICAL CHARACTERISTCS: (Tamb = -40 to +85C, VDD =1.65 to 1.95V, AVDD = 1.65 to 1.95V, VDD3 = 3.0 to 3.6V unless otherwise specified)
Symbol VMCLK VMCLKOFS Parameter Master clock input voltage swing Master clock input Voltage offset Conditions Min 0.8 Typ 1 Vdd/2 Max 1.2 Unit Vpp V
8/117
STA400A
OSCILLATOR BUFFER ELECTRICAL CHARACTERISTICS The Oscillator Pad Buffer is a single stage oscillator with an inverter working as an amplifier biased by an internal resistor (>1 MOhm). With an external PI network consisting of a crystal and two capacitors it works as oscillator, without the external crystal component it acts as input trigger. Pin XTI (analog pad buffer) is the input for the external clock source or for the quartz component, XTO is the oscillator buffer output pin to be connected to the external quartz. Oscillator Mode Specification (Guaranteed by Design) Condition: 27 MHz oscillation - PI quartz network connected to XTI and XTO (CA = CB = 16pF).
Symbol Ci Cp DC tstart-up Symbol Hys Hysteresis Parameter Current Consumption Power Consumption Duty Cycle Start-up Time Parameters VL 0.631 49.07 49.60 3 VH 1.123 Hysteresis 0.492 Min Typ Max 450 810 49.86 Unit A W % ms Unit V
Input Trigger Mode Specification (no crystal connected) (Guaranteed by Design) Condition: 27 MHz sine wave (0.5V amplitude, VDD/2 offset) applied to XTI.
Symbol Ci Cp DC Parameters Current Consumption Power Consumption Duty Cycle Min Typ 133 240 49.45 Max Unit A W %
The external analog signal to be applied to the XTI input must be a sinusoid or a impulse wave centered at Vdd/ with 1V peak-to-peak amplitude. Minimum Oscillator Transconductance (Guaranteed by Design)
Symbol gmcrit Patrameters Min Typ 1236 Max Unit A/V
The oscillator pad buffer can work with different crystal frequencies. To check if a given quartz can be used with this oscillator, the needed amplifier transconductance must be evaluated by the following formula:
( CA CB + C A C O + CB CO ) = Rm -------------------------------------------------------------------------------CA CB
2 2
gm crit
if
C A = CB = C
the equation simplifies to:
gm crit = Rm ( C + 2 CO )
2 2
where Rm is the quartz equivalent series resistance, CA and CB the PI network capacitances and CO the quartz shunt capacitance. The transconductance of the oscillator pad given in the table above must be 8/9 times the transconductance calculated with the formula.
9/117
STA400A
1 FUNCTIONAL DESCRIPTION
The main inputs of the STA400A Channel Decoder are the 2nd IF analog signals centered at 6.095 MHz for the satellite and at 2.99 MHz for the terrestrial branch. The final down-convertion to baseband of the three signals is digitally performed inside the chip. After the demodulation process, the three TDM data streams are available and stored into the external memory for further digital processing including TDM decoding and demultiplexing, time and spatial diversity combining, FEC processing and data stream generation for the external source decoding. The external memory and the PRC-based packed structure of the service layer allow the use of one Viterbi decoder and RS decoder for the FEC processing of both the combined satellite and terrestrial frames. The STA400A is designed to work with the STA450A Service/Source Decoder, an external RF Tuner and a 128Mbit Synchronous DRAM. Figure 3 depicts the connection block diagram of the STA400A Channel Decoder and the external components. The 128Mbit SDRAM may be selected as a single 4Mx8Bitx4Banks or as a dual 2Mx8Bitx4Banks Memory. In the latter case the MCS0 pin must be connected to the chip select input of the memory and the XMEM_TYPE register (address 0x0630) must be programmed with "0x01" (see section 2.8). STA400A is fully configurable via the I2C-bus interface. Figure 3. STA400A Connection Diagram
COMMAND INPUTS - 3
Mobile Adapter
SDRAM#0
CLOCK ENABLE
SDRAM#1
CLOCK
To Functional Test Interface
I/O MASK - 1 BANK ADDRESS - 2 DATA BUS - 8 ADDRESS BUS - 12
MAI1
MAO1
MAO2
MDQM
MWE CAS RAS
MDQ[7:0]
MBS[1:0]
FTESTOUT[15:0]
MADD[11:0]
MCLKON
MCKE
IF2TA_P
Terr ADC Diff. Input
IF2TA_N
MCS0 MCS1
CHIP SELECT
IF2SA_P
Sat ADC Diff. Input
TUNER
10k 1u
IF2SA_N PCSD1 TAGC
AGCs Control
1u
DATA LINE CLK LINE
CHIP SELECT
PCSD PCDC PCFS PCTS_EF
STA400
PCDC1 PCFS1 PCTS_EF1 MFP_CLK
ADCSEL SAGC
10k
STA450
XTI/MCLK IF2SD[7:0] IF2TD[9:0] ADCSEL XTO
23.92 MHz
PLL_SYNC CLK_IN
INTR
MCLKO SDA IIC DATA LINE SCL IIC CLOCK LINE
22pF
22pF
TO MICROCONTROLLER
The 23.92 MHz system clock applied to XTI/MCLK input (pin 33) can be generated by the built-in clock buffer and an XTAL pi-network as showed in fig.3 or may come from an external source. In both cases the quartz or the external source must be compliant with the specifications given in the I/O Cell Description (section 3). In fig.3 the two embedded 10 bits ADCs are used to sample and convert to digital the satellite and terrestrial IF signals from the tuner. An internal mux, controlled by the ADCSEL input (pin 34), may be used to by-pass the
10/117
INTERRUPT LINE
From External Source
STA400A
two embedded ADCs. This functionality gives the possibility to use two external ADCs connected to the satellite digital input (IF2SD[7:0]) and to the terrestrial digital input (IF2TD[9:0]) respectively. The digital inputs must be tied to ground when not used. The FTESTOUT[15:0] pins are available for testing purpose and for measuring system performance. 1.1 IF SAMPLING AND CONTROL INTERFACE This block comprises the embedded ADCs, the satellite and terrestrial AGCs and CDEC CONTROL registers. It receives from the RF Front-End the two QPSK modulated satellite signals centered at 6.095 MHz and the MultiCarrier Modulated terrestrial signal centered at 2.99 MHz (2nd IF frequencies). These signals are over sampled by the 23.92 MHz master clock (MCLK) and converted to digital on 8 bits for the satellite composite signal and on 10 bits for the terrestrial signal (see fig.1). The programmable registers of the IF Sampling block are described in section 2.6. Embedded ADCs The two embedded ADCs are 10 bit high speed A/D converters designed for high sampling rate (up to 50 MHz) and low power consumption (1mW/MHz) with a full differential pipeline conversion architecture that needs 6 clock periods for one conversion. A voltage reference is integrated in the circuit for external components minimization but it is possible to use an external reference. The ADCs provide also a reduced input capacitance, a low reference capability and a wide input bandwidth (50MHz). Pins IF2xA_P IF2xA_N can be connected as full-differential inputs or as pseudo-differential input. In fig.4 the latter configuration is showed (x=S for Satellite and x=T for Terrestrial branch). Figure 4. ADC Pseudo-Differental Configuration
2.2uF
100nF
47K
xADCREF
50ohm
50ohm
xINCM
33ohm
VIN
IF2xA_P
47pF
27pF
IF2xA_N
DATA[9:0]
33ohm
xVCMO xREFP xREFM
100pF
100nF
100pF
100nF FROM INTERNAL CLK DISTRIBUTION
The two pins xREFM (Bottom of the reference ladder) and xREFP (Top of the reference ladder) are decoupling nodes for conversion dynamic adjustment; when the internal reference is used these pins must be connected as showed in figure 4. Pin xADCREF is connected with an external resistor (typical value 47 Kohm) to trim the internal bias current, xINCM is the output common mode used to centre the external input network and xVCMO is the internal common mode that can be externally filtered by a capacitor.
11/117
STA400A
IF AGC To maintain constant the signal levels at the A/D converters input, two 1-bit Pulse Density Modulated (PDM) signals (SAGC for satellite and TAGC for terrestrial branch) are generated to drive an external IF AGC. The difference between the user programmable reference level and the power of the input samples is integrated by the programmable gain loop filter and then sent to a 1-bit modulator to generate the output control signal. The sense of this signal is programmable to adapt it to a positive or negative slope of the variable gain amplifier. The SAGC and TAGC outputs can be filtered by an external low pass filter to close the AGC loop (see fig.3); in this way the mean power of the ADCs input signal is forced to the reference. The AGC loop gain is given by: AGC = 2xAGCBETA. The parameter xAGCBETA can take values from 0 to 6. When xAGCBETA="111" the loop gain is zero. The AGC loop may be opened by programming "111" in the x AGCBETA parameter and writing "00000000" in the xAGCINTG register. In this condition the control signal is a 50% duty-cycle square wave with a frequency of MCLK/2 (23.92MHz/2=11.96MHz). The 8 MSBs of the integrator register may be read at any time in the xAGCINTG register. This value is the level of the AGC outputs after low pass filtering; it gives an image of the input signal power at the terrestrial and satellite branch respectively. The reference level can be set by the xAGCREF register, the loop gain and the sense of the control pins (TAGC and SAGC) are set by the AGC_CTRL1 register described in section 2.6. CONTROL Registers The IF_CTRL, CONTROL and STATUS1 are the control registers of the IF Sampling interface (see section 2.6). To have a more stable reading of the xAGCINTG register a moving average filter over 2048 samples is used. This filter can be enabled or disabled by the bit7 of the IF_CTRL register. The data bit from the external ADCs (if used) may have a two's complement or offset binary format. Bit1 of the IF_CTRL register sets the binary format for the digital IF inputs. The CONTROL register configures the master clock outputs (MCLKO and MCLKON) and the external memory mode access of the bi-directional bus (MDQ[7:0]). When the master clock output buffers are disabled the output levels are fixed to ground resulting in no activity on these pins; this aproach minimizes the interferences when these signals are not used. The bi-directional buffers of the STA400A and the input/output mask of the external SDRAM are controlled by the MDQM pin. The STA400A has a low level active bi-directional buffers (high level on the enable drives the buffers to Hi-Z). The input/output mask operation of the external SDRAM may be selected active HIGH or active LOW (see figure 5) setting the MDQM_CTRL parameter of the CONTROL register (bit5). Figure 5. Input/Output Mask Configuration
STA400A STA400
MDQ BIDIR BUFFER
SDRAM
DATA INPUT REGISTER
MDQ[7:0]
DATA OUTPUT REGISTER
MDQM OUTPUT BUFFER
0 1
MDQM
I/O MASK
MDQM_CTRL
12/117
STA400A
The carrier lock indication of the satellite and the terrestrial demodulators, and the status of the FEC TerrestrialSatellite combining may be read in the STATUS1 register described in section 2.6. 1.2 SATELLITE DEMODULATION The satellite signals are demodulated by two QPSK demodulators, one tuned to the East satellite and the other to the West satellite. The two QPSK demodulators are identical and include quadrature demodulation, carrier and timing recovery and tracking, frequency sweep generation, Nyquist Root Raised Cosine filtering with 15% roll-off, digital AGC, lock indication and carrier to noise estimation. Figure 6. Satellite Demodulator Block Diagram
I/Q MIXER - CARRIER NCO
AGC2 LOOP RRC INTERPOLATOR FILTER
IOUT
FROM IF SAMPLING
QCHS
RRC INTERPOLATOR FILTER
QOUT
AGC2BETA LIMITER
uP
uP
REG
I +Q
2 2
SIN/COS ROM
TIMING NCO
+
uP
AGC2REF
AGC2INTG
uP
SYMBOL CLOCK
REG
REG
TIMING LOOP FILTER
uP
REG
ALFATIM
+ +
LIMITER L-SHIFT
uP
CARFREQ REG
TIMING ERROR DETECTOR
C/N ESTIM
REG
uP
REG
uP
IFFREQ
uP
uP
SYMFREQ
TIMINTG CTRL
TIMINTG
uP
BETA_E
BETA_M
uP
uP
BETATIM
CARRIER LOOP FILTER
uP REG
ALPHACAR
TO TDM DECODING
LOCK_Sx pin 37/38
+ +
LIMITER L-SHIFT
NEW IFFREQ
CLEAR
PHASE ERROR DETECTOR
LOCK DETECT
CARRIER NULL OFFSET
DISABLE
FREQ SWEEP
uP
uP
REG
uP
CARINTG
uP
BETA_E
BETA_M
uP
BETACAR
The architecture of one QPSK demodulator is depicted in fig.6. The input signal, sampled at 23.92 MHz and quantized on 8 bits, is multiplied by the sine an cosine functions to obtain the In-phase and the Quadrature component of the transmitted symbols. The demodulated QPSK signal is affected by the phase and frequency error due to oscillator inaccuracies and frequency shift. These errors are removed by the carrier tracking loop by means of a Phase/Frequency Detector, a loop filter and an NCO. The symbol tracking loop removes the phase and frequency uncertainties in the symbols: instead of controlling the sampling clock phase, the timing error detector adjusts, using the timing NCO, the impulse response phase of the two interpolator filters. To enhance the performace of the demodulator in presence of a signal dropout, the carrier and symbol loops are controlled by the CarrierNullOffset and the TimingCtrl blocks. The first operates on the Carrier NCO and Carrier Loop Filter, the latter on the Timing Loop Filter. An internal ramp generator (FreqSweep) is used to help the carrier loop during the acquisition phase. The frequency sweep is stopped by the lock detector output whenever a lock condition is reached. The phase ambiguity introduced by the demodulation process and the frame synchronization are resolved in the TDM Decoding block using the Master Frame Preamble (MFP) and the Fast Syncronization Preamble (FSP).
13/117
STA400A
The second IF composite satellite signal, available at the IF2SA inputs, has the spectrum schematically shown in Fig.7. The base band convertion of the selected satellite signal is done by programming the carrier NCO (acting as local oscillator) of the demodulator. For demodulating the S1-Early Satellite signal the carrier NCO frequency of the Early QPSK Demodulator must be equal to 6.095 + 0.92 = 7.015 MHz; for the S2-Late Satellite signal the frequency at the carrier NCO output of the Late QPSK Demodulator must be 6.095 - 0.92 = 5.175 MHz. The register map of the QPSK demodulators is described in section 2.2. I/Q Mixer - Carrier NCO The final downconvertion to baseband of the 2nd IF satellite signal is performed by a mixer and a local oscillator implemented with an NCO and a Sin/Cos Look-up table (see figure 6). The signal coming from the IF Sampling block is multiplied by the output of the quadrature NCO to produce the I and Q components of the baseband signal. The NCO output are the sine and cosine functions obtained with a look-up table driven by a 28 bit phase accumulator. The IFFREQ register sets the frequency of the carrier NCO as given in the following: Fc = FMCLK x (IFFREQ)/228 , where FMCLK is the clock frequency and IFFREQ is the 28 bit integer value loaded in the register. For example, to program the S1-NCO to 7.015 MHz the IFFREQ register must be loaded with 04B13B14 (Hex) equivalent to 78723860 (Dec). The sine/cosine output frequency of the NCO is given by Fo = (Fc + Fsw + PHerr) x FMCLK/228 where Fc is the nominal center frequency, Fsw is the output of the frequency sweep generator, PHerr is the filtered phase error from the carrier loop filter output and F MCLK/228 is the NCO frequency resolution. The CARFREQ read only register gives the value of the actual carrier frequency after the lock condition has been reached. This register can be used to measure the frequency offset between the local oscillator and the incoming carrier. The QCHS block of the I/Q mixer changes the sign of the Quadrature component in order to adapt the demodulation process to a different rotation sense of the QPSK mapping. Figure 7. Second IF Satellite Signal Spectrum
3.726 1.886 1.886
S2A (S2B)
1.64 1.64
S1A (S1B)
Fo - 0.92 0.92
Fo 0.92 1.84
Fo + 0.92
F (MHz)
Fo = 6.095 MHz RRC Symbol freq = 1.64 MHz roll-off factor = 15 % S2 = Late Satellite S1 = Early satellite A = Ensemble A; B = Ensemble B
14/117
STA400A
High-Side/Low-Side Injenction Control In a superetherodyne tuner (using two downconversions to produce the second IF signal at the Channel Decoder satellite input) is possible that one LO may use an High-Side injection of the carrier and the other LO may use a Low-Side injection. In this case a data polarity convertion is required in the Channed Decoder. To accomodate this function two methods are available: the first method requires a polarity change in the QCHS and CARCHS bits of the QPSK_CTRL register, with the second method the IFFREQ register of the carrier NCO must be programmed with the image frequency using the following formula: FMCLK - Fc = FMCLK x (IFFREQ)/228 For example, to set the image frequency of the 7.015 MHz the value FB4EC4EC (Hex) must be loaded in the IFFREQ register. Matched/Interpolator Filters The STA400A provides two matched/interpolator filters. These filters perform the Nyquist filter function (matched with the one in the transmission side) with a Root Raised Cosine (RRC) shape and a roll-off factor of 15% and the interpolation function to evaluate the optimum sampling instant of the output symbol. The filters, based on a poliphase structure (12 taps with 32 coefficients/ tap), receive at their inputs the separate I and Q streams at FMCLK/FSYM samples/symbols and produce the separate I and Q output streams at one sample per symbol. The frequency responce of one filter is given in fig.8 and fig.9. AGC2 The AGC2 loop is designed to maintain a fixed signal level at the input of the Soft Decision Slicer. As shown in fig.6, the AGC2 loop consists of an error detector, a loop filter and a gain multiplier. The modulus of the complex symbols is compared to a programmable reference level (AGC2REF register) and then scaled by the AGC2BETA coefficient and integrated. The filtered error drives two multipliers at the output of the Matched filters to maintain constant the level at the demodulator output. The AGC2 loop gain is given by: AGC2 = 2AGC2BETA. The parameter AGC2BETA can take values from 0 to 6. When AGC2BETA="111" the loop gain is null and the AGC2 amplifier gain keeps the last value. The AGC loop may be opened by programming "111" in the AGC2BETA parameter and writing "0x00" in the AGC2INTG register. The reference level set in the AGC2REF register impacts on the carrier and timing loop equations and on the operation of the Soft Decision Slicer. Figure 8. RRC Filter Frequency Responce
0
3 815 kHz
10
20 Magnitude (dB)
30
40
50
60
0
200
400
600
800 1000 1200 Frequency (kHz)
1400
1600
1800
2000
15/117
STA400A
Figure 9. RRC Filter Passband Ripple
0.5
0 Magnitude (dB) 0.5 1 0
100
200
300
400 500 600 Frequency (kHz)
700
800
900
1000
Carrier Phase/Frequency Error Detector The carrier Phase/Frequency Error Detector (PFD) measures the error between the sampled symbols and the quadrant bisector. The error is calculated by the following formula : PHerr = I x Sgn(Q) - Q x Sgn(I), where Sgn(.) is the sign function. This value is computed at symbol rate if the actual I and Q components are greater than a programmed threshold otherwise the previous value is maintained. In this way the detector outputs a DC value proportional to the frequency offset between the incoming signal and the local oscillator. In the steady state, when the carrier loop is locked (and, therefore, the phase error is small), the circuit behaves like a pure phase detector while during the acquisition phase it behaves like a PFD. The threshold value may be programmed by the PFDTHR register. The signal level after the AGC2 loop must be taken into account when setting the threshold. The default preset for this parameter is about the 20% of the AGC2 reference value (see AGC2REF register). The carrier Phase and Frequency Detector Gain (Kd) characteristic as a function of the Carrier to Noise ratio is given in fig.10. Kd = 1.24 is the value for a noise free input signal and may be reduce up to 50% of its maximum value in a low C/N condition. Figure 10. Carrier Phase/Frequency Detector Gain
PFD Gain 1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0
2
4
6
8
10 C/N (dB)
12
14
16
18
20
16/117
STA400A
Carrier Loop Filter The carrier loop filter is a first order IIR filter with two programmable parameters, one for the proportional and the other for the integral correction, as shown in fig. 6. The output of the integrator, that produces a frequency control term, is summed with the weighted phase error in the proportional path and then sent to the Carrier NCO to close the carrier tracking loop. The proportional gain alpha and the integral gain beta of the filter are configured by the registers ALFACAR and BETACAR respectively. The integral gain is set by a mantissa and exponent as given by: beta = beta_m x 2(beta_e) where beta_m, the mantissa, is a 5-bit integer value set in the five LSBs of the BETACAR register (beta_m=BETACAR[4:0]) and beta_e, the exponent, is a 3-bit integer set in the three MSBs of the BETACAR register (beta_e=BETACAR[7:5]). The proportional gain is an integer value set in the ALFACAR register with a range from 0 to 255 (alpha=ALFACAR[7:0]). The CARINTG register collects the 8 MSBs of the filter integrator and may be read or written at any time by the system controller. When the register is written, the integrator LSBs are reset. The filter integrator is saturated to 21-bit by the LIMITER block resulting in a maximum peak-to-peak frequency range of 373KHz (with FMCLK = 23.92MHz). Carrier Loop Equations The carrier loop is fully digital and comprises two blocks working at symbol rate: the Phase/Frequency Error Detector and the Loop Filter, and two blocks working at clock rate: the Carrier NCO and the I/Q Mixer (see fig.6). The loop is parametrised by the coefficients alpha and beta given in the registers ALFACAR and BETACAR respectively. The carrier loop is a second order loop whose natural frequency fn and damping factor may be calculated applying the following formulas: mk d f n = 26.96 mK d b eta [Hz] = 0.01322 alpha -----------b eta where alpha is set in the ALFACAR register and beta in the BETACAR register, Kd is the PFD gain as shown in fig.10 and m is the reference level of the AGC2 loop (see AGC2REF register). For example, to set the loop natural frequency to 1.3KHz with the default value for m=AGC2REF (90dec, 5Ahex) and Kd = 1.24 (noise free value), the above equation solved for beta gives: fn be ta = ------------------------------ = 20.83 726.84mK d alpha can be chosen to have a damping factor equal to 0.7: - b eta alpha = -------------------- ------------ = 22.87 0.01322 mK d The register ALFACAR can be programmed with 23 (Dec) and the register BETACAR can be programmed with the parameter BETA_E=0 and BETA_M=21 (Dec). Frequency Sweep When the frequency offset is greater than the pull-in range of the carrier loop or in presence of low signal to noise ratio the tracking performance of the loop itself may became rather slow. To help the loop in tracking this frequency offset an internal frequency sweep generator can be enabled via IIC-bus. The output of this block is summed to the frequency register of the I/Q Mixer and operates only during the carrier acquisition. The sweep is stopped by the lock detector when the carrier lock condition is reached (see fig.6). The sweep rate is given by the following formula:
2
17/117
STA400A
SWSTE P F 2 dF - M CL K ------ = --------------------------------------- ----------------- [Hz/s] STEPPER + 1 2 28 dt
2
The frequency sweep operation is controlled by the RAMPCTRL register. The parameter SWSTEP can take 0 or 1 values and STEPPER can be programmed in the range 0 to 15 decimal. The maximum peak-to-peak frequency sweep range is 373.75KHz. The sweep direction can be positive or negative depending on the bit-6 of the RAMPCTRL register. The sweep always starts from the zero value; when the upper limit is reached, the sweep continues with the lower one if the positive slope is set and viceversa when the negative slope is selected. This frequency sweep block can be switched on or off setting the SWON parameter to 1 or 0 respectively. When SWON=0 the output value of the ramp is null. Carrier Lock Detector The lock detector consists of an up/down counter with saturation driven by a dedicated logic. This circuit monitors the QPSK symbol constellation to decid the counter direction. If the actual symbol is inside the region delimited by the equations 2 x I - Q 0 and 2 x Q - I 0 (the lock region) the counter counts up otherwise counts down. If the demodulator is locked, the number of symbols inside the lock region is greater than the number of symbols outside and the the counter is driven in the up direction toward the saturation limit. When the counter output is above a programmable threshold, the lock indicator is set to '0' declaring the lock condition of the carrier tracking loop. This threshold is set by the LOCKTHR register. The lock detector controls the frequency sweep generator, the Carrier Null Offset and TIMING_CTRL circuits. Timing NCO The timing NCO is the timing generator for the two interpolator filters (see fig.6). To correct the symbol error, the impulse response of the interpolator is shifted by an amount of time depending on the phase accumulated in the timing NCO. It consists of a 25-bit modulo-1 accumulator driven by the output of the timing loop filter. The 5LSBs of the accumulator give the fractional part of the sampling clock used by the interpolator filter to select the coefficients of the impulse response that cancel the timing error. The integer part, given by the carry bit of the accumulator, is used to decimate to symbol rate the output of the interpolator/matched filter. The nominal symbol frequency is set by the SYMFREQ register. The timing loop adjusts this nominal value to find the optimal symbol phase (maximum open eye condition) and to track the residual symbol frequency offset. The output of the timing generator is given by Fo = (Fsym + TEDerr) x FMCLK/225 where Fsym = 1.64MHz is the nominal symbol frequency, TEDerr is the filtered timing error detector output and FMCLK/ 225 is the NCO resolution. For example, to set the symbol frequency to 1.64MHz the SYMFREQ register must be loaded with the value 00231A8B (Hex) equivalent to 2300555 (Dec). Timing Error Detector The timing error detector (TED) is based on a one sample per symbol algorithm to compute the timing error between the demodulated symbol at the matched filter output and the optimum sampling instant. The output of the detector is given by the following equation: TEDerr = In x Sgn(In-1) - In-1 x Sgn(In) + Qn x Sgn(Qn-1) - Qn-1 x Sgn(Qn) This signal is filtered by the timing loop filter and then sent to the timing NCO to close the tracking loop. The TED Gain (Kd) characteristic as a function of the Carrier to Noise ratio is given in fig.11. Kd = 0.56 is the value for a noise free input signal and may be reduce up to 40% of its maximum value in a low C/N condition.
18/117
STA400A
Figure 11. Timing Error Detector Gain
TED Gain
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0
2
4
6
8
10 C/N (dB)
12
14
16
18
20
Timing Loop Filter The timing loop filter is a first order IIR filter with two programmable parameters, one for the proportional and the other for the integral correction, as shown in fig.6. The output of the integrator, that produces a frequency control term, is summed with the weighted timing error in the proportional path and then sent to the timing NCO to close the timing tracking loop. The proportional gain alpha and the integral gain beta of the filter are programmable by the registers ALFATIM and BETATIM respectively. The integral gain is set by a mantissa and exponent as given by: beta = beta_m x 2(beta_e) where beta_m, the mantissa, is a 5-bit integer value set in the five LSBs of the BETATIM register (beta_m=BETATIM[4:0]) and beta_e, the exponent, is a 3-bit integer set in the three MSBs of the BETATIM register (beta_e=BETATIM[7:5]). The proportional gain is an integer value set in the ALFATIM register with a range from 0 to 255 (alpha=ALFATIM[7:0]). The TIMINTG register collects the 8 MSBs of the filter integrator and may be read or written at any time by the system controller. When the register is written the integrator LSBs are reset. A limiter is provided on the filter integrator to limit the frequency sweep of the timing NCO. After a drop-out or during the unlock condition, the frequency uncertainty of the timing NCO (that produces a symbol slip on the demodulated data) can be controlled setting the maximum number of bit in the timing integrator. This value is set in the LIMITER block by the TIMLPF_LENGTH parameter (see TIMLPF_CTRL register). The limiter peakto-peak range can take 8 values from 8-bits to 20-bits corresponding to a frequency shift from 182Hz to 7.5KHz respectively. Timing Integrator Control This block operates on the timing loop integrator. During a very long drop-out or when no signal is applied to the demodulator input, the timing loop integrator may drift up to the saturation value. As the signal is applied again or after the drop-out event, it is possible that the integrator remains in saturation for a long period causing a very slow symbol re-acquisition time. The TimintgCtrl block recognizes this event and sends a reset to the integrator register to speed-up the re-acquisition phase. The flow diagram of the TimintgCtrl block Finite State Machine (FSM) is depicted in fig.12. The FSM parameters and the block enable/disable command are set in the TIMLPF_CTRL register
19/117
STA400A
Figure 12. TimingCtrl FSM Flow Diagram
Reset Time Counter Clear Releasing in the Time Loop Filter Integrator
demodulator locked (LOCK=0) or TIMING_CLR_EN=0
demodulator locked (LOCK=0) demodulator unlocked (LOCK=1)
Time Counter Active
demodulator unlocked for a time less than a fixed value (TIMINTG_CLR_WIN)
demodulator unlocked for a time equal to a fixed value (TIMINTG_CLR_WIN)
Time Counter Reset Time Loop Filter Integrator Cleared
demodulator unlocked
Timing Loop Equations The timing recovery is fully digital and comprises two blocks working at symbol rate: the Timing Error Detector and the Loop Filter and two blocks working at clock rate: the Timing NCO and the Nyquist/Interpolator filters (see fig.6). The loop is parametrised by the coefficients alpha and beta given in the registers ALFATIM and BETATIM respectively. The timing loop is a second order loop whose natural frequency fn and damping factor may be calculated by the following formulas: f n = 4.76 mK d beta [Hz] = 0.075 alpha mK d -----------beta
where alpha is set in the ALFATIM register and beta in the BETATIM register, Kd is the TED gain as shown in fig.11 and m is the reference level of the AGC2 loop (see AGC2REF register). For example, to set the loop natural frequency to 126Hz with the default value for m=AGC2REF (90dec, 5Ahex) and Kd = 0.56 (noise free value), the above equation solved for beta gives: fn be ta = --------------------------------- = 13.90 22.6576mK d alpha can be chosen to have a damping factor equal to 0.7: - be ta alpha = -------------- ------------ = 4.9 0.075 mK d The register ALFACAR can be programmed with 5 (Dec) and the register BETACAR can be programmed with the parameter BETA_E=0 and BETA_M=14 (Dec).
2
20/117
STA400A
C/N Estimator This block gives the signal to noise ratio at the Nyquist filter output. It computes the statistic (mean and variance) of a single component of the demodulated complex signal and writes the estimated C/N value in dB in the CN register. This register has a fixed point format. The integer part of the number is stored in the six MSBs (bit7-2) and the fractional part in the two LSBs (bit1-0). The C/N estimation is correct only when the QPSK demodulator is locked. Carrier Null Offset This block is used to enhance the acquisition performance of the carrier loop. It may be enabled/disabled setting bit-6 of the QPSK_CTRL register. The block consists of a FSM that is activated when the carrier loop has reached the lock condition (low level on at the Lock Detector output). The FSM checks if the lock detector output is low for a programmable period (see NULOFS_WIN register) and then it writes the locked carrier frequency value (read from the CARFREQ register) into the Carrier NCO. It resets also the carrier loop filter integrator and disables the frequency sweep (see fig.6). In this way the demodulator works with a null carrier offset resulting in a faster re-acquisition time of the carrier in case of a signal drop-out. The NULOFS_DELTAF register gives the possibility to subtract a programmed frequency from the locked carrier before writing the new value in the carrier NCO. The flow diagram of the CarrierNullOffset FSM is showed in fig.13
Flag Register A flag register is provided in the QPSK demodulator. This is a read only register containing specific status bits of the demodulator. It gives information on the lock staus and on the operation of the CarrierNullOffset and TimintgCtrl blocks. Figure 13. CarrierNullOffset FSM Flow Diagram
system reset or block disable system reset or block disable (NULOFS_EN=0) or demodulator unlocked (LOCK=1)
Reading lock
demodulator unlocked
demodulator locked (LOCK=0)
Reading lock Time counter active
demodulator locked for a time less than a fixed value (NULOFS_WIN)
demodulator locked for a time equal to the fixed value (NULOFS_WIN)
Frequency.Sweep Disabled Carrier Loop Filte Integrator Cleared Writing New IF Frequency in the Carrier NCO: NEW_IF_FREQ= CARFREQ-NULOFS_DELTAF
Clear release in the carrier loop filter integrator
no system reset and block enable
21/117
STA400A
1.3 TERRESTRIAL DEMODULATION (To Be Completed) The MultiCarrier Modulated (MCM) terrestrial signal is sampled at 23.92 MHz and converted to 10-bit. The terrestrial demodulator processes these samples at four time the MCM symbol rate (4*2.99 MHz = 11.96 MHz) and includes the final down-convertion and I/Q symbol generation, low-pass filtering and down-sampling to MCM symbol rate (2.99 MHz). The MCM demodulation is performed by an FFT over 768 samples. The MultiCarrier Demodulator also includes frequency and symbol synchronization, Amplitude-Modulated Synchronisation Symbol (AMSS) detection for frame synchronisation, guard interval removal, differential decoding, demapping and metric generation. All the MCM demodulator functionality are programmable by the microcontroller; the Register Map is listed in sections 2.3 and 2.9.
1.4 TDM DECODING (To Be Completed) There are two different TDM structures within the DARS system, the satellite TDM and the Terrestrial TDM, carrying the same Payload Channels (PC), which are included in a 432 msec framed packet consisting of one or more Prime Rate Channel (PRC) with Reed-Solomon protection (outer encoding). The combined satellite transmission includes a punctured rate 3/8 convolutional inner encoder (from a mother code of rate 1/3 and "1 out of 9" punctured scheme) and a convolutional interleaved with 4.698 sec. delay. Each satellite transports one half of the punctured and interleaved PC resulting in an effective inner encoder rate of 3/4. Up to 256 PRCs are multiplexed together into a Time Division Multiplex (TDM) structure. The Time Slot Control Channel (TSCC), containing information of the TDM structure, is added at the begin of the fully FEC protected PCs. After the insertion of 1 Master Frame Preamble (MFP), 205 Fast Synchronization Preamble (FSP) and the padding field (PAD) the complete satellite Master Frame (MF) contains 1416960 bits over 432 msec, resulting in a satellite TDM bit-rate of 3.28 Mbits/sec. The terrestrial bit-stream is a repeater signal from the satellite transmission. The inner encoder has a convolutional code rate of 3/5 (from a mother code of rate 1/3 and "4 out of 9" punctured scheme) and does not include convolutional interleaving. The terrestrial MF structure contains only 3 fields: MFP, Data Field (TSCC/PCs) and PAD resulting in a 1755360 bits over 432 msec. for a bit-rate of 4.063333 Mbits/sec. The TDM decoder receives the demodulated symbol streams from the two satellite and the terrestrial demodulators. The TDM processing includes Sat-Sat combining, frame synchronization, external memory management and PRC demultiplexing. The frame synchronization is based on the MFP detection. The MFP and FSP are also used for the phase ambiguity resolution of the satellite demodulated data and for fast synchronization after a short dropout and cycleslip. The PRC demultiplexer processes the TSCW (Time Slot Control Word) from the TSCC field to extract all the information needed for the allocation of the PRCs to the selected PCs. Up to 50 PRCs (48 PRCs plus 2 TSCC) can be demultiplexed resulting in a maximum PC bit stream rate of 414.8 Kbit/s (384Kbit/s of useful data). The programmable register for the TDM Decoding are explained in sections 2.4 and 2.8.
1.5 FEC (To Be Completed) The PRC and the TSCC data from the external memory are decoded by the FEC (Viterbi Decoder, Reed-Solomon Decoder and Block Deinterleaver) and sent to the PC-BitStream Interface. The PRC-based packet structure of the Service Layer and the external memory allow the use of one Viterbi Decoder and one RS Decoder for both the combined-satellite and terrestrial TDM frame. The first operation of the FEC block is a data pre-processing for buffering, reordering and demultiplexing of the data streams coming from the external memory and containing both the satellite and terrestrial TDM. In this phase the depuncturing process is also performed.
22/117
STA400A
The depunctured R=1/3 coded data stream (equal for combined-satellite and terrestrial) is decoded by the Viterbi Decoder using 6 bit of quantization (1 hard bit and 5 soft bits). The outer decoding process, the block deinterleaving and the satellite/terrestrial selective combining is performed by the RS decoder circuit. Additional feature of the FEC block is the Bit Error Rate estimation (computed separately for terrestrial and combined satellite) based on the re-encoding of the Viterbi decoded bit-stream.
1.6 PC BITSTREAM INTERFACES After demodulation, TDM processing and FEC decoding the CDEC delivers the TSCC and the selected PRCs to external devices for further processing. To implement this function, STA400A contains two identical Payload Channel (PC) Bitstream Interfaces (see fig.1). Each PC Interface performs the parallel to serial conversion and the reformatting of the data packets coming from the PRC Demux Control block and provides serial data, clock and synchronization signals to the PC output ports. The Payload Channel output protocol (showed in fig.14) is configurable, independently for the two interfaces, via the PC interface registers described in section 2.7. Figure 14. PC Bitstream Output Protocol
432ms frame period
PCSD
TSCC1
TSCC2
PRC_A1
PRC_An
PRC_B1 CLOCK
PRC_Bn
PRC_Z1
PRC_Zn
PCDC PCFS
H1
H2
PCSD
PCDC PCFS
The 432ms TDM frame is divided in 50 time intervals with the first two containing the TSCC data. Each time interval contains a burst of 448 bytes (2 header bytes H1 and H2, and 446 bytes of PRC data) transmitted from the PRC Demux to the PC Interface. The PC output ports are enabled depending on the settings of the register Pcid Data Wr (addr: 0x0651-0x0652). Each output port provides 5 signals: s PCSD, Payload Channel Serial Data
s s s
PCDC, Payload Channel Data Clock PCFS, Payload Channel PRC Frame Sync PCBS, Payload Channel Byte Sync
23/117
STA400A
s
PCTS_EF, Payload Channel TSCC Sync / Reed-Solomon Error Flag
The PCDC frequency can be set from 11.96 MHz to 373.75 kHz via the 5 MSBs of the PCDC_CONF register (PCDC_CONF[6:2]); the clock polarity and the clock configuration (always running or fixed to '1' when the interface is not transmitting data) can be configured via the PCDC_CONF[1] and the PCDC_CONF[0] bits respectively. The PCSD data format can be set via the PCSD_CONF register; PCSD_CONF[0] and PCSD_CONF[1] define if data are transmitted MSB or LSB first and if a parity bit is appended or not to each data byte respectively The calculated parity can be even or odd depending on the content of PCSD_CONF[2] bit. PCFS is the PRC packet synchronization; the default setting is one pulse at the beginning of each burst of 448 bytes. PCBS is a byte synchronization signal with one pulse at the beginning of each decoded data byte (default configuration). PCTS_EF can be configured as the TSCC synchronization signal (default configuration) or as the Reed-Solomon error flag signal. The TSCC synchronization is a pulsed signal having period T=432ms (one pulse every TDM frame). The width of the synchronization pulses is equal to 1 PCDC cycle. The parameters of these last three signals can be configured via the PCSYNC_CONF register.
1.7 MICROPOCESSOR INTERFACE Data communication between the microcontroller and the device takes place through the 2 wires (SDA and SCL) IIC-bus interface. The STA400A is always a slave device. The STA400A Register Map is organized in 8 main pages with a base address given in Table 2.2. After the device address, to read or write a register, the microcontroller must send first the base-address to select one of the 8 pages and a relative-address to select the register inside the page. The STA400A has byte or multibytes registers access with different classes (see table 2.1); the complete list of the registers is given in the Register Map section. Interrupt Line The interrupt line of the STA400A (pin 53 - INTR) OR-Wires 8 different interrupt requests from the CDEC that can be individually masked by the registers IRQ1_MASK (address 0x0417). The interrupt vector is represented by the IRQ1_STATUS register (address 0x0419) described in section 2.6. After an interrupt request, the INTR pin remains at high level, except for the MFP_CLK interrupt bit5, that is an impulse periodic signal. The IRQ1_STATUS interrupt vector may be automatically reset after the read operation or may be reset by the microcontroller (writing 0x00) depending on the bit0 of the CONTROL register (see section 2.6) IIC-BUS Specification The I2C-bus protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the others as the slave. The master will always initiate the transfer and will provide the serial clock for synchronisation. Data Transition or Change Data changes on the SDA line must only occur when the SCL clock is low. SDA transitions while the clock is high are used to identify START or STOP condition. Start Condition START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is
24/117
STA400A
stable in the high state. A START condition must precede any command for data transfer. Stop Condition STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communications between STA400A and the bus master. Acknowledge Bit An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse the receiver pulls the SDA bus low to acknowledge the receipt of 8 bits of data. Some registers do not give acknowledge when the data is not available. Data Input During the data input the STA400A samples the SDA signal on the rising edge of the clock SCL. For correct device operation the SDA signal has to be stable during the rising edge of the clock and the data can change only when the SCL line is low. Device Addressing To start communication between the master and the STA400A, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode. The 7 most significant bits are the device address identifier, corresponding to the I2C bus definition. For the STA400A these are fixed as 1101010. The 8th bit (LSB) is the read or write operation bit (RW; set to 1 in read mode and to 0 in write mode). After a START condition the STA400A identifies on the bus the device address and, if matched, it will acknowledges the identification on SDA bus during the 9th bit time. The following 2 bytes after the device identification byte are the internal space address. Write Operation (see fig. 15) Following a START condition the master sends a device select code with the RW bit set to 0. The STA400A gives the acknowledge and waits for the 2 bytes of internal address. The least significant 15 bits of the 2 bytes address provides access to any of the internal registers. The most significant bit means incremental mode (1 = auto incremental enabled, 0 = auto incremental disabled). The STA400A has an internal byte address counter. Each time a byte is written or read, this counter, according to the autoincremental bit setting, is incremented or not. After the reception of each of the internal bytes address the STA400A again responds with an acknowledge. Byte Write In the byte write mode the master sends one data byte and this is acknowledged by STA400A. The master then terminates the transfer by generating a STOP condition. The Multibyte Write needs the auto incremental mode bit set to '1'. Multibyte Write The multibyte write mode can start from any internal address. The master sends the data and each one is acknowledged by the STA400A. The transfer is terminated by the master generating a STOP condition.
25/117
STA400A
Read Operation (see Fig. 16) Current Byte Address Read For the current byte address read mode, following a START condition the master sends the device address with the RW bit set to 1. The STA400A acknowledges this and outputs the byte addressed by the internal byte address counter. The counter is then incremented or not depending on the auto incremental bit. The master does not acknowledge the received byte, but terminates the transfer with a STOP condition. Random Byte Address Read A dummy write is performed to load the byte address into the internal address counter. This is followed by another START condition from the master and the device address repeated with the RW bit set to 1. The STA400A acknowledges this and outputs the byte addressed by the internal byte address counter already loaded The master does not acknowledge the received byte, but terminates the transfer with a STOP condition. Sequential Address Read This mode can be initiated with either a current address read or a random address read. However in this case the master does acknowledge the data byte output and the STA400A continues to output the next byte in sequence, providing that the auto incremental mode bit be set. To terminate the stream of bytes the master does not acknowledge the last received byte, but terminates the transfer with a STOP condition. The output data stream is from consecutive byte addresses, with the internal byte address counter automatically incremented after each byte output. Figure 15. Write Mode Sequence
ACK BYTE WRITE START DEV BYTE ACK BYTE ACK DATA IN ACK
RW
STOP
ACK MULTIBYT WRITE START DEV BYTE
ACK BYTE
ACK DATA IN
ACK DATA IN
ACK
RW
D97AU669
STOP
Figure 16. Read Mode Sequence
ACK CURRENT ADDRESS READ START NO ACK
DEV
DATA
RW ACK ACK BYTE
STOP ACK BYTE DEV ACK DATA NO ACK
RANDOM ADDRESS READ START
DEV
RW RW= ACK HIGH DEV DATA ACK
START
RW ACK NO ACK DATA
STOP
SEQUENTIAL CURRENT READ START
DATA
STOP ACK ACK BYTE BYTE ACK DEV ACK DATA ACK DATA ACK DATA NO ACK
SEQUENTIAL RANDOM READ START
DEV
RW
START
RW
D97AU670
STOP
26/117
STA400A
2 REGISTER MAP
Table 1. Register Classes
Abbreviations Name of Register Class
wr r rt pr pri wrt int trt
write and read read read plus en-trigger preset when read preset when read plus trigger signal write and read plus trigger signal interrupt register pair transparent
pr:
Event counter. (increments if input =1 and will be reset after read access to preset value)
pri: Event counter like pr-register, plus trigger output signal if maximum is arrived. wrt: Write and read register plus trigger output signal when write access. rt: int: Read only register plus trigger output signal when read access. This register class always consists out of a status and mask register. The status register stores interrupt signals from CDEC. The mask registers determines if an interrupt signal should generate an irq_out signal or not. A transparent register does not exists physically in the register map. The register map pipelines the information to the CDEC register. The register operates as a normal write/read register in the register map.
trt:
Note:The pr and rt register classes must be read with the random address read mode only. Sequential read mode is not allowed. Table 2. Base Address List
Base Address (hex) Block
00 01 02 03 04 05 06 07
Satellite Demodulators (SatDem1 + SatDem2) Terrestrial Demodulator (Section 1) TDM (Section 1) FEC IF Sampling and Control Interface PC Bitstream Interface TDM (Section 2) Terrestrial Demodulator (Section 2)
27/117
STA400A
2.1 REGISTER MAP OVERVIEW Table 3. QPSK Demodulator #1 (S1-Early) Base Address: 00 - Address Range: 59 - 77
Relative Address (Hex) Register Name WL Type Reset Value (Hex) Comment
59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77
QPSK_DEMOD_EN QPSK_CTRL PFDTHR SYMFREQ0 SYMFREQ1 SYMFREQ2 SYMFREQ3 IFFREQ0 IFFREQ1 IFFREQ2 IFFREQ3 ALFACAR BETACAR ALFATIM BETATIM RAMPCTRL AGC2BETA AGC2REF AGC2INTG TIMINTG CARINTG CARFREQ0 CARFREQ1 CARFREQ2 CARFREQ3 CN FLAG NULOFS_WIN NULOFS_DELTAF TIMLPF_CTRL LOCKTHR
1 8 6 8 8 8 1 8 8 8 4 8 8 8 8 7 3 8 8 8 8 8 8 8 4 8 4 4 8 8 2
wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr r r r r r r wr wr wr wr
01 47 14 8B 1A 23 00 EC C4 4E FB 17 15 07 0E 20 03 5A 00 00 00 ------07 2B 90 02
QPSK Dem Enable Register QPSK Dem Control Register Phase/Freq. Detector Threshold Symbol Frequency (LSB)
Symbol Frequency (MSB) Intermediate Frequency (LSB)
Intermediate Frequency (MSB) Carrier Loop Filter Alpha Param. Carrier Loop Filter Beta Param. Timing Loop Filter Alpha Param. Timing Loop Filter Beta Param. Ramp Control Register AGC2 Gain AGC2 Reference 8MSB of AGC2 Loop Integrator 8MSB of Timing Loop Integrator 8MSB of Carrier Loop Integrator Locked Carrier Frequency (LSB)
Locked Carrier Frequency (MSB) C/N Esteem Demodulator Status Null Carrier Offset Window Null Carrier Offset Delta Frequency Timing Loop Low Pass Filter Control Lock Detector Threshold
28/117
STA400A
Table 4. QPSK Demodulator #2 (S1-Late) Base Address: 00 - Address Range: 7F - 9D
Relative Address (Hex) Register Name WL Type Reset Value (Hex) Comment
7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D
QPSK_DEMOD_EN QPSK_CTRL PFDTHR SYMFREQ0 SYMFREQ1 SYMFREQ2 SYMFREQ3 IFFREQ0 IFFREQ1 IFFREQ2 IFFREQ3 ALFACAR BETACAR ALFATIM BETATIM RAMPCTRL AGC2BETA AGC2REF AGC2INTG TIMINTG CARINTG CARFREQ0 CARFREQ1 CARFREQ2 CARFREQ3 CN FLAG NULOFS_WIN NULOFS_DELTAF TIMLPF_CTRL LOCKTHR
1 8 6 8 8 8 1 8 8 8 4 8 8 8 8 7 3 8 8 8 8 8 8 8 4 8 4 4 8 8 2
wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr r r r r r r wr wr wr wr
01 47 14 8B 1A 23 00 9E D8 89 FC 17 15 07 0E 20 03 5A 00 00 00 ------07 2B 90 02
QPSK Dem Enable Register QPSK Dem Control Register Phase/Freq. Detector Threshold Symbol Frequency (LSB)
Symbol Frequency (MSB) Intermediate Frequency (LSB)
Intermediate Frequency (MSB) Carrier Loop Filter Alpha Param. Carrier Loop Filter Beta Param. Timing Loop Filter Alpha Param. Timing Loop Filter Beta Param. Ramp Control Register AGC2 Gain AGC2 Reference 8MSB of AGC2 Loop Integrator 8MSB of Timing Loop Integrator 8MSB of Carrier Loop Integrator Locked Carrier Frequency (LSB)
Locked Carrier Frequency (MSB) C/N Esteem Demodulator Status Null Carrier Offset Window Null Carrier Offset Delta Frequency Timing Loop Low Pass Filter Control Lock Detector Threshold
29/117
STA400A
Table 5. Terrestrial Demodulator (Section 1) Base Address: 01 - Address Range: 00 - C1
Relative Address (Hex) Register Name WL Type Reset Value (Hex) Comment
00 01 02 04 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 15 16 17 19 1A 1B 1C 1D 1F 20 21 22 23
Enable_M Status1_M Status2_M DataOvf_M IQGMode_M Clk_devcomp_M AMSSThrL_M AMSSThrH_M AMSSFailed_M SyncSearch_M SyncLoss1_M SyncLoss2_M FrameLen_M ChannelLen_M CycleCnt1_M CycleCnt2_M CycleCntRef1_M CycleCntRef2_M AttFactor1_M AttFactor2_M HistLen_M CN1_M CN2_M CN3_M FfCtrl_M FfBeta_M BlkDetect_M InitDelay_M MaxFreq1_M MaxFreq2_M MinCf_M
8 8 2 8 3 1 7 7 3 4 8 3 8 8 8 4 8 4 8 5 4 8 8 8 6 8 1 2 8 5 8
wr r r pr wr wr wr wr wr wr wr wr wr wr r r wrt wrt wr wr wr r r r wr wr wr wr wr wr wr
FF 00 00 00 02 01 37 41 07 0A FF 03 B4 B4 --00 00 F0 1F 0F ---1E 04 00 00 46 00 90
enable signals for mcm submodules status information of mcm submodules
overflow event counter of mcm submodules iq generation mode selects mode of clk deviation compensation low threshold of AMSS detection high threshold of AMSS detection if not more than mrm_sync_min_amss_failed AMSS-not-detected events : pre-sync -> hunt Number of mcm-frames during pre sync state number of allowed AMSS failed events (sync -> hunt)
frame window length of AMSS detection channel window length of AMSS detection actual difference of mcm-frame cycle count to nominal value.
external setting of actual difference of mcm-frame cycle count to nominal value
attenuation factor for correlation results.
length of history register estimated noise and signal&noise power.
control of ff internal algorithm loop filter constant beta external setting of blockage condition to fc delay on use of ff output at startup maximum allowed difference of ff and cf to detect out-of-range condition of ff.
confidence value for cf estimation
30/117
STA400A
Table 5. Terrestrial Demodulator (Section 1) (continued)
Relative Address (Hex) Register Name WL Type Reset Value (Hex) Comment
24 25 26 27 28 2A 33 34 35 36 37 38 39 3B 3C 3D 3E 3F 40 41 42 43 44 45 47 49 4B 4D 4F 50
CfRef1_M CfRef2_M CfValue1_M CfValue2_M FfScale_M Ff_OOR_M EpocEn_M DemapCtrl_M EpocThr1_M EpocThr2_M NormShift_M LinScale_M ShiftOvfl_M LimitOvfl_M EpocCarriers1_M EpocCarriers2_M EpocRotRe_M EpocRotIm_M PSFrameCnt_M PS_NoAMSSCnt_M AMSSFailCnt1_M AMSSFailCnt2_M OivlAMSSFail1_M OivlAMSSFail2_M MaxCorrIw_M MaxCorrOw_M MinCorrIw_M MinCorrOw_M FrameToggle_M CorrMaxAkt_M
8 5 8 5 8 8 1 8 8 6 4 8 8 8 8 2 8 8 4 3 8 8 8 4 7 7 7 7 1 7
wrt wrt r r wr pr wr wr wr wr wr wr pr pr r r r r r r r r r r rt rt rt rt r r
00 00 --E0 00 01 E0 00 06 0B 80 00 00 -----------------
external setting of cf offset value.
actual cf offset value.
scale factor multiplied with ff value counter for ff_out_of_range events epoc enable control of demapping control of epoc algorithm
normalization shift for FFT data a linear scaling of the FFT output data overflow counter if norm shift 0x37 is too large overflow counter if input data for pp exeeds input range number of carriers used for EPOC correction in current MCM symbol
EPOC correction phasor (real part) EPOC correction phasor (imag part) counter of frames during presync state counter of frames without amss detection counter of sequent frames without amss detection.
number of failed amss dectection during an interval set by register 0x0195/96.
maximum correlation inside channel window maximum correlation outside channel window minimum correlation inside channel window minimum correlation outside channel window with each mcm frame register value changes between 0 and 1 stores the current weighted maximum correlation value inside channel window stores the current position inside frame window.
51
CorrMaxPos1_M
8
r
--
31/117
STA400A
Table 5. Terrestrial Demodulator (Section 1) (continued)
Relative Address (Hex) Register Name WL Type Reset Value (Hex) Comment
52 53 54 55 56 60 61 62 70 71 72 80 81 82 83 84 90 91 95 96 97 98 9A 9B 9C B0 B2 B4 C0 C1
CorrMaxPos2_M PosShift1_M PosShift2_M WinJump1_M WinJump2 NCOInc1_M NCOInc2_M NCOInc3_M FfEst1_M FfEst2_M FfEst3_M MctlEn_M MctlMask_M MctlInit_M TdmCntTh_M MctlState_M MeanAbs_M ClipRate_M OivlLenAMSSFail1_M OivlLenAMSSFail2_M WinJpLimit1_M WinJpLimit2_M JpLimitEvt_M WinJpNoLimit1_M WinJpNoLimit2_M IQGDataOvf_M NCODataOvf_M LPFDataOvf_M IrqMask_M IrqStatus_M
3 8 4 8 3 8 8 1 8 8 1 1 6 1 8 2 8 8 8 4 8 3 8 8 3 8 8 8 2 2
r r r r r r r r r r r wr wr wrt wr r r r wr wr wr wr pr wr wr pr pr pr int int
-----------00 1F 00 18 00 00 00 8B 0F 03 00 00 00 00 00 00 00 00 00 Overflow event counter of LPF inside IQGEN Overflow event counter of NCO Overflow event counter of LPF MCM interrupt mask MCM interrupt status counts jump limit events actual requested jump of window without limit function. sets maximal allowed jump of window. MCM Control MCM Control masks MCM Control initialization trigger Number of TDM frames in lock for transition to state NO_UPDATE MCM Control Status Mean of absolute value of MCM output symbols MCM output clip rate sets length of observation interval of reg 0x0144/45 (139 frames =~ 1 sec). actual fine frequency value. NCO increment. real jump of window. real shift operation after checking history.
32/117
STA400A
Table 6. TDM (Section 1) Base Address: 02 - Address Range: 00 - CB
Relative Address (Hex) Register Name WL Type Reset Value (Hex) Comment
00 04 05 06 07 08 09 0A 0B 0C 0D 12 13 14 15 16 17 18 19 1A 1B 1D 1E 20 21 22
TdmEnable_S TdmSync_S1 MfpLength_S1 MfpThr_S1 SyncLength_S1 PreSyncThr_S1 SyncThr_S1 FspThr_S1 MetricCtrl_S1 Scrambler1_S1 Scrambler2_S1 TdmSync_S2 MfpLength_S2 MfpThr_S2 SyncLength_S2 PreSyncThr_S2 SyncThr_S2 FspThr_S2 MetricCtrl_S2 Scrambler1_S2 Scrambler2_S2 MfpLock_S1 MfpLost_S1 MfpW_re_S1 MfpW_im_S1 FspW_re_S1
8 5 4 7 4 4 4 6 4 8 4 5 4 7 4 4 4 6 4 8 4 7 4 8 8 7
wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr r r r r r
FF 10 0F 44 03 02 0B 14 00 05 08 10 0F 44 03 02 0B 14 00 05 08 ------
satellite TDM decoding block enable satellite one TDM decoding synchronization data control satellite one TDM decoding extended MFP detection window length satellite one TDM decoding extended MFP detection threshold satellite one TDM decoding synchronization window length satellite one TDM decoding pre-synchronization lost threshold satellite one TDM decoding synchronization lost threshold satellite one TDM decoding FSP invalid threshold satellite one TDM decoding QPSK metric generation data control satellite one TDM decoding scrambler polynomial satellite one TDM decoding synchronization data control satellite two TDM decoding extended MFP detection window length satellite two TDM decoding extended MFP detection threshold satellite two TDM decoding synchronization window length satellite two TDM decoding pre-synchronization lost threshold satellite two TDM decoding synchronization lost threshold satellite two TDM decoding FSP invalid threshold satellite two TDM decoding QPSK metric generation data control satellite two TDM decoding scrambler polynomial satellite two TDM decoding status satellite one TDM decoding extended MFP counter satellite one TDM decoding extended MFP correlation weight, real part satellite one TDM decoding extended MFP correlation weight, imaginary part satellite one TDM decoding FSP correlation weight, real part
33/117
STA400A
Table 6. TDM (Section 1) (continued)
Relative Address (Hex) Register Name WL Type Reset Value (Hex) Comment
23 24 25 26 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 39 3A 3B 3C 3F 40 41 50
FspW_im_S1 FspPhase_S1 MfpLock_S2 MfpLost_S2 MfpW_re_S2 MfpW_im_S2 FspW_re_S2 FspW_im_S2 FspPhase_S2 TdmEnable_T MfpLength_T MfpThrPreSync_T MfpThrSync_T SyncLength_T SyncThr_T SyncLost_T Scrambler1_T Scrambler2_T DataFormat_T TdmStatus_T MfpLost_T MfpW_re_T MfpW_im_T TdmPhase_T TdmSyncCtrl_T SwfgEnable_S SwfgStatus_S Prc_En
7 2 7 4 8 8 7 7 2 5 4 7 7 5 4 4 8 4 4 3 4 8 8 2 1 8 2 3
r r r r r r r r r wr wr wr wr wr wr wr wr wr wr r r r r r wr wr r wr
---------1F 07 2C 28 03 02 0B 05 08 00 -----01 FF -00
satellite one TDM decoding FSP correlation weight, imaginary part satellite one TDM decoding phase satellite two TDM decoding status satellite two TDM decoding extended MFP counter satellite two TDM decoding extended MFP correlation weight, real part satellite two TDM decoding extended MFP correlation weight, imaginary part satellite two TDM decoding FSP correlation weight, real part satellite two TDM decoding FSP correlation weight, imaginary part satellite two TDM decoding phase terrestrial TDM decoding block enable terrestrial TDM decoding MFP detection window length terrestrial TDM decoding MFP detection threshold, pre-synchronization terrestrial TDM decoding MFP detection threshold, synchronization terrestrial TDM decoding TDM synchronization window length terrestrial TDM decoding TDM synchronization found threshold terrestrial TDM decoding TDM synchronization lost threshold terrestrial TDM decoding scrambling polynomial terrestrial TDM decoding data formatting terrestrial TDM decoding status terrestrial TDM decoding MFP correlation lost terrestrial TDM decoding MFP correlation weight, real part terrestrial TDM decoding MFP correlation weight, imaginary part terrestrial TDM decoding TDM phase terrestrial TDM decoding synchronization control satellite weighting factor generation block enable satellite weighting factor generation status 0: TDM PRC interface block enable; 2:1 TDM PRC interface PRC source
34/117
STA400A
Table 6. TDM (Section 1) (continued)
Relative Address (Hex) Register Name WL Type Reset Value (Hex) Comment
51 52 60 61 62 63 64 65 66 67 68 80 81 82 83 84 85 86 90 91 92 93 94 95 96 97 98 99 9A
Prc_Num1 Prc_Num2 DescDataEn DescData_re_T DescData_im_T DescData_re_S1 DescData_im_S1 DescData_re_S2 DescData_im_S2 DescData_S1wfg DescData_S2wfg TpmEnable_S TpmDataFormat_S1 TpmMfpThr_S1 TpmFspThr_S1 TpmDataFormat_S2 TpmMfpThr_S2 TpmFspThr_S2 TpmMfpW_re_S1 TpmMfpW_im_S1 TpmMfpSymSlip1_S1 TpmMfpSymSlip2_S1 TpmFspW_re_S1 TpmFspW_im_S1 TpmFspPosSlip1_S1 TpmFspPosSlip2_S1
TpmFspTdmPhase_S1
8 1 5 8 8 4 4 4 4 4 4 2 2 7 6 2 7 6 8 8 8 4 7 7 8 4 2 2 8
wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr wr r r r r r r r r r r r
00 00 00 00 00 00 00 00 00 00 00 00 00 28 14 00 28 14 ------------
TDM PRC interface: PRC number. (Range from 1 to 258). select signal for multiplexers after descrambler real terrestrial test data imag terrestrial test data real satellite one test data imag satellite one test data real satellite two test data imag satellite two test data SWFG one test data SWFG two test data satellite TDM preamble monitor block enable satellite one TDM preamble monitor input data format satellite one TDM preamble monitor MFP detection threshold satellite one TDM preamble monitor FSP detection threshold satellite two TDM preamble monitor input data format satellite two TDM preamble monitor MFP detection threshold satellite two TDM preamble monitor FSP detection threshold satellite one TDM preamble monitor MFP correlation weight, real part satellite one TDM preamble monitor MFP correlation weight, imaginary part
satellite one TDM preamble monitor MFP symbol slip
satellite one TDM preamble monitor FSP correlation weight, real part satellite one TDM preamble monitor FSP correlation weight, imaginary part satellite one TDM preamble monitor FSP position slip satellite one TDM preamble monitor FSP phase satellite one TDM preamble monitor preamble detection satellite one TDM preamble monitor FSP cycle slip counter
TpmPrDetect_S1 TpmFspCySlipCnt_S1
35/117
STA400A
Table 6. TDM (Section 1) (continued)
Relative Address (Hex) Register Name WL Type Reset Value (Hex) Comment
9B A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB B0 B1 B2 B3 B4 B5 C0 C1 C2 C3 C8 C9 CA CB
TpmFspPoSlipCnt_S1 TpmMfpW_re_S2 TpmMfpW_im_S2 TpmMfpSymSlip1_S2 TpmMfpSymSlip2_S2 TpmFspW_re_S2 TpmFspW_im_S2 TpmFspPosSlip1_S2 TpmFspPosSlip2_S2
TpmFspTdmPhase_S2
8 8 8 8 4 7 7 8 4 2 2 8 8 8 4 8 4 8 2 3 4 5 3 3 4 5 3
r r r r r r r r r r r r r r r r r r r wr wr wr wr wr wr wr wr
-------------------02 03 0F 03 02 03 0F 03
satellite one TDM preamble monitor FSP position slip counter satellite two TDM preamble monitor MFP correlation weight, real part satellite two TDM preamble monitor MFP correlation weight, imaginary part satellite two TDM preamble monitor MFP symbol slip satellite two TDM preamble monitor FSP correlation weight, real part satellite two TDM preamble monitor FSP correlation weight, imaginary part
satellite two TDM preamble monitor FSP symbol slip
satellite two TDM preamble monitor FSP phase satellite two TDM preamble monitor preamble detection satellite two TDM preamble monitor FSP cycle slip counter satellite two TDM preamble monitor FSP position slip counter satellite one TDM decoding symbol slip satellite two TDM decoding symbol slip terrestrial TDM decoding symbol slip Satellite one TDM decoding FSP detection start window length Satellite one TDM decoding FSP detection hunt window increment
Satellite one TDM decoding FSP short dropout length
TpmPrDetect_S2 TpmFspCySlipCnt_S2 TpmFspPoSlipCnt_S2 TdmSySlip1_S1 TdmSySlip2_S1 TdmSySlip1_S2 TdmSySlip2_S2 TdmSySlip1_T TdmSySlip2_T FspStarWinLen_S1 FspHuntWinInc_S1
FspShDropOutLen_S1
FspSecuAlignThr_S1 FspStarWinLen_S2 FspHuntWinInc_S2
FspShDropOutLen_S2
Satellite one TDM decoding FSP secure alignment threshold Satellite two TDM decoding FSP detection start window length Satellite two TDM decoding FSP detection hunt window increment
Satellite two TDM decoding FSP short dropout length
FspSecuAlignThr_S2
Satellite two TDM decoding FSP secure alignment threshold
36/117
STA400A
Table 7. FEC Base Address: 03 - Address Range: 00 - 51
Relative Address (Hex) Register Name WL Type Reset Value (Hex) Comment
00 01 02 07 08 09 0A 0B 0C 10 20 21 24 25 28 29 30 31 32 35 36 37 38 40 42 43 44 45 46 50 51
Control_F Status_F ErrorCtrl_F InitState_F InitLfsr1_F InitLfsr2_F InitTerm1_F InitTerm2_F InitTerm3_F VitBerCtrl_F TerrBer1_F TerrBer2_F Sat1Ber1_F Sat1Ber2_F Sat2Ber1_F Sat2Ber1_F ForceCorr_F RS_Ctrl_F RS_Cnt_F RS_ByeCnt1_F RS_ByeCnt2_F RS_FrameCnt1_F RS_FrameCnt2_F InitSeq_F RS1_TerrByteErr_F RS2_TerrByteErr_F RS1_SatByteErr_F RS2_SatByteErr_F RS_Block_decis_F IrqMask_F IrqStatus_F
6 4 6 6 8 4 8 8 4 4 8 4 8 4 8 4 8 4 1 8 6 8 2 8 5 5 5 5 2 5 5
wr r wr wr wr wr wr wr wr wr r r r r r r wr wr wrt r r r r wr r r r r r int int
3F -01 2E CC 0C 00 80 0B 0F ------1D 03 01 ----1D -----00 00
control vector for FEC and FEC Preprocessing status flags of FEC Processing blocks (FEC Preproc, VD, FEC Mgmt, RS input control) FEC error reporting initial state of convolutional decoder after training sequence initial state of flush LFSR
termination sequence after flush operation
Viterbi BER Measurement control flags Terrestrial channel error rate
Sat1 channel error rate
Sat2 channel error rate
forced correction value for PRC preamble (1D hex) RS/RS Input Control configuration bits RS Decoder Error Counter Control RS byte error counter
RS frame error counter
initialization sequence for VD (PRC preamble 1D hex) terr. Reed-Solomon block 1 error reporting terr. Reed-Solomon block 2 error reporting sat. Reed-Solomon block 1 error reporting sat. Reed-Solomon block 2 error reporting status of last Reed-Solomon diversity decision FEC interrupt mask FEC interrupt status
37/117
STA400A
Table 8. IF Sampling and Control Interface Base Address: 04 - Address Range: 00 - 20
Relative Address (Hex) Register Name WL Type Reset Value (Hex) Comment
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 17 19 1B 1D 1F 20
AGC_CTRL1 SAGCREF0 SAGCREF1 SAGCINTG TAGCREF0 TAGCREF1 TAGCINTG IF_CTRL
8 8 5 8 8 5 8 2 8 8
wr wr wr wr wr wr wr wr wr wr wr wr wr wr
88 90 01 00 90 01 00 00 00 00 00 00 03 00
Terr. and Sat. AGC Control Register1 Satellite Agc Reference (LSB) Satellite Agc Reference (MSB) 8MSB of Satellite AGC Integrator Terrestrial Agc Reference (LSB) Terrestrial Agc Reference (MSB) 8MSB of Terr. AGC Integrator IF Sampling Control Register Reserved Reserved Block Functional Test Output Sel. CDEC Functional Test Output Sel. Master Clock Programmable Divider Control of the interface for external BER measurement Reserved for Future Use Reserved for Future Use
SELTSTOUT TSTMUXCTL CLKDIV_CONF QPSK_BER_CTRL
4 4 2
CONTROL
8 8 8 8 8 8
wr wr r r r r wr pr wr pr r r
00 00 ----00 00 00 00 ---
General Purpose Control Reserved Reserved Reserved Reserved Reserved Interrupt #1 Mask Interrupt #1 Status Reserved for Future Use Reserved for Future Use General Purpose Status Reserved for Future Use
IRQ1_MASK IRQ1_STATUS
8 8 8 8
STATUS1
8 8
38/117
STA400A
Table 9. PC Bitsctream Interface Base Address: 05 - Address Range: 00 - 06
Relative Address (Hex) Register Name WL Type Reset Value (Hex) Comment
00 01 02 03 04 05 06
PCDC_CONF_0 PCDC_CONF_1 PCSD_CONF_0 PCSD_CONF_1 PCSYNC_CONF
7 7 6 6 8 8
wr wr wr wr wr wr pr
00 00 00 00 77 00 00
Clock Configuration for PC Interface #0 Clock Configuration for PC Interface #1 Output Data Configuration for PC Interface #0 Output Data Configuration for PC Interface #1 Synchronization Signals Configuration for both Interfaces Reserved For Future Use Alarm Signals for Interface #0 and #1
PC_ALARM
2
Table 10. TDM (Section 2) Base Address: 06 - Address Range: 10 - F6
Relative Address (Hex) Register Name WL Type Reset Value (Hex) Comment
10 11 20 21 22 23 24 25 30 31 32 34 35 36 37 38 40 41 42 43 44
DeltaRefCyc1_M DeltaRefCyc2_M MfpSyncMax_S1 MfpSyncMin_S1 MfpSyncMax_S2 MfpSyncMin_S2 MfpSyncMax_T MfpSyncMin_T Xmem_Type XmemRefCyc1 XmemRefCyc2 XmemMode XmemStatus XmemStErrAdr1 XmemStErrAdr2 XmemStErrAdr3 UdCycDelta1_T UdCycDelta2_T Cnt_Prio Ud_Cycles1 Ud_Cycles2
8 5 8 8 8 8 8 8 1 8 1 2 2 8 8 8 8 3 8 8 3
r r wr wr wr wr wr wr wr wr wr wr r r r r wr wr wr wr wr
--46 2F 46 2F 11 29 00 75 01 00 ----00 00 80 9C 00
delta reference cycles for MCM Frame Sync
set the rightmost distance of sat1 MFP sync set the leftmost distance of sat1 MFP sync set the rightmost distance of sat2 MFP sync set the leftmost distance of sat2 MFP sync set the rightmost distance of terrestrial MFP sync set the leftmost distance of terrestrial MFP sync external memory device type external memory refresh cycle period
external memory management mode external memory management status external memory management self-test error address
MFP Cycle Number Up Down Delta
MFP Cycles Time Internal Setting MFP Cycle Number Adiustment.
39/117
STA400A
Table 10. TDM (Section 2) (continued)
Relative Address (Hex) Register Name WL Type Reset Value (Hex) Comment
45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5B 61-F0 F5 F6
FrameLen1 FrameLen2 FrameLen3 DeltaCycles1 DeltaCycles2 MFC1 MFC2 MFC_lsb Tdm2Enable XmemFifoLevel PcidDataRd1 PcidDataRd2 PcidDataWr1 PcidDataWr2 PcidAddr PRC_ti Tscw_Err Tscw_AddrRd Tscw_Data StatusErr_T MgmtCtrl_T Tscw_AddrCurr BK1-BK144 IrqMask_T IrqStatus_T
8 8 8 8 3 8 3 7 8 4 8 2 8 2 5 8 2 8 8 2 4 8 8 3 3
wr wr wr r r r r r wr r r r wrt wrt wr wr wr wrt rt r wr r trt int int
00 AD 9D -----FF ---00 00 00 C8 00 00 --03 -FF 00 00
TDM frame length
MFP Clock Period Monitor
Master Frame counter
Master Frame counter (LSB) TDM management block enable External memory write access buffer filling level pcid table read register
pcid number and pcid interface enable
address of the pcid in the table Sets the time interval between the output of two PRCs. Sets what is done if the TSCW has uncorrected errors start address of register of TSCW table, which shall to be read contents of addressed TSCW word (enables autoincrement function of address when read access) read management enable and error flag control vector for TDM management address of current register of TSCW table, which is read TDM management bookkeeping matrix TDM interrupt mask TDM interrupt status
Table 11. Terrestrial Demodulator (Section 2) Base Address: 07 - Address Range: 10 - 81
Relative Address (Hex) Register Name WL Type Reset Value (Hex) Comment
10 11
CfCntGood1_M CfCntGood2_M
8 8
pr pr
00 00
counter for Coarse Frequency Good events
40/117
STA400A
Table 11. Terrestrial Demodulator (Section 2)
15 16 18 20 21 22 23 24 26 27 28 29 2A 2B 2D 30 31 35 40 41 45 50 51 55 80 81 CfCntBad1_M CfCntBad2_M CfCtrl_M Cf_MinKexpLow_M Cf_DiffKexpMaxLow_M Cf_Delta_KexpLow_M Cf_DeltaCntLow1_M Cf_DeltaCntLow2_M Cf_MaxKexpHigh_M Cf_DiffKexpMaxHigh_M Cf_DeltaKexpHigh_M Cf_DeltaCntHigh1_M Cf_DeltaCntHigh2_M Cf_InitDelay_M Cf_KexpThAct_M Cf_EstAct1_M Cf_EstAct2_M Cf_KestActExp_M Cf_Est1_M Cf_Est2_M Cf_EstExp_M Cf_AvgEst1_M Cf_AvgEst2_M Cf_AvgEstExp_M Cf_AvgCtrl Cf_AvgMinEstConf_M 8 8 1 8 8 8 8 2 8 8 8 8 2 5 8 8 8 8 8 8 8 8 8 8 8 8 pr pr wr wr wr wr wr wr wr wr wr wr wr wr r r r r r r r r r r wr wr 00 00 00 90 08 01 20 00 FF 06 01 01 00 17 ----------B0 00 current MCM CF Averager confidence estimate MCM Coarse Freq Averager control vector MCM Coarse Freq Averager: threshold for CF confidence coarse frequency confidence exponent of received AMSS after averaging current MCM CF Averager estimate coarse frequency confidence exponent of received AMSS before averaging coarse frequency estimation of received AMSS after averaging control of initial behavior of cf estimation current confidence threshold value coarse frequency estimation of received AMSS before averaging control of confidence threshold calculation for cf estimation control of confidence threshold calculation for cf estimation control of confidence threshold calculation for cf estimation control of confidence threshold calculation for cf estimation control of cf algorithm control of confidence threshold calculation for cf estimation control of confidence threshold calculation for cf estimation control of confidence threshold calculation for cf estimation control of confidence threshold calculation for cf estimation counter for Coarse Frequency Bad events
41/117
STA400A
2.2 QPSK Demodulator (S1-Early/S2-Late) The two QPSK demodulators (S1-Early and S2-Late) have the same register set so they have been listed below once. The registers have different addresses and the same reset value except for the IFFREQ register. QPSK_DEMOD_EN - QPSK Demodulator Enable Register This register disables the QPSK demodulator when bit-0 is set to '0'. When disabled the demodulator output is fixed to '0x00' or to '0x80' depending on the bit-4 setting of the QPSK_CTRL register (address 0x005A/0x0080)
Type: SingleByte - R/W Word Length: 1 Byte Name Address (Hex) Bit Map Reset Value (Hex)
QPSK_DEMOD_EN1
S1/S2
0059/007F
7-0
01
b7-b1: b0: DEM_EN
Not Used 0=Demodulator disabled; 1=Demodulator enabled.
QPSK_CTRL - QPSK Demodulator Control Register This is a control register for the QPSK demodulator.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
QPSK_CTRL
S1/S2
005A/0080
7-0
4F
b7: b6: b5: b4: b3: b2: b1: b0:
AVG_OFF NULOFS_EN
This bit disables the averager filter of the integrators. 0=Averager Filter enabled; 1=Averager Filter disabled. This bit enables/disables the NULOFS block. 0=Disabled; 1=Enabled. Reserved.
DEM2TDM_FMT IQSWAP QCHS TIMCHS CARCHS
Output Data Format. 0=Two's complement; 1=Offset binary. This bit swaps the I and Q component of the demodulator output. 0=No Change; 1=Swaps I with Q. This bit inverts the Q component sign in the I/Q mixer. 0=No invertion; 1=Sign invertion. This bit inverts the timing loop sign. 0=No invertion; 1=Sign invertion. This bit inverts the carrier loop sign. 0=No invertion; 1=Sign invertion.
42/117
STA400A
PFDTHR - Phase/Frequency Error Detector Threshold This register sets the threshold for the frequency detector. The number format is positive integer.
Type: SingleByte - R/W Word Length: 6 Byte Name Address (Hex) Bit Map Reset Value (Hex)
PFDTHR
S1/S2
005B/0081
5-0
14
SYMFREQ - Symbol Frequency This register sets the symbol frequency of the Timing NCO (equal to 1.64MHz for both satellite demodulators). It is 25 bit long and is divided into four bytes; SYMFREQ0 is the LSB byte, SYMFREQ3 is the MSB. SYMFREQ

F s ym 25 must be loaded with an interger value given by SYMFR EQ = int 0.5 + ----------------- 2 F M CLK

where FMCLK =
23.92MHz is the master clock frequency, Fsym is the symbol frequency and Int(.) is the integer part of the number.
Type: MultiBytes - R/W Word Length: 25 Byte Name Address (Hex) Bit Map Reset Value (Hex)
SYMFREQ3 SYMFREQ2 SYMFREQ1 SYMFREQ0
S1/S2 S1/S2 S1/S2 S1/S2
005F/0085 005E/0084 005D/0083 005C/0082
24 23-16 15-8 7-0
00 23 1A 8B
IFFREQ - Intemediate Frequency This register sets the 2nd intermediate carrier frequency of the I/Q Mixer. It is 28 bit long and is divided into four bytes; IFFREQ0 is the LSB byte, IFFREQ3 is the MSB. IFFREQ must be loaded with an interger value given by Fc 28 IFFREQ = in t 0.5 + ----------------- 2 where FMCLK = 23.92MHz is the master clock frequency, Fc is the second F M CL K intermediate frequency (5.175MHz for S2-Late satellite and 7.015MHz for S1-Early satellite) and Int(.) is the integer part of the number.
Type: MultiBytes - R/W Word Length: 28 Byte Name Address (Hex) Bit Map Reset Value (Hex)

IFFREQ3 IFFREQ2 IFFREQ1 IFFREQ0
S1/S2 S1/S2 S1/S2 S1/S2
0063/0089 0062/0088 0061/0087 0060/0086
27-24 23-16 15-8 7-0
04/03 B1/76 3B/27 14/62
43/117
STA400A
ALFACAR - Carrier Loop Filter Alpha Parameter This register sets the proportional gain of the carrier loop. It must be loaded with a positive integer number from 0x00 to 0xFF (0 to 255 decimal).
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
ALFACAR
S1/S2
0064/008A
7-0
17
b7-b0: ALPHA
Positive integer, range 0 to 255 decimal.
BETACAR - Carrier Loop Filter Beta Parameter This register sets the integral gain of the carrier loop. The representation of the number is mantissa-exponent (base 2): beta = beta_m x 2(beta_e)
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
BETACAR
S1/S2
0065/008B
7-0
15
b7-b5: b4-b0:
BETA_E BETA_M
Exponent of the number. Positive integer, range 0 to 7 decimal. Mantissa of the number. Positive integer, range 0 to 31 decimal.
ALFATIM - Timing Loop Filter Alpha Parameter This register sets the proportional gain of the timing loop. It must be loaded with a positive integer number from 0x00 to 0xFF (0 to 255 decimal).
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
ALFATIM
S1/S2
0066/008C
7-0
07
b7-b0:
ALPHA
Positive integer, range 0 to 255 decimal.
BETATIM - Timing Loop Filter Beta Parameter This register sets the integral gain of the timing loop. The representation of the number is mantissa-exponent (base 2): beta = beta_m x 2(beta_e)
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
BETATIM
S1/S2
0067/008D
7-0
0E
b7-b5: b4-b0:
BETA_E BETA_M
Exponent of the number. Positive integer, range 0 to 7 decimal. Mantissa of the number. Positive integer, range 0 to 31 decimal.
44/117
STA400A
RAMPCTRL - Frequency Sweep Control Register This register controls the operation of the frequency sweep block.
Type: SingleByte - R/W Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
RAMPCTRL
S1/S2
0068/008E
6-0
20
b7: b6: b5: b4: b3-b0: . SLOPE SWON SWSTEP STEPPER
RFU 0=Positive; 1=Negative 0=Sweep Disabled; 1=Sweep Enabled 0=Multiply by 1; 1=Multiply by 2 0000=Divide by 1 0001=Divide by 2 1111=Divide by 16
AGC2BETA - AGC2 Loop Gain This register sets the AGC2 Loop Gain according to the following formula: AGC2 = 2AGC2BETA
Type: SingleByte - R/W Word Length: 3 Byte Name Address (Hex) Bit Map Reset Value (Hex)
AGC2BETA
S1/S2
0069/008F
2-0
03
b7-b3: b2-b0:
Not Used AGC2BETA 000 -> Gain=1 001 -> Gain=2 010 -> Gain=4 011 -> Gain=8 101 -> Gain=32 110 -> Gain=64 100 -> Gain=16 111 -> Gain=0
AGC2REF - AGC2 Reference This registers sets the reference level or the AGC2 loop. The format is positive integer from 0 to 255 decimal.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
AGC2REF
S1/S2
006A/0090
7-0
5A
b7-b0:
AGC2REF
Positive integer, range 0 to 255 decimal
AGC2INTG - 8 MSBs of AGC2 Loop Integrator This register contains the 8 MSBs of the AGC2 loop integrator. The format is two's complement.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
AGC2INTG
S1/S2
006B/0091
7-0
00
45/117
STA400A
TIMINTG - 8 MSBs of Timing Loop Integrator This register contains the 8 MSBs of the timing loop integrator. The format is two's complement.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TIMINTG
S1/S2
006C/0092
7-0
00
CARINTG - 8 MSBs of Carrier Loop Integrator This register contains the 8 MSBs of the carrier loop integrator. The format is two's complement.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
CARINTG
S1/S2
006D/0093
7-0
00
CARFREQ - Locked Carrier Frequency This register is 28 bit long and is divided into four bytes; CARFREQ0 is the LSB byte, CARFREQ3 is the MSB. It contains the carrier frequency on which the demodulator is locked. The format is two's complement.
Type: MultiBytes - R Word Length: 28 Byte Name Address (Hex) Bit Map Reset Value (Hex)
CARFREQ3 CARFREQ2 CARFREQ1 CARFREQ0
S1/S2 S1/S2 S1/S2 S1/S2
0071/0097 0070/0096 006F/0095 006E/0094
27-24 23-16 15-8 7-0
-----
CN- Carrier to Noise Esteem This register gives the Carrier to Noise Ratio estimation in dB. The number has a fixed point format.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
CN
S1/S2
0072/0098
7-0
--
b7- b3 : Integer Part b2- b0 : Fractional Part Example : CN = '10010111' = (100101.11)bin = (37.75)dec => C/N = 37.75dB FLAG - Demodulator Status Register This is a read only register containing specific status bit of the demodulator.
Type: SingleByte - R Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FLAG
S1/S2
0073/0099
7-4
--
b7: b6:
46/117
LOCK
0=Demodulator Locked; 1=Demodulator Unlocked
TIMINTG_CLR 0=Timing Integrator Cleared; 1=Timing Integrator Active
STA400A
b5: b4: b3-b0: CARINTG_CLR 0=Carrier Integrator Cleared; 1=Carrier Integrator Active CLR_RAMP 0=Ramp Cleared; 1=Ramp Active RFU
NULOFS_WIN - Null Carrier Offset Window The CarrierNullOffset block writes the new IF Frequency in the Carrier NCO if the demodulator lock signal is low for a period of time equal to the value written in this register. The window length is given in msec.
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
NULOFS_WIN
S1/S2
0074/009A
3-0
07
b3-b0:
NULOFS_WIN 0000 -> 10msec 0001 -> 20msec 0010 -> 30msec 0011 -> 40msec
0100 -> 50msec
1000 -> 175msec
1100 -> 350msec 1101 -> 400msec 1110 -> 450msec 1111 -> 500msec
0101 -> 100msec 1001 -> 200msec 0110 -> 125msec 1010 -> 250msec 0111 -> 150msec 1011 -> 300msec
NULOFS_DELTAF - Null Carrier Offset Delta Frequency The CarrierNullOffset block subtracts from the locked carrier frequency the value contains in this register before writing the new IF Frequency in the Carrier NCO. The register format is two's complent. Given a frequency FREQ in Hz, the value to load in the register is given by: 2 NU LOFS_D ELTAF = Int FREQ ---------------------------- + 0.5 where Int(.) is the integer function. 512F M CLK
28
Type: SingleByte - R/W
Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
NULOFS_DELTAF
S1/S2
0075/009B
7-0
2B
TIMLPF_CTRL - Timing Loop Filter Control This register controls the operation of the Timing Loop Filter.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TIMLPF_CTRL
S1/S2
0076/009C
7-0
90
b7: b6-b5: b4:
TIMAVG_OFF TIMINTG_CLR_WIN TIMINTG_CLR_EN
0=Self-Noise Filter enabled; 1=Self-Noise Filter disabled. 00 -> Window=10sec 01 -> Window=20sec 10 -> Window=40sec 11 -> Window=60sec
0=TimintgCtrl block disabled; 1=TimintgCtrl block enabled
47/117
STA400A
b3: b2-b0: TIMLPF_LENGTH RFU 000 -> Timing Integrator bit length =8100 -> Timing Integrator bit length =14 001 -> Timing Integrator bit length =9101 -> Timing Integrator bit length =16 010 -> Timing Integrator bit length =10110 -> Timing Integrator bit length =18 011 -> Timing Integrator bit length =12111 -> Timing Integrator bit length =20 LOCKTHR - Lock Detector Threshold This register sets the threshold for the lock detector block.
Type: SingleByte - R/W Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
LOCKTHR
S1/S2
0077
1-0
02
b1-b0:
LOCKTHR
00 -> Threshold = 32 dec 01 -> Threshold = 64 dec 10 -> Threshold = 80 dec 11 -> Threshold = 96 dec
2.3 Terrestrial Demodulator (Section 1) Enable_M - MCM Demodulator Enable Register MCM Submodules Enable Signals. Enable active on `1'.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Enable_M
0100
7-0
FF
b7: b6: b5: b4: b3: b2: b1: b0:
mrm_ff_demod_en mrm_fc_demod_en mrm_cf_demod_en mrm_ss_demod_en mrm_fs_demod_en mrm_pp_demod_en mrm_fft_demod_en mrm_iqg_demod_en
enable of Fine Frequency submodule enable of Frequency Control submodule enable of Coarse Frequency submodule enable of Symbol Synchronization submodule enable of Frame Synchronization submodule enable of Pre Processing submodule enable of FFT submodule enable of I/Q Generation submodule
Status_M - MCM Demodulator Status Register Status information of mcm submodule
Type: MultiBytes - R Word Length: 10 Byte Name Address (Hex) Bit Map Reset Value (Hex)
STATUS2_M STATUS1_M
0102 0101
9-8 7-0
---
48/117
STA400A
b9 : b8 : b7-b6 : mfc_freq_lock mff_ff_state mfc_fc_state 0= NO LOCK; 1= LOCK 0=IDLE; 1= OPERATIONAL 00= IDLE 01= INIT 10= TRACKING 11= FREEZE b5 : b4 : b3-b2 : mcf_cf_state mss_ss_state mfs_fs_state 0=IDLE; 1= OPERATIONAL 0= IDLE; 1= ACTIVE (channel window active) 00= IDLE 01= HUNT 10= PRE SYNC 11= SYNC b1 : b0 : mpp_pp_state mfft_fft_state 0=IDLE; 1= OPERATIONAL 0=IDLE; 1= OPERATIONAL
DataOvf_M - MCM Demodulator Blocks Overflow Register Overflow bit event counter of iqgen, lpf and nco.The internal overflow bits are "ored" and counted. This may be an indication that the input signal is to strong so that internal overflow occurs.
Type: SingleByte - PR Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
DataOvf_M
0104
7-0
00
IQGMode_M - IQ Generation Mode Inverts and interchanges of I and Q at the output of the IQ Generation. Required for A,B ensemble switch. For ensemble A value of 02h and for ensemble B the default value of 00h must be used.
Type: SingleByte - R/W Word Length: 3 Byte Name Address (Hex) Bit Map Reset Value (Hex)
IQGMode_M
0106
2-0
02
b2 : b1 : b0 :
Interchange of Re and Im data Sign Invertion of Im data Sign Invertion of Re data
Clk_devcomp_M - Clock Deviation Compensation Mode
Type: SingleByte - R/W Word Length: 1 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Clk_devcomp_M
0107
0
01
b0 :
`1'=Signal coming from TDM management will be used `0'=Signal coming from Register Map (CycleCntRe) will be used
49/117
STA400A
AMSSThrL_M - AMSS Detection Low Threshold If the correlation exceeds this threshold a valid AMSS sequence is recognized and the Channel window is started.
Type: SingleByte - R/W Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
AMSSThrL_M
0108
6-0
37
AMSSThrH_M - AMSS Detection High Threshold This threshold is used in addition to mrm_amss_low_corr_th to improve performance for good channels showing a high correlation value.
Type: SingleByte - R/W Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
AMSSThrH_M
0109
6-0
41
AMSSFailed_M - AMSS Not Detected Event This register sets the number of events that are necessary to reach the sync state within SyncSearch_M subsequent frame_windows. Otherwise the state machine will be set back to the hunt state.
Type: SingleByte - R/W Word Length: 3 Byte Name Address (Hex) Bit Map Reset Value (Hex)
AMSSFailed_M
010A
2-0
07
SyncSearch_M - Pre-Synch MCM Frames Number See AMSSFailed_M for description
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
SyncSearch_M
010B
3-0
0A
SyncLoss_M - Number of Allowed AMSS Failed Event If AMSS failed events equal to the value ste in this register occurs subsequently, the state machine will be set back to the hunt state.
Type: MultiBytes - R/W Word Length: 11 Byte Name Address (Hex) Bit Map Reset Value (Hex)
SyncLoss2_M SyncLoss1_M
010D 010C
10-8 7-0
03 FF
50/117
STA400A
FrameLen_M - AMSS Detection Frame Window Length This register sets the window value within which, before and after the expected AMSS sequence, the occurance of the AMSS sequence is searched. Value corresponds to mcm symbol rate
Type: SingleByte - R/W
Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FrameLen_M
010E
7-0
B4
ChannelLen_M - AMSS Detection Channel Window Length Window while searching for higher AMSS correlation peaks. Value corresponds to mcm symbol rate.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
ChannelLen_M
010F
7-0
B4
CycleCnt_M - MCM Frame Cycle Count Difference wrt Nominal Value This value is computed due to the internal clock adjustment based on MFP evaluation.
Type: MultiBytes - R Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
CycleCnt2_M CycleCnt1_M
0111 0110
11-8 7-0
---
CycleCntRef_M - MCM Frame Cycle Count Difference Setting External setting of actual difference of mcm-frame cycle count to nominal value.
Type: MultiBytes - WRT Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
CycleCntRef2_M CycleCntRef1_M
0113 0112
11-8 7-0
00 00
AttFactor_M - Attenuation Factor Attenuation factor for correlation results inside channel window. Used for determination of guard window position.
Type: MultiBytes - R/W Word Length: 13 Byte Name Address (Hex) Bit Map Reset Value (Hex)
AttFactor2_M AttFactor1_M
0116 0115
12-8 7-0
1F F0
51/117
STA400A
attenuation function: ( k ) = 10
k a --------- -------------2k 0 20dB
; (k + 1) = (k) +b
k0 = channel window length (in Symbol Rate), a = attenuation factor (in dB) and b= corr_weight_factor / 213 b = 10
k a --------- -------------2k 0 20d B
Constant Channel Window (Ko=180 samples):
Attenuation b (*213)
0dB 3dB 6dB 12dB
8192 8184 8176 8160
Constant Attenuation (3dB):
Channel Window b(*213)
180 90 45
8184 8176 8160
HistLen_M - History Register Length Stores the last 15 shift operations of the window start position. The chosen value will restrict the array out of which the minimum shift operation will be searched.
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
HistLen_M
0117
3-0
0F
b3-b0 : 0000=Current correlation maximum will be proceeded . 1111=Current and the last 15 correlation positions will be taken account CN_M - Estimated Noise ans Signal to Noise Power Uses 12 adjacent carriers besides the active carriers. Estimates power within these 24 adjacent carriers (mff_n_guard) and power within all 637 active carriers (mff_cpn_act).
Type: MultiBytes - R Word Length: 24 Byte Name Address (Hex) Bit Map Reset Value (Hex)
CN3_M CN2_M CN1_M
011B 011A 0119
23-16 15-8 7-0
----
b23-b12 : b11-b0 :
52/117
mff_n_guard mff_cpn_act
STA400A
FfCtrl_M - Fine Frequency Control Register If mrm_ff_fed_mean_en is set to `1' the ouput of the FED is averaged over two adjacent mcm symbols. If mrm_ff_lpf_sel is set to `1' an IT1 controller is implemented, otherwise a pure I controller. The mrm_ff_alpha value determines the integral part for both IT1 and I controller.
Type: SingleByte - R/W Word Length: 6 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FfCtrl_M
011C
5-0
1E
b5-b2: b1: b0:
mrm_ff_alpha mrm_ff_lpf_set mrm_ff_fed_mean_en
FfBeta_M - Fine Frequency Loop Filter Beta Constant If mrm_ff_lpf_sel is set to `1' the mrm_ff_beta value sets the proportional part for the IT1 controller. For a pure I controller mrm_ff_beta is not used.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FfBeta_M
011D
7-0
04
BlkDetect_M - Frequency Control Blockage Condition During blockage (mrm_blockage_detect = `1') the Frequency Control state is set to FREEZE. In that state the frequency offset is held and no further actions are untertaken.
Type: SingleByte - R/W Word Length: 1 Byte Name Address (Hex) Bit Map Reset Value (Hex)
BlkDetect_M
011F
0
00
b0:
mrm_blockage_detect
InitDelay_M - Fine Frequency Statup Delay This register sets the number for which the Frequency Control remains within the INIT state before entering the TRACKING state, i.e. the corresponding number of Fine Frequency estimates are discarded after external reset or internal clear.
Type: SingleByte - R/W Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
InitDelay_M
0120
1-0
00
53/117
STA400A
MaxFreq_M - Fine Frequency Out-Of-Range Setting Maximum Allowed Difference of fine frequency and coarse frequency estimation to Detect Out-of-Range Condition of ff. If the difference between Fine and Coarse Frequency estimation is equal or larger than this value, the Fine Frequency is considered out of range and is internally cleared. The value is in units of 91.25Hz (2.99e6/ 32368).
Type: MultiBytes - R/W Word Length: 13 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MaxFreq2_M MaxFreq1_M
0122 0121
12-8 7-0
00 46
MinCf_M - Coarse Frequency Estimation Confidence Value Only Coarse Frequency estimations with a confidence value equal or larger than the value set in this register are considered as valid and loaded into the internal coarse frequency estimation value register.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MinCf_M
0123
7-0
90
CfRef_M - Coarse Frequency Offset Setting External value for coarse frequency estimation. This value will be overwritten if the Coarse Frequency delivers valid estimations. The value is in units of 91.25Hz (2.99e6/32768).
Type: MultiBytes - WRT Word Length: 13 Byte Name Address (Hex) Bit Map Reset Value (Hex)
CfRef2_M CfRef1_M
0125 0124
12-8 7-0
00 00
CfValue_M - Coarse Frequency Offset Value The value is in units of 91.25Hz (2.99e6/32768).
Type: MultiBytes - R Word Length: 13 Byte Name Address (Hex) Bit Map Reset Value (Hex)
CfValue2_M CfValue1_M
0127 0126
12-8 7-0
---
54/117
STA400A
FfScale_M - Fine Frequency Scale Factor Factor that is multiplied with the Fine Frequency estimates to get the Frequency Control's internally used estimate. The msb bit has a weight of 0.5, i.e. a value of FF h is interpreted as a factor of 255/256. This value has to considered together with the control constants of the Fine Frequency Control loop.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FfScale_M
0128
7-0
E0
Ff_OOR_M - Fine Frequency Out-Of-Range Counter This counter counts up if the Fine Frequency Estimate is considered as out of range and the Fine Frequency Control loop is reset (see register max Freq_M, addr: 0x0121/22).
Type: SingleByte - PR Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Ff_OOR_M
012A
7-0
00
EpocEn_M - Error Phase Offset Correction Enable If this bit is set, the EPOC algorithm inside the Post Processing is enabled
Type: SingleByte - R/W Word Length: 1 Byte Name Address (Hex) Bit Map Reset Value (Hex)
EpocEn_M
0133
0
01
DemapCtrl_M - Demapping Control The Re and Im input values are cross added to get the output Re and Im values corresponding to the metric used for the FEC. This register determines this metric generation calculations.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
DemapCtrl_M
0134
7-0
E0
b7: b6: b5: b4: b3: b2: b1: b0:
sign control inverts Re input value for the Re output sign control inverts Im input value for the Re output sign control inverts Re input value for the Im output sign control inverts Im input value for the Im output pass control force zero of Re input value for the Re output pass control force zero of Im input value for the Re output pass control force zero of Re input value for the Im output pass control force zero of Im input value for the Im output
55/117
STA400A
EpocThr_M - Error Phase Offset Correction Threshold Only carriers with a Re value equal or larger than mrm_epoc_thresh are taken for the EPOC internally calculations. The value is relative to the dynamic range of the signal. A value of 0FFF corresponds to 2047/2048. The msb must be set always to `0'.
Type: MultiBytes - R/W Word Length: 14 Byte Name Address (Hex) Bit Map Reset Value (Hex)
EpocThr2_M EpocThr1_M
0136 0135
13-8 7-0
06 00
NormShift_M - FFT Normalization Normalization factor for FFT output. This register scales the FFT output by a factor of 2norm_shift_M. (mantissa only)
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
NormShift_M
0137
3-0
0B
LinScale_M - FFT Output Linear Scaling The register mrm_lin_scale performs a linear scaling of the FFT output data. The register values from 0 to 255 correspond to an actual scaling factor of Lin_scale_M/128, i.e. from 0 to 255/128. The default of 128 corresponds to a scaling factor of 1.0.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
LinScale_M
0138
7-0
80
ShiftOvfl_M - NormShift Overflow Counter Overflow counter of FFT shift and norm shift together. The counter trigger is set if the normalization 0x37 is too large so that overall scaling is too large.
Type: SingleByte - PR Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
ShiftOvfl_M
0139
7-0
00
LimitOvfl_M - Pre Processing Overflow Counter Overflow event counter if the range of scale FFT data exceeds input range of PreProcessing.
Type: SingleByte - PR Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
LimitOvfl_M
013B
7-0
00
56/117
STA400A
EpocCarriers_M - Number of Carrier for Error Phase Offset Correction Shows the number of utilized active sub-carriers to compute EPOC correction phasor for current MCM symbol. Number can range from 0 to 636 (=0x27C).
Type: MultiBytes - R Word Length: 10 Byte Name Address (Hex) Bit Map Reset Value (Hex)
EpocCarriers2_M EpocCarriers1_M
013D 013C
9-8 7-0
---
EpocRotRe_M - Error Phase Offset Correction Phasor (Real Part) Real part of EPOC correction phasor. The value is in 2's complement with a range from -1 to 1 - 2-7 quantized with 8 bits.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
EpocRotRe_M
013E
7-0
--
EpocRotIm_M - Error Phase Offset Correction Phasor (Imaginary Part) Imaginary part of EPOC correction phasor. The value is in 2's complement with a range from -1 to 1 - 2-7 quantized with 8 bits.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
EpocRotIm_M
013F
7-0
--
PSFrameCnt_M - Frame Counter in Pre Sync State Counter of frames during presync state
Type: SingleByte - R Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
PSFrameCnt_M
0140
3-0
--
PS_NoAMSSCnt_M - Frame Counter Without AMSS Detection
Type: SingleByte - R Word Length: 3 Byte Name Address (Hex) Bit Map Reset Value (Hex)
PS_NoAMSSCnt_M
0141
2-0
--
AMSSFailCnt_M - Sequent Frame Counter Without AMSS Detection Counter of sequent frames without AMSS detection during sync state. It will be reset after one succesfull detection
Type: MultiBytes - R Word Length: 16 Byte Name Address (Hex) Bit Map Reset Value (Hex)
AMSSFailCnt2_M AMSSFailCnt1_M
0143 0142
15-8 7-0
---
57/117
STA400A
OivlAMSSFail_M - AMSS Failed Detection Number Number of failed amss detections during an interval whose length can be set by register adr. 0x0196/96
Type: MultiBytes - R Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
OivlAMSSFail2_M OivlAMSSFail1_M
0145 0144
11-8 7-0
---
MaxCorrIw_M - Maximum Correlation Inside Channel Window
Type: SingleByte - RT Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MaxCorrIw_M
0147
6-0
--
MaxCorrOw_M - Maximum Correlation Outside Channel Window
Type: SingleByte - RT Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MaxCorrOw_M
0149
6-0
--
MinCorrIw_M - Minimum Correlation Inside Channel Window
Type: SingleByte - RT Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MinCorrIw_M
014B
6-0
--
MinCorrOw_M - Minimum Correlation Outside Channel Window
Type: SingleByte - RT Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MinCorrOw_M
014D
6-0
--
FrameToggle_M - Frame Toggle Flag Register
Type: SingleByte - R Word Length: 1 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FrameToggle_M
014F
0
--
58/117
STA400A
CorrMaxAkt_M - Actual Maximum Correlation Inside Channel Window This value stores the actual weighted maximum correlation value inside the channel window
Type: SingleByte - R Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
CorrMaxAkt_M
0150
6-0
--
CorrMaxPos_M - Actual Correlation Position Inside Frame Window This value stores the actual position inside the channel window of weighted maximum correlation value:
Type: MultiBytes - R Word Length: 11 Byte Name Address (Hex) Bit Map Reset Value (Hex)
CorrMaxPos2_M CorrMaxPos1_M
0152 0151
10-8 7-0
---
PosShift_M - Shift After History Checking
Type: MultiBytes - R Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
PosShift2_M PosShift1_M
0154 0153
11-8 7-0
---
WinJump_M - Window Jump
Type: MultiBytes - R Word Length: 11 Byte Name Address (Hex) Bit Map Reset Value (Hex)
WinJump2_M WinJump1_M
0156 0155
10-8 7-0
---
NCOInc_M - NCO Increment The register provides the current NCO increment. The value is in 2's complement with a resolution of 5.703 Hz per LSB. This corresponds to a maximum control range of 216 * 5.703 Hz= 373.75 kHz ( 156 ppm @ 2.4 GHz).
Type: MultiBytes - R Word Length: 17 Byte Name Address (Hex) Bit Map Reset Value (Hex)
NCOInc3_M NCOInc2_M NCOInc1_M
0162 0161 0160
16 15-8 7-0
----
59/117
STA400A
FfEst_M - Actual Fine Frequency Value The register provides the current value of the fine frequency contribution to the NCO increment. The value is in 2's complement with a resolution of 5.703 Hz per LSB.
Type: MultiBytes - R Word Length: 17 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FfEst3_M FfEst2_M FfEst1_M
0172 0171 0170
16 15-8 7-0
----
MctlEn_M - MCM Demodulator Control MCM Control is enabled if his register is set to `1', disabled if set to `0'. The reset value enables this block.
Type: SingleByte - R/W Word Length: 1 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MctlEn_M
0180
0
00
MctlMask_M - MCM Demodulator Control Mask This register is a mask vector for internal state transitions and output control signals of MCM Control. The output signals are masked out, i.e. set to logic 0, when the corresponding output mask bit (bits 0,1 or 2) is set to 0. By default the outputs are not masked. If transition mask 2 (bit 5) is set to 0, signal full_avg_len of the MCM CF Averager is taken as is, otherwise it is internally forced to 1. If transition mask 1 (bit 4) is set to 0, the transition from state NO_UPDATE to TDM_LOCK of MCM Control is disabled. By default it is enabled. If transition mask 0 (bit 3) is set to 0, the transition from state NO_UPDATE to FS_LOCK of MCM Control is disabled. By default it is enabled. Setting bits 3 and 4 to `0' means that after entering the state NO_UPDATE this state is not left except when forced by a block disable (reg. 0x180 set to 0) or an external initialization (reg 0x182 set to 1).
Type: SingleByte - R/W Word Length: 6 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MctlMask_M
0181
5-0
1F
b5: b4: b3: b2: b1: b0:
full_avg_len tdm_lock fs_lock timeout_disa fc_noup fs_init
60/117
STA400A
MctlInit_M - MCM Demodulator Control Initialization Trigger Setting this register to 1 will trigger an intialization of MCM Control when not already in state IDLE (then no action would occur). This action also triggers an initialization of MCM Frame Sync and MCM Coarse Frequency.
Type: SingleByte - R/W Word Length: 1 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MctlInit_M
0182
0
00
TdmCntTh_M - Number of TDM Frames in Lock The register value corresponds to the number of subsequent TDM frames which have to be in lock before state NO_UPDATE is entered.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TdmCntTh_M
0183
7-0
18
MctlState_M - MCM Demodulator Control Status This register displays the internal state of MCM Control.
Type: SingleByte - R Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MctlState_M
0184
1-0
--
b1-b0:
00 -> Status=IDLE 01 -> Status=FS_LOCK 10 -> Status=TDM_LOCK 11 -> Status=NO_UPDATE
MeanAbs_M - MCM Demodulator Output Symbols Mean The register provides the mean of the amplitude of real and imaginary part of the MCM output symbols. The value range is from 0 to 255 =0xFF. The absolute value is in multiples of 1/256.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MeanAbs_M
0190
7-0
--
ClipRate_M - MCM Demodulator Output Clip Rate The register provides the clipping rate of the MCM output. The value range is from 0 to 0xFF (255). The clipping rate is in multiples of 1/256, i.e. 0xFF corresponds to full clipping, 0x80 to 50% clipping rate.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
ClipRate_M
0191
7-0
--
61/117
STA400A
OivlLenAMSSFail_M - Observation Interval Length This register sets the length of observation interval of the register "OivlAMSSFail" (Addr: 0x0144/45). T ivl O ivlLen = ---------- ; T MF
Type: MultiBytes - R/W Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MCM Frame length: TMF=7,2 msec
OivlLenAMSSFail2_M OivlLenAMSSFail1_M
0196 0195
11-8 7-0
0F 8B
b11-b0:
0x086 -> Interval (Tivl) = 1.0 sec 0x2B6 -> Interval (Tivl) = 5.0 sec 0x56C -> Interval (Tivl) = 10.0 sec 0x823 -> Interval (Tivl) = 15.0 sec 0xAD9 -> Interval (Tivl) = 20.0 sec 0xFFF -> Interval (Tivl) = 29.5 sec
WinJpLimit_M - Maximum Allowed Window Jump
jp_limit = TJP/TS ; Sample Frequency fS=5.98 MHz ; TS=0.167 sec
Type: MultiBytes - R/W Word Length: 11 Byte Name Address (Hex) Bit Map Reset Value (Hex)
WinJpLimit2_M WinJpLimit1_M
0198 0197
10-8 7-0
00 03
b10-b0:
0x003 -> Jump (Tjp) = 0.5 usec 0x01E -> Jump (Tjp) = 5.0 usec 0x03C -> Jump (Tjp) = 10.0 usec 0x05A -> Jump (Tjp) = 15.0 usec 0x078 -> Jump (Tjp) = 20.0 usec 0x168 -> Jump (Tjp) = 60.0 usec
JpLimitEvt_M - Jump Limit Events Counter
Type: SingleByte - PR Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
JpLimitEvt_M
019A
7-0
00
62/117
STA400A
WinJpNoLimit_M - Actual Requested Window Jump w/o Limit Actual requesteted jump of window without limit function. (See table of register adr 0x097/98).
Type: MultiBytes - R/W Word Length: 11 Byte Name Address (Hex) Bit Map Reset Value (Hex)
WinJpNoLimit2_M WinJpNoLimit1_M
019C 019B
10-8 7-0
00 00
IQGDataOvf_M - IQGEN LPF Overflow Counter Event counter of overflow bit of halfband filter in IQ generator
Type: SingleByte - PR Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
IQGDataOvf_M
01B0
7-0
00
NCODataOvf_M - NCO Overflow Counter Event counter of overflow bit of NCO
Type: SingleByte - PR Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
NCODataOvf_M
01B2
7-0
00
LPFDataOvf_M - LPF Overflow Counter Event counter of `ored' overflow bits of halfband filters in the Low Pass Filterf
Type: SingleByte - PR Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
LPFDataOvf_M
01B4
7-0
00
IrqMask_M - MCM Demodulator Interrupt Mask If the mask bits are set the corresponding interrupt is enabled, i.e. if the Irq_Status_M bit is set an external interupt is generated.
Type: SingleByte - INT Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
IrqMask_M
01C0
1-0
00
b1 : b0 :
frequency unlock frame sync unlock
63/117
STA400A
IrqStatus_M - MCM Demodulator Interrupt Status Bit 0 is set if the Frequency Control is enabled (cf. bit 6 of Enable_M) and the frequency lock indicator has changed from LOCK to NO LOCK (cf. bit 9 of status_M). This bit is set if the Frame Sync is enabled (cf. bit 3 of Enable_M) and the it's state has changed from SYNC to HUNT (cf. bit 3-2 of Status_M).
Type: SingleByte - INT Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
IrqStatus_M
01C1
1-0
00
b1 : b0 :
frequency unlock frame sync unlock
2.4 TDM (Section 1) TdmEnable_S - Satellite TDM Decoding Block Enable
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TdmEnable_S
0200
7-0
FF
b7 : b6 : b5 : b4 : b3 : b2 : b1 : b0 :
sat2_tfm_en sat2_td_en sat2_qmg_en sat2_ts_en sat1_tfm_en sat1_td_en sat1_qmg_en sat1_ts_en
enable sub-block satellite two TDM FIFO management enable sub-block satellite two TDM de-scrambling enable sub-block satellite two QPSK metric generation enable sub-block satellite two TDM synchronization enable sub-block satellite one TDM FIFO management enable sub-block satellite one TDM de-scrambling enable sub-block satellite one QPSK metric generation enable sub-block satellite one TDM synchronization
TdmSync_S1 - Satellite One TDM Decoding Synchronization Data Control T
Type: SingleByte - R/W Word Length: 5 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TdmSync_S1
0204
4-0
10
b4 : b3 : b2 : b1 : b0 :
fsm_fallback invert_data_out invert_data_in iq_swap_data_out iq_swap_data_in
64/117
STA400A
MfpLength_S1 - Sat1 TDM Decoding Extended MFP Detection Window Length Once the MFP is found the subsequent appearance is scanned within this symmetric window around the MFP's predicted position on the soft-symbol stream.
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpLength_S1
0205
3-0
0F
MfpThr_S1 - Sat1 TDM Decoding Extended MFP Detection Threshold Threshold of the extended MFP correlation determining extended MFP detection if reached or exceeded.
Type: SingleByte - R/W Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpThr_S1
0206
6-0
44
SyncLength_S1 - Sat1 TDM Decoding Synchronization Window Length Number of (predicted) subsequent extended MFP positions which are evaluated to determine the status of the MFP synchronization.
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
SyncLength_S1
0207
3-0
03
PreSyncThr_S1 - Sat1 TDM Decoding Pre-Synchronization Lost Threshold Number of undetected extended MFP's within the TDM decoding synchronization window, forcing the TDM synchronization to reenter the initial synchronization procedure searching the extended MFP on the entire soft-symbol stream. . Value 0x00 disables loss of lock.
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
PreSyncThr_S1
0208
3-0
02
SyncThr_S1 - Sat1 TDM Decoding Synchronization Lost Threshold Number of subsequent undetected extended MFP's while being sychronized, forcing the TDM synchronization to reenter the initial synchronization procedure searching the extended MFP on the entire soft-symbol stream. (Long range drop-out condition).
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
SyncThr_S1
0209
3-0
0B
65/117
STA400A
FspThr_S1 - Sat1 TDM Decoding FSP Invalid Threshold Threshold of the FSP correlation determining an invalid FSP detection if not exceeded.
Type: SingleByte - R/W Word Length: 6 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FspThr_S1
020A
5-0
14
MetricCtrl_S1 - Satellite One TDM Decoding QPSK Metric Generation Data Control Enables swap of data I- and Q-component and QPSK-map inversion if the corresponding bit is set. Determines the threshold of the Soft Decision Slicer and the applied data output format.
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MetricCtrl_S1
020B
3-0
00
b3 : b2 : b1 : b0 :
mgen_map_inv mgen_format mgen_lim_thold mgen_iq_swap_data_in 0 = Two's complement; 0-> Threshold = (64)dec; 1= Offset binary 1-> Threshold = (80)dec
Scrambler_S1 - Satellite One TDM Decoding Scrambler Polinomial
Type: MultiBytes - R/W Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Scrambler2_S1 Scrambler1_S1
020D 020C
11-8 7-0
08 05
TdmSync_S2 - Satellite Two TDM Decoding Synchronization Data Control
Type: SingleByte - R/W Word Length: 5 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TdmSync_S2
0212
4-0
10
b4 : b3 : b2 : b1 : b0 :
fsm_fallback invert_data_out invert_data_in iq_swap_data_out iq_swap_data_in
66/117
STA400A
MfpLength_S2 - Sat2 TDM Decoding Extended MFP Detection Window Length Once the MFP is found the subsequent appearance is scanned within this symmetric window around the MFP's predicted position on the soft-symbol stream.
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpLength_S2
0213
3-0
0F
MfpThr_S2 - Sat2 TDM Decoding Extended MFP Detection Threshold Threshold of the extended MFP correlation determining extended MFP detection if reached or exceeded.
Type: SingleByte - R/W Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpThr_S2
0214
6-0
44
SyncLength_S2 - Sat2 TDM Decoding Synchronization Window Length Number of (predicted) subsequent extended MFP positions which are evaluated to determine the status of the MFP synchronization.
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
SyncLength_S2
0215
3-0
03
PreSyncThr_S2 - Sat2 TDM Decoding Pre-Synchronization Lost Threshold Number of undetected extended MFP's within the TDM decoding synchronization window, forcing the TDM synchronization to reenter the initial synchronization procedure searching the extended MFP on the entire soft-symbol stream. . Value 0x00 disables loss of lock.
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
PreSyncThr_S2
0216
3-0
02
SyncThr_S2 - Sat2 TDM Decoding Synchronization Lost Threshold Number of subsequent undetected extended MFP's while being sychronized, forcing the TDM synchronization to reenter the initial synchronization procedure searching the extended MFP on the entire soft-symbol stream. (Long range drop-out condition).
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
SyncThr_S2
0217
3-0
0B
67/117
STA400A
FspThr_S2 - Sat2 TDM Decoding FSP Invalid Threshold Threshold of the FSP correlation determining an invalid FSP detection if not exceeded.
Type: SingleByte - R/W Word Length: 6 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FspThr_S2
0218
5-0
14
MetricCtrl_S2 - Satellite One TDM Decoding QPSK Metric Generation Data Control Enables swap of data I- and Q-component and QPSK-map inversion if the corresponding bit is set. Determines the threshold of the Soft Decision Slicer and the applied data output format. b3 : b2 : b1 : b0 : mgen_map_inv mgen_format mgen_lim_thold mgen_iq_swap_data_in 0 = Two's complement; 1= Offset binary 0-> Threshold = (64)dec; 1-> Threshold = (80)dec
Scrambler_S2 - Satellite Two TDM Decoding Scrambler Polinomial
Type: MultiBytes - R/W Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Scrambler2_S2 Scrambler1_S2
021B 021A
11-8 7-0
08 05
MfpLock_S1 - Satellite One TDM Decoding Status
Type: SingleByte - R Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpLock_S1
021D
6-0
--
b6-b5 : tdm_sync b4-b3 : tdm_dropout_align b2-b1 : tdm_sync_status b0 : tdm_lock
00= IDLE 01= XMFP HUNT 00= IDLE 01= SHORT 00= IDLE/FLUSH 01= PRESYNC 0= UNLOCK;
10= FSP RESYNC 11= XMFP RESYNC 10= MEDIUM 11= LONG 10= SYNC 10= SYNC 1= LOCK
MfpLost_S1 - Satellite One TDM Decoding Extended MFP Counter Number of extended MFP's not found within the synchronization window whilest presynchronized (range from 0 to the value loaded into the register PreSyncThr_S1, addr:0x0208) or subsequent not found whilest synchronized (range from 0 to the value loaded into the register SyncThr_S1, addr:0x0209).
Type: SingleByte - R Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpLost_S1
021E
3-0
--
68/117
STA400A
MfpW_re_S1 - Satellite One TDM Decoding Extended MFP Correlation Weight, Real Part Result of the latest extended MFP real part correlation.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpW_re_S1
0220
7-0
--
MfpW_im_S1 - Satellite One TDM Decoding Extended MFP Correlation Weight, Imaginary Part Result of the latest extended MFP imaginary part correlation.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpW_im_S1
0221
7-0
--
FspW_re_S1 - Satellite One TDM Decoding FSP Correlation Weight, Real Part Result of the latest FSP real part correlation.
Type: SingleByte - R Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FspW_re_S1
0222
6-0
--
MspW_im_S1 - Satellite One TDM Decoding FSP Correlation Weight, Imaginary Part Result of the latest FSP imaginary part correlation.
Type: SingleByte - R Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FspW_im_S1
0223
6-0
--
FspPhase_S1 - Satellite One TDM Decoding Phase
Type: SingleByte - R Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FspPhase_S1
0224
1-0
--
b1-b0 :
00= 0 01= 270
10= 90 11= 180
MfpLock_S2 - Satellite Two TDM Decoding Status
Type: SingleByte - R Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpLock_S2
0225
6-0
--
69/117
STA400A
b6-b5 : b4-b3 : b2-b1 : b0 : tdm_sync tdm_dropout_align tdm_sync_status tdm_lock 00= IDLE 00= IDLE10= FSP RESYNC 01= XMFP HUNT11= XMFP RESYNC 10= MEDIUM 01= SHORT11= LONG 00= IDLE/FLUSH10= SYNC 01= PRESYNC11= UNLOCK 0= UNLOCK; 1= LOCK
MfpLost_S2 - Satellite Two TDM Decoding Extended MFP Counter Number of extended MFP's not found within the synchronization window whilest presynchronized (range from 0 to the value loaded into the register PreSyncThr_S2, addr:0x0216) or subsequent not found whilest synchronized (range from 0 to the value loaded into the register SyncThr_S2, addr:0x0217).
Type: SingleByte - R Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpLost_S2
0226
3-0
--
MfpW_re_S2 - Satellite Two TDM Decoding Extended MFP Correlation Weight, Real Part Result of the latest extended MFP real part correlation.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpW_re_S2
0228
7-0
--
MfpW_im_S2 - Satellite Two TDM Decoding Extended MFP Correlation Weight, Imaginary Part Result of the latest extended MFP imaginary part correlation.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpW_im_S2
0229
7-0
--
FspW_re_S2 - Satellite Two TDM Decoding FSP Correlation Weight, Real Part Result of the latest FSP real part correlation.
Type: SingleByte - R Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FspW_re_S2
022A
6-0
--
70/117
STA400A
MspW_im_S2 - Satellite Two TDM Decoding FSP Correlation Weight, Imaginary Part Result of the latest FSP imaginary part correlation.
Type: SingleByte - R Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FspW_im_S2
022B
6-0
--
FspPhase_S2 - Satellite Two TDM Decoding Phase
Type: SingleByte - R Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FspPhase_S2
022C
1-0
--
b1-b0 : 00= 0 01= 270
10= 90 11= 180
TdmEnable_T - Terrestrial TDM Decoding Block Enable
Type: SingleByte - R/W Word Length: 5 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TdmEnable_T
022D
4-0
1F
b4 : b3 : b2 : b1 : b0 :
terr_tf_en terr_twc_en terr_td_en terr_tt_en terr_ts_en
enable sub-block terrestrial TDM FIFO enable sub-block terrestrial TDM write controller enable sub-block terrestrial TDM de-scrambling enable sub-block terrestrial TDM data formating enable sub-block terrestrial TDM synchronization
MfpLength_T - Terrestrial TDM Decoding MFP Detection Window Length Once the MFP is found, the subsequent appearance is scanned within this symmetric window around the MFP perdicted position on the solf-symbol stream.
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpLength_T
022E
3-0
07
MfpThrPreSync_T - Terrestrial TDM Decoding MFP Detection Threshold, Pre-Synchronization Threshold of the MFP correlation determining MFP detection to achieve pre-synchronization if reached or exceeded.
Type: SingleByte - R/W Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpThrPreSync_T
022F
7-0
2C
71/117
STA400A
MfpThrSync_T - Terrestrial TDM Decoding MFP Detection Threshold, Synchronization Threshold of the MFP correlation determining MFP detection to achieve synchronization if reached or exceeded.
Type: SingleByte - R/W Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpThrSync_T
0230
7-0
28
SyncLength_T - Terrestrial TDM Synchronization Window Length Number of (predicted) subsequent MFP positions, which are evaluated to determine the status of the MFP synchronization.
Type: SingleByte - R/W Word Length: 5 Byte Name Address (Hex) Bit Map Reset Value (Hex)
SyncLength_T
0231
4-0
03
SyncThr_T - Terrestrial TDM Synchronization Found Threshold Number of detected MFPs within the TDM decoding synchronization window to achieve synchronization. If this number is not reached or exceeded, the TDM synchronization reenters the initial synchronization procedure searching the MFP on the entire soft-symbol stream.
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
SyncThr_T
0232
3-0
02
SyncLost_T - Terrestrial TDM Synchronization Lost Threshold Number of subsequent undetected MFP's while being synchronized, forcing the TDM synchronization to reenter the initial synchronization procedure searching the MFP on the entire soft-symbol stream.
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
SyncLost_T
0233
3-0
0B
Scrambler_T - Terrestrial TDM Decoding Scrambler Polinomial
Type: MultiBytes - R/W Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Scrambler2_T Scrambler1_T
0235 0234
11-8 7-0
08 05
DataFormat_T - Terrestrial TDM Decoding Data Formatting Enables swap of data I- and Q-component, MCM-map inversion and limiter if the corresponding bit is set. De72/117
STA400A
termines the applied data output format. If the limiter is enabled, data with MSB = '1' is replaced by "all-ones", data with MSB = '0' is shifted left logically.
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
DataFormat_T
0236
3-0
00
b3 : b2 : b1 : b0 :
map_inv format limit iq_swap 0= Two's complement; 1= Offset binary
TdmStatus_T - Terrestrial TDM Decoding Status
Type: SingleByte - R Word Length: 3 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TdmStatus_T
0237
2-0
--
b2-b1 : tdm_sync_status b0 : tdm_lock
00= IDLE 01= PRESYNC 0 = UNLOCK
10= SYNC 11= UNLOCK 1= LOCK
MfpLost_T - Terrestrial TDM Decoding MFP Correlation Lost Number of MFPs found within the synchronization window whilest pre-synchronized (range from 0 to the value loaded into the register SyncLost_T, addr:0x0233).
Type: SingleByte - R Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpLost_T
0239
3-0
--
MfpW_re_T - Terrestrial TDM Decoding MFP Correlation Weight, Real Part Result of the latest MFP real part correlation.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpW_re_T
023A
7-0
--
MfpW_im_T - Terrestrial TDM Decoding MFP Correlation Weight, Imaginary Part Result of the latest MFP imaginary part correlation.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpW_im_T
023B
7-0
--
73/117
STA400A
TdmPhase_T - Terrestrial TDM Decoding Phase
Type: SingleByte - R Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TdmPhase_T
023C
1-0
--
b1-b0 : 00= 0 1= 270
10= 90 11= 180
TdmSyncCtrl_T - Terrestrial TDM Decoding Synchronization Control
Type: SingleByte - R/W Word Length: 1 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TdmSyncCtrl_T
023F
0
01
b0 :
fsm_fallback_en
SwfgEnable_S - Satellite Weighting Factor Generation Block Enable
Type: SingleByte - R/W Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Swfg_Enable_S
0240
7-0
FF
b7:
swfg2_fsp_invalid_en
enable satellite two weighting factor generation FSP invalid evalutation.Weights are forced to '0' if this bit is set to '1' and the TDM decode block detects an invalid FSP.
b6:
swfg2_cycle_slip_en
enable satellite two weighting factor generation cycle slip evalutation. Weights are forced to '0' if this bit is set to '1' and the TDM decode block detects a cycle slip.
b5: b4: b3:
swfg2_fifo_en swfg2_comp_en swfg1_fsp_invalid_en
enable sub-block satellite two weighting factor FIFO enable sub-block satellite two weighting factor calculation enable satellite one weighting factor generation FSP invalid evalutation.Weights are forced to '0' if this bit is set to '1' and the TDM decode block detects an invalid FSP.
b2:
swfg1_cycle_slip_en
enable satellite one weighting factor generation cycle slip evalutation. Weights are forced to '0' if this bit is set to '1' and the TDM decode block detects a cycle slip.
b1: b0:
swfg1_fifo_en swfg1_comp_en
enable sub-block satellite one weighting factor FIFO enable sub-block satellite one weighting factor calculation
74/117
STA400A
SwfgStatus_S - Satellite Weighting Factor Generation Status
Type: SingleByte - R Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
SwfgStatus_S
0241
1-0
--
b1: b0:
swfg2_status swfg1_status
Sat2 weighting factor generation status Sat1 weighting factor generation status
0=idle1=operational 0=idle1=operational
Prc_En - TDM PRC Interface Block Enable
Type: SingleByte - R/W Word Length: 3 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Prc_En
0250
2-0
00
b2-b1: b0:
prc source block_en
00= Satellite1 01= Satellite2 0= Disabled
10= Terrestrial 11= RFU 1= Enabled
Prc_Num - PRC Number This register sets the PRC number in the range from 1 to 258.
Type: MultiByte2 - R/W Word Length: 9 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Prc_Num2 Prc_Num1
0252 0251
8 7-0
00 00
DescDataEn - Signal Selection for Multiplexer After Descrambler Select signals for multiplexer after tdm descrambling (0: original data; 1: register contents)
Type: SingleByte - R/W Word Length: 5 Byte Name Address (Hex) Bit Map Reset Value (Hex)
DescDataEn
0260
4-0
00
b4: b3: b2: b1: b0:
swfg2_data_out_en swfg1_data_out_en sat2_data_out_en sat1_data_out_en terr_data_out_en
75/117
STA400A
DescData_re_T - Terrestrial Test Real Data
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
DescData_re_T
0261
7-0
00
DescData_im_T - Terrestrial Test Imaginary Data
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
DescData_im_T
0262
7-0
00
DescData_re_S1 - Sat1 Test Real Data
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
DescData_re_S1
0263
3-0
00
DescData_im_S1 - Sat1 Test Imaginary Data
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
DescData_im_S1
0264
3-0
00
DescData_re_S2 - Sat2 Test Real Data
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
DescData_re_S2
0265
3-0
00
DescData_im_S2 - Sat2 Test Imaginary Data
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
DescData_im_S2
0266
3-0
00
DescData_S1wfg - Sat1 Weighting Test Data
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
DescData_S1wfg
0267
3-0
00
76/117
STA400A
DescData_S2wfg - Sat2 Weighting Test Data
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
DescData_S2wfg
0268
3-0
00
TpmEnable_S - Satellite TDM Preamble Monitor Enable
Type: SingleByte - R/W Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmEnable_S
0280
1-0
00
b1: b0:
tpm2_en tpm1_en
enable sub-block satellite two TDM preamble monitor enable sub-block satellite one TDM preamble monitor
TpmDataFormat_S1 - Sat1 TDM Preamble Monitor Input Data Format Control swap of I- and Q-component and data inversion for input data. If one bit is set to '1' it's corresponding functionality is invoked.
Type: SingleByte - R/W Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmDataFormat_S1
0281
1-0
00
b1: b0:
tpm_invert_data_in tpm_iq_swap_data_in
TpmMfpThr_S1 - Sat1 TDM Preamble Monitor MFP Detection Threshold Threshold of the MFP correlation determining MFP detection if reached or exceeded.
Type: SingleByte - R/W Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmMfpThr_S1
0282
6-0
28
TpmFspThr_S1 - Sat1 TDM Preamble Monitor FSP Detection Threshold Threshold of the FSP correlation determining FSP detection if reached or exceeded.
Type: SingleByte - R/W Word Length: 6 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmFspThr_S1
0283
5-0
14
TpmDataFormat_S2 - Sat2 TDM Preamble Monitor Input Data Format Control swap of I- and Q-component and data inversion for input data. If one bit is set to '1' it's corresponding
77/117
STA400A
functionality is invoked.
Type: SingleByte - R/W Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmDataFormat_S2
0284
1-0
00
b1: b0:
tpm_invert_data_in tpm_iq_swap_data_in
TpmMfpThr_S2 - Sat2 TDM Preamble Monitor MFP Detection Threshold Threshold of the MFP correlation determining MFP detection if reached or exceeded.
Type: SingleByte - R/W Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmMfpThr_S2
0285
6-0
28
TpmFspThr_S2 - Sat2 TDM Preamble Monitor FSP Detection Threshold Threshold of the FSP correlation determining FSP detection if reached or exceeded.
Type: SingleByte - R/W Word Length: 6 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmFspThr_S2
0286
5-0
14
TpmMfpW_re_S1 - Sat1 TDM Preamble Monitor MFP Correlation Weight, Real Part Result of the latest MFP real part correlation.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmMfpW_re_S1
0290
7-0
--
TpmMfpW_im_S1 - Sat1 TDM Preamble Monitor MFP Correlation Weight, Imaginary Part Result of the latest MFP imaginary part correlation.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmMfpW_im_S1
0291
7-0
--
TpmMfpSymSlip_S1 - Sat1 TDM Preamble Monitor MFP Symbol Slip
Type: MultiBytes - R Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmMfpSymSlip2_S1 TpmMfpSymSlip1_S1
0293 0292
11-8 7-0
---
78/117
STA400A
TpmFspW_re_S1 - Sat1 TDM Preamble Monitor FSP Correlation Weight, Real Part Result of the latest FSP real part correlation.
Type: SingleByte - R Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmFspW_re_S1
0294
6-0
--
TpmFspW_im_S1 - Sat1 TDM Preamble Monitor FSP Correlation Weight, Imaginary Part Result of the latest FSP imaginary part correlation.
Type: SingleByte - R Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmFspW_im_S1
0295
6-0
--
TpmFspPosSlip_S1 - Sat1 TDM Preamble Monitor FSP Position Slip
Type: MultiBytes - R Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmFspPosSlip2_S1 TpmFspPosSlip1_S1
0297 0296
11-8 7-0
---
TpmFspTdmPhase_S1 - Sat1 TDM Preamble Monitor FSP Phase Phase of the TDM soft-symbol stream basing the result on the lastest FSP correlation.
Type: SingleByte - R Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmFspTdmPhase_S1
0298
1-0
--
b1-b0 :
00= 010= 90 01= 27011= 180
TpmPrDetect_S1 - Sat1 TDM Preamble Monitor Preamble Detection Preamble detection based on the result of the latest preamble correlation.
Type: SingleByte - R Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmPrDetect_S1
0299
1-0
--
TpmFspCySlipCnt_S1 - Sat1 TDM Preamble Monitor FSP Cycle Slip Counter Cycle slip counter based on FSP evaluation whilst FSP detected for the latest TDM frame.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmFspCySlipCnt_S1
029A
7-0
--
79/117
STA400A
TpmFspPoSlipCnt_S1 - Sat1 TDM Preamble Monitor FSP Position Slip Counter FSP position slip counter based on the distorsion of the detected FSPs to their expected position with respect to the lastest detected MFP.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmFspPoSlipCnt_S1
029B
7-0
--
TpmMfpW_re_S2 - Sat2 TDM Preamble Monitor MFP Correlation Weight, Real Part Result of the latest MFP real part correlation.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmMfpW_re_S2
02A0
7-0
--
TpmMfpW_im_S2 - Sat2 TDM Preamble Monitor MFP Correlation Weight, Imaginary Part Result of the latest MFP imaginary part correlation.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmMfpW_im_S2
02A1
7-0
--
TpmMfpSymSlip_S2 - Sat2 TDM Preamble Monitor MFP Symbol Slip
Type: MultiBytes - R Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmMfpSymSlip2_S2 TpmMfpSymSlip1_S2
02A3 02A2
11-8 7-0
---
TpmFspW_re_S2- Sat2 TDM Preamble Monitor FSP Correlation Weight, Real Part Result of the latest FSP real part correlation.
Type: SingleByte - R Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmFspW_re_S2
02A4
6-0
--
TpmFspW_im_S2- Sat2 TDM Preamble Monitor FSP Correlation Weight, Imaginary Part Result of the latest FSP imaginary part correlation.
Type: SingleByte - R Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmFspW_im_S2
02A5
6-0
--
80/117
STA400A
TpmFspPosSlip_S2 - Sat2 TDM Preamble Monitor FSP Position Slip
Type: MultiBytes - R Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmFspPosSlip2_S2 TpmFspPosSlip1_S2
02A7 02A6
11-8 7-0
---
TpmFspTdmPhase_S2 - Sat2 TDM Preamble Monitor FSP Phase Phase of the TDM soft-symbol stream basing the result on the lastest FSP correlation.
Type: SingleByte - R Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmFspTdmPhase_S2
02A8
1-0
--
b1-b0 : 00= 0 01= 270
10= 90 11= 180
TpmPrDetect_S2 - Sat2 TDM Preamble Monitor Preamble Detection Preamble detection based on the result of the latest preamble correlation.
Type: SingleByte - R Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmPrDetect_S2
02A9
1-0
--
TpmFspCySlipCnt_S2 - Sat2 TDM Preamble Monitor FSP Cycle Slip Counter Cycle slip counter based on FSP evaluation whilst FSP detected for the latest TDM frame.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmFspCySlipCnt_S2
02AA
7-0
--
TpmFspPoSlipCnt_S2 - Sat2 TDM Preamble Monitor FSP Position Slip Counter FSP position slip counter based on the distorsion of the detected FSPs to their expected position with respect to the lastest detected MFP.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmFspPoSlipCnt_S2
02AB
7-0
--
81/117
STA400A
TpmSySlip_S1 - Sat1 TDM Decoding Symbol Slip Extended MFP detection based symbol slip.
Type: MultiBytes - R Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmSySlip2_S1 TpmSySlip1_S1
02B1 02B0
11-8 7-0
---
TpmSySlip_S2 - Sat2 TDM Decoding Symbol Slip Extended MFP detection based symbol slip.
Type: MultiBytes - R Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmSySlip2_S2 TpmSySlip1_S2
02B3 02B2
11-8 7-0
---
TpmSySlip_T - Terrestrial TDM Decoding Symbol Slip
Type: MultiBytes - R Word Length: 10 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TpmSySlip2_T TpmSySlip1_T
02B5 02B4
9-8 7-0
---
FspStartWinLen_S1 - Sat1 TDM Decoding FSP Detection Start Window Length Entering a short range dropout condition, the FSP is searched within a symetrical (start) window around the nominal FSP position.
Type: SingleByte - R/W Word Length: 3 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FspStartWinLen_S1
02C0
2-0
02
FspHuntWinInc_S1 - Sat1 TDM Decoding FSP Detection Hunt Window Increment Entering a medium range dropout condition, the FSP is searched within a symetrical window around the nominal FSP position. This window is increased on FSP period bases with an increment of inc/8 symbols begining with the start window length.
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FspHuntWinInc_S1
02C1
3-0
03
82/117
STA400A
FspShDropOutLen_S1 - Sat1 TDM Decoding FSP Short DropOut Length Number of subsequent undetected FSPs determining the upper limit of a short range dropout condition.
Type: SingleByte - R/W Word Length: 5 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FspShDropOutLen_S1
02C2
4-0
0F
FspSecuAlignThr_S1 - Sat1 TDM Decoding FSP Secure Alignment Threshold Number of subsequent detected FSPs with nominal FSP period length determining secure alignment to the TDM soft-symbol stream within a medium range dropout condition.
Type: SingleByte - R/W Word Length: 3 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FspSecuAlignThr_S1
02C3
2-0
03
FspStartWinLen_S2 - Sat2 TDM Decoding FSP Detection Start Window Length Entering a short range dropout condition, the FSP is searched within a symetrical (start) window around the nominal FSP position.
Type: SingleByte - R/W Word Length: 3 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FspStartWinLen_S2
02C8
2-0
02
FspHuntWinInc_S2 - Sat2 TDM Decoding FSP Detection Hunt Window Increment Entering a medium range dropout condition, the FSP is searched within a symetrical window around the nominal FSP position. This window is increased on FSP period bases with an increment of inc/8 symbols begining with the start window length.
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FspHuntWinInc_S2
02C9
3-0
03
FspShDropOutLen_S2 - Sat2 TDM Decoding FSP Short DropOut Length Number of subsequent undetected FSPs determining the upper limit of a short range dropout condition.
Type: SingleByte - R/W Word Length: 5 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FspShDropOutLen_S2
02CA
4-0
0F
FspSecuAlignThr_S2 - Sat2 TDM Decoding FSP Secure Alignment Threshold Number of subsequent detected FSPs with nominal FSP period length determining secure alignment to the
83/117
STA400A
TDM soft-symbol stream within a medium range dropout condition.
Type: SingleByte - R/W Word Length: 3 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FspSecuAlignThr_S2
02CB
2-0
03
2.5 FEC Control_F - FEC Control Register The control flags enable the corresponding operation if set, otherwise the operation is disabled. The flags fec_en and fec_prep enable the operation of the FEC and FEC Preprocessing. Weighting of the two satellite data streams is performed only when wgt_en=1, otherwise the data from the memory are not weighted. The flags terr_format and sat_format determine the Viterbi input data format for both terrestrial and satellite data streams. As only one Viterbi Decoder is applied both flags have to be equal. The Viterbi flush operation is enabled at the end of a PRC packet when vd_flush_on=1.
Type: SingleByte - R/W Word Length: 6 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Control_F
0300
5-0
3F
b5 : b4 : b3 : b2 : b1 : b0 :
vd_flush_on sat_format terr_format wgt_en fec_prep_en fec_en
`0'= VD flush disabled `1'= VD flush enabled `0'= satellite data in two's complement (Viterbi input) `1'= satellite data in offset binary (Viterbi input) `0'= terrstrial data in two's complement (Viterbi input) `1'= terrestrial data in offset binary (Viterbi input) `0'= Satellite Weighting disabled `1'= Satellite Weighting enabled `0'= FEC Preprocessing disabled `1'= FEC Preprocessing enabled `0'= FEC disabled `1'= FEC enabled
Status_F - FEC Status Register The status vector comprises the status flags of the sub-modules of the FEC Processing. An inactive module is indicated by status=0, an active module by status=1
Type: SingleByte - R Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Status_F
0301
3-0
--
b3 :
FEC Preprocessing
`0'= FEC Preprocessing inactive
84/117
STA400A
`1'= FEC Preprocessing operational b2 : b1 : b0 : RS Input Control Viterbi Decoder FEC Management `0'= RS Input Control inactive `1'= RS Input Control operational `0'= VD inactive `1'= VD operational `0'= FEC Management inactive `1'= FEC Management operational ErrorCtrl_F - FEC Error Register
Type: SingleByte - R/W Word Length: 6 Byte Name Address (Hex) Bit Map Reset Value (Hex)
ErrorCtrl_F
0302
5-0
01
b5-b0 : 0x00 0x01 0x02 0x03 ... 0x32
-> -> -> -> ->
Asynchronous status overwrite for each PRC proceed Update FEC error registers with TSCC1 status only Update FEC error registers with TSCC2 status only Update FEC error registers with 1st PRC packet after TSCCs Update FEC error registers with 48th PRC packet after TSCCs Undefined
x33-0x3F ->
InitState_F - Convolutional Decoder Initial State Control Register Initial state of convolutional decoder after training sequence, which corresponds to the reverse of the last 6 bits of the PRC preamble 1D(hex)=00011101 -> 101110 = 2E(hex)=46(dec).
Type: SingleByte - R/W Word Length: 6 Byte Name Address (Hex) Bit Map Reset Value (Hex)
InitState_F
0307
5-0
2E
InitLfsr_F - Viterbi Decoder LFSR Initial State
Type: MultiBytes - R/W Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
InitLfsr2_F InitLfsr1_F
0309 0308
11-8 7-0
0C CC
85/117
STA400A
InitTerm_F - Termination Sequence After Flush Operation Sequence after flush operation for termination of Viterbi decoder. The upper 8 bits have to be the PRC preamble 1D(hex) in ascending order (b12..b19).
Type: MultiBytes - R/W Word Length: 20 Byte Name Address (Hex) Bit Map Reset Value (Hex)
InitTerm3_F InitTerm2_F InitTerm1_F
030C 030B 030A
19-16 15-8 7-0
0B 80 00
VitBerCtrl_F - Viterbi BER Measurements Control
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
VitBerCtrl_F
0310
3-0
0F
b3 : b2 : b1 : b0 :
fvd_csat_ber_mode `0'= Sat. measurment as single acquisition `1'= Sat. measurement as continuous acquisition fvd_csat_ber_en `0'= Sat. BER measurement disabled `1'= Sat BER measurement enabled fvd_terr_ber_mode `0'= Terr. measurment as single acquisition `1'= Terr. measurement as continuous acquisition fvd_terr_ber_en `0'= Terr. BER measurement disabled `1'= Terr. BER measurement enabled
TerrBer_F - Terrestrial Channel Bit Error Rate The terrestrial channel error rate states the number of channel symbol errors which where determined within one PRC packet by reencoding of the Viterbi-decoded terrestrial data stream. A new measurement is indicated by the signal terr_ber_done which is comprised in the interrupt vector (addr. 0x0350)
Type: MultiBytes - R Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TerrBer2_F TerrBer1_F
0321 0320
11-8 7-0
---
Sat1Ber_F - Satellite 1 Channel Bit Error Rate The Sat1 channel error rate states the number of channel symbol errors which where determined within one PRC packet by reencoding of the Viterbi-decoded Sat1 data stream. A new measurement is indicated by the
86/117
STA400A
signal sat1_ber_done which is comprised in the interrupt vector (addr. 0x0350)
Type: MultiBytes - R Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Sat1Ber2_F Sat1Ber1_F
0325 0324
11-8 7-0
---
Sat2Ber_F - Satellite 2 Channel Bit Error Rate The Sat2 channel error rate states the number of channel symbol errors which where determined within one PRC packet by reencoding of the Viterbi-decoded Sat2 data stream. A new measurement is indicated by the signal sat2_ber_done which is comprised in the interrupt vector (addr. 0x0350)
Type: MultiBytes - R Word Length: 12 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Sat2Ber2_F Sat2Ber1_F
0329 0328
11-8 7-0
---
ForceCorr_F - FEC Control Register This Register is used to force the correction value for PRC preamble (System value 0x1D) at RS input
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
ForceCorr_F
0330
7-0
1D
RS_Ctrl_F - RS Decoder Configuration
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
RS_Ctrl_F
0331
3-0
03
b3-b2 :
RS Error count conf
`00'= Count 16 RS Blocks (8 PRCs); `01'= Count 64 RS Blocks (32 PRCs); `10'= Count 256 RS Blocks (128 PRCs); `11'= Count 1024 RS Blocks (512 PRCs).
b1 : b0 :
terr_csat_comb force_corr_en
`1'= Enable Terrestrial-Satellite Combining `0'= Disable Terrestrial-Satellite Combining `1'= enable forced correction of PRC preamble; `0'= disable forced correction of PRC preamble
RS_Cnt_F - RS Decoder Error Count Control This register controls the RS Error Counter. After reset the counter is disabled. To start BER measurement a value must be written in this register. When written, this register generates a one clock cycle trigger signal for
87/117
STA400A
the RS Error Counter.
Type: SingleByte - WRT Word Length: 1 Byte Name Address (Hex) Bit Map Reset Value (Hex)
RS_Cnt_F
0332
0
01
b0 :
Error counter control
`0'= Continuos acquisition; `1'= Single acquisition.
RS_ByteCnt_F - RS Byte Corrected Error Counter This register is 14 bits long and is divided into two bytes. The LSB byte is named RS _ByteCnt1, the MSB byte is named RS_ByteCnt2. It cointains the number of the corrected RS bytes with unsigned format.
Type: MultiBytes - R Word Length: 14 Byte Name Address (Hex) Bit Map Reset Value (Hex)
RS_ByteCnt2_F RS_ByteCnt1_F
0336 0335
13-8 7-0
---
RS_FrameCnt_F - Corrupted RS Block Counter This register is 10 bits long and is divided into two bytes. The LSB byte is named RS _FrameCnt1, the MSB byte is named RS _FrameCnt2. It cointains the number of the corrupted RS blocks with unsigned format.
Type: MultiBytes - R Word Length: 10 Byte Name Address (Hex) Bit Map Reset Value (Hex)
RS_FrameCnt2_F RS_FrameCnt1_F
0338 0337
9-8 7-0
---
InitSeq_F - Viterbi Decoder Initialization Sequence The Viterbi decoder is initialized with the PRC preamble (hex 1D)
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
InitSeq_F
0340
7-0
1D
RS1_TerrByteErr_F - Terrestrial RS Block1 Error Register
Type: SingleByte - R Word Length: 5 Byte Name Address (Hex) Bit Map Reset Value (Hex)
RS1_TerrByteErr_F
0342
4-0
--
b4-b0 : 0x00 ->
88/117
No Errors
STA400A
0x01 -> 0x02 -> ... 0x10 -> 0x1F -> 16 byte errors corrected Uncorrectable errors 1 byte error corrected 2 byte errors corrected
RS2_TerrByteErr_F - Terrestrial RS Block2 Error Register
Type: SingleByte - R Word Length: 5 Byte Name Address (Hex) Bit Map Reset Value (Hex)
RS2_TerrByteErr_F
0343
4-0
--
b4-b0 : 0x00 -> 0x01 -> 0x02 -> ... 0x10 -> 0x1F ->
No Errors 1 byte error corrected 2 byte errors corrected 16 byte errors corrected Uncorrectable errors
RS1_SatByteErr_F - Satellite RS Block1 Error Register
Type: SingleByte - R Word Length: 5 Byte Name Address (Hex) Bit Map Reset Value (Hex)
RS1_SatByteErr_F
0344
4-0
--
b4-b0 :
0x00 -> 0x01 -> 0x02 -> ... 0x10 -> 0x1F ->
No Errors 1 byte error corrected 2 byte errors corrected 16 byte errors corrected Uncorrectable errors
RS2_SatByteErr_F - Satellite RS Block2 Error Register
Type: SingleByte - R Word Length: 5 Byte Name Address (Hex) Bit Map Reset Value (Hex)
RS2_SatByteErr_F
0345
4-0
--
b4-b0 : 0x00 -> 0x01 -> 0x02 ->
No Errors 1 byte error corrected 2 byte errors corrected
89/117
STA400A
... 0x10 -> 0x1F -> 16 byte errors corrected Uncorrectable errors
RS_Block_decis_F - Status of the Last RS Diversity Decision
Type: SingleByte - R Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
RS_Status_decis_F
0346
1-0
--
b1-b0 : 00 = Satellite Path selected for current frame 01 = Terrestrial Path selected for current frame 10 = Undefined 01 = Undefined IrqMask_F - FEC Interrupt Mask This register masks the interrupt request when a `0' is written in the relative bit.
Type: SingleByte - INT Word Length: 5 Byte Name Address (Hex) Bit Map Reset Value (Hex)
IrqMask_F
0350
4-0
00
b4 : b3 : b2 : b1 : b0 :
interrupt mask for rs_cnt_end interrupt mask for sat2_ber_done interrupt mask for sat1_ber_done interrupt mask for terr_ber_done interrupt mask for fec_irq_status
IrqStatus_F - FEC Interrupt Status This is the interrupt status vector. When a bit means that an interrupt is requested by the corresponding block. To reset a single bit, a `0' must be written into. `0x00' resets the complete vector.
Type: SingleByte - INT Word Length: 5 Byte Name Address (Hex) Bit Map Reset Value (Hex)
IrqStatus_F
0351
4-0
00
b4 : b3 : b2 : b1 : b0 :
rs_cnt_end
interrupt for new RS error count measurement
sat2_ber_done interrupt for new Sat2 BER measurement sat2_ber sat1_ber_done interrupt for new Sat1 BER measurement sat1_ber terr_ber_done fec_irq_status interrupt for new terr. BER measurement terr_ber interrupt signal from FEC Management
90/117
STA400A
2.6 IF Sampling and Control Interface AGC_CTRL1 - AGC Control Register #1 This register controls Terrestrial and satellite AGC loop gain and the sense of the TAGC and SAGC control pins.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
AGC_CTRL1
0400
7-0
88
b7: b6-b4: b3: b2-b0:
TAGCCHS TAGCBETA(2:0) SAGCCHS SAGCBETA(2:0)
Terrestrial AGC Loop Change Sign Terrestrial AGC Loop Gain. Satellite AGC Loop Change Sign Satellite AGC Loop Gain.
TAGCBETA and SAGCBETA Gain Table:
TAGCBETA/ SAGCBETA Loop Gain
000 001 010 011 100 101 110 111
2**0 = 1 2**1 = 2 2**2 = 3 2**3 = 4 2**4 = 16 2**5 = 32 2**6 = 64 Open Loop
SAGCREF - Satellite AGC Reference Level This register is 13 bits long and is divided into two bytes. The LSB byte is named SAGCREF0, the MSB byte is named SAGCREF1. It sets the signal level at the Satellite ADC input.
Type: MultiBytes - R/W Word Length: 13 Byte Name Address (Hex) Bit Map Reset Value (Hex)
SAGCREF1 SAGCREF0
0402 0401
12-8 7-0
01 90
SAGCINTG - Satellite AGC Integrator This register is connected to the 8MSB of the internal integrator of the satellite AGC loop. It gives an image of the power level at the satellite analog input. The register format is two's complement.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
SAGCINTG
0403
7-0
00
91/117
STA400A
TAGCREF - Terrestrial AGC Reference Level This register is 13 bits long and is divided into two bytes. The LSB byte is named TAGCREF0, the MSB byte is named TAGCREF1. It sets the signal level at the terrestrial ADC input.
Type: MultiBytes - R/W Word Length: 13 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TAGCREF1 TAGCREF0
0405 0404
12-8 7-0
01 90
TAGCINTG - Terrestrial AGC Integrator This register is connected to the 8MSB of the internal integrator of the terrestrial AGC loop. It gives an image of the power level at the terrestrial analog input. The register format is two's complement.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TAGCINTG
0406
7-0
00
IF_CTRL - IF Sampling Control Register This register selects the external ADC format and controls the average filter of the AGC integrator.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
IF_CTRL
0407
7-0
00
b7: b6-b2: b1 : b0:
AVG_OFF FORMAT
Internal averager circuit disable. `1'=Averager disabled; `0'=Averager enabled. Reserved for Future Use External/Internal ADC code format. `1'=Two's complement; `0'=Offset Binary. Reserved
SELTSTOUT - Internal Test Bus Selection for each Block This register selects, for each internal blocks, which signals are connected to the FTESTOUT pins. It must ve used together with the TSTMUXCTL register (addr 0x040B).
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
SELTSTOUT
040A
3-0
00
b3-b0:
TBD
TSTMUXCTL - Selection of the Internal Block for Functional Test This register selects, among 16 test buses from the internal functional blocks, the one to be connected to the FTESTOUT bus according with the table below. It must ve used together with the SELTSTOUT register (addr
92/117
STA400A
0x040A).
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TSTMUXCTL
040B
3-0
00
b3-b0:
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Reserved Reserved Reserved for Future Use Reserved for Future Use Reserved for Future Use PC Bitstream Interface #2 PC Bitstream Interface #1 FEC_RS (Reed-Solomon decoder) FEC_FPP (FEC Pre-Processing) FEC_VD TDM Reserved for Future Use Terrestrial Demodulator (MCM demodulator) Satellite Demodulator #2 (QPSK2) Satellite Demodulator #1 (QPSK1) IF Sampling
CLKDIV_CONF- Master Clock Programmable Divider This register sets the division factor (2,4 or 8) of the master clock applied to XTI/MCLK input. The divided clock is available at CLKD output (pin 56).
Type: SingleByte - R/W Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
CLKDIV_CONF
040C
1-0
03
b1- b0 : CLK_DIV
00 = MCLK/2 01 = MCLK/4 10 = MCLK/8 11 = Disabled
(CLKD frequency = 23.92MHz/2=11.96MHz) (CLKD frequency = 23.92MHz/2=11.96MHz) (CLKD frequency = 23.92MHz/2=11.96MHz) (CLKD fixed to GND)
QPSK_BER_CTRL - Satellite Demodulators BER Control This register is used in functional test mode for B.E.R. Measurement after satellite demodulation, using an external serial BER Tester. The BER measurement is on the hard decided output symbol and the relative clock available at the FTESTOUT interface (see SELTSTOUT Register description). This register controls the interface operations to synchronize the BER Tester on the demodulated satellite sym-
93/117
STA400A
bols before starting the BER computation.
Type: SingleByte - R/W Word Length: 3 Byte Name Address (Hex) Bit Map Reset Value (Hex)
QPSK_BER_CTRL
040D
2-0
00
b2: b1-b0:
IQ SWAP PHCHG
Swap between I and Q components of the received symbols Phase ambiguity correction 00 = 0 degrees 01 = 90 degrees 10 = 180 degrees 11 = 270 degrees
CONTROL - General Purpose Control Register This register controls the master clock outputs, the bidirectional buses mode to access the external memory and the BIST access mode (reserved for structural test).
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
CONTROL
0410
7-0
00
b7:
MCLKO_OFF
MCLKO output buffer disable. 0 = Buffer active; 1 = Buffer disabled (output fixed to ground).
b6:
MCLKON_OFF MCLKON output buffer disable. 0 = Buffer active; 1 = Buffer disabled (output fixed to ground).
b5:
MDQM_CTRL
External memory input/output mask polarity. 0 = High level active; 1 = Low level active.
b4-b1: b0:
Reserved IRQ_RST_CTRLReset after read on the interrupt register (IRQ1_STATUS) 0 = Disabled; 1 = Enabled.
IRQ1_MASK - Interrupt Mask Register Enable/Disable interrupts on INTR pin.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
IRQ1_MASK
0417
7-0
00
94/117
STA400A
b7: b6: b5: b4: b3: b2: b1: b0: Sat2 Lock indicator interrupt masked Sat1 Lock indicator interrupt masked MFP_CLK interrupt masked (5 msec impulse sync) MFP_CLK interrupt masked (level) IIC-bus illegal address masked TDM interrupt masked FEC interrupt masked MCM interrupt masked 0=disabled; 1=enabled. 0=disabled; 1=enabled. 0=disabled; 1=enabled. 0=disabled; 1=enabled. 0=disabled; 1=enabled. 0=disabled; 1=enabled. 0=disabled; 1=enabled. 0=disabled; 1=enabled.
Note: bit5 and bit4 cannot be used togheter, i.e. if bit5 is used the bit4 must be masked and viceversa. If both are enabled, bit4 will be sent to INTR pin. IRQ1_STATUS - Interrupt Status Register This register represents the interrupt vector when the INTR pin is activated (HIGH level active). It can be reset after read if the bit0 (IRQ_RST_CTRL) of the CONTROL register is set to `1' or a single bit can be reset directly writing `0'.
Type: SingleByte - PR Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
IRQ1_STATUS
0419
7-0
00
b7: b6: b5:
Interrupt request from Sat2 lock indicator (high active); Interrupt request from Sat1 lock indicator (high active); Interrupt request from MFP_CLK (5 msec impulse continuos sync signal); Bit5 is generated from the MFP_CLK and is a 432msec period signal with ~1.16% duty-cycle (5msec/432msec); there is no need to reset bit5 by the interrupt routine.
b4:
Interrupt request from MFP_CLK (high active). Bit4 is activated by the positive edge of the MFP_CLK and is a high level signal; the interrupt routing must reset this bit.
b3: b2: b1: b0:
Interrupt request from IIC-bus illegal address Interrupt request from TDM Interrupt request from FEC Interrupt request from MCM
(high active); (high active); (high active); (high active).
STATUS1 - CDEC Status Register This register represents the interrupt vector when the INTR pin is activated (HIGH level active). It can be reset after read if the bit0 (IRQ_RST_CTRL) of the CONTROL register is set to `1' or a single bit can be reset directly writing `0'.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
STATUS1
041F
7-0
--
b7-b4:
Reserved for Future Use
95/117
STA400A
b4: b3: b2: b1: b0: Terrestrial Demodulator lock indicator Satellite #2 lock indicator Satellite #1 lock indicator FEC terrestrial-satellite combining decision for RS block #2 FEC terrestrial-satellite combining decision for RS block #1 0 = locked 1 = unlocked 0 = locked 1 = unlocked 0 = locked 1 = unlocked 0 = satellite; 1 = terrestrial; 0 = satellite; 1 = terrestrial;
2.7 PC Bitstream Interface PCDC_CONF_0 - Clock Configuration for PC Interface #0
Type: SingleByte - R/W Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
PCDC_CONF_0
0500
6-0
00
b6-b2: b1: b0:
PCDC_DIVVALUE_0 Master clock divider. The master clock is divided by (PCDC_DIVVALUE_0+1)*2. PCDC_NEG_0 1=PCDC0 is inverted. PCDC_RUNFREE_0 0=Clock running only when data is sent out; 1=Clock always running.
PCDC_CONF_1 - Clock Configuration for PC Interface #1
Type: SingleByte - R/W Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
PCDC_CONF_1
0501
6-0
00
b6-b2: b1: b0:
PCDC_DIVVALUE_1 Master clock divider. The master clock is divided by (PCDC_DIVVALUE_1+1)*2. PCDC_NEG_11=PCDC0 is inverted. PCDC_RUNFREE_10=Clock running only when data is sent out; 1=Clock always running.
PCSD_CONF_0 - Data Configuration for PC Interface #0
Type: SingleByte - R/W Word Length: 6 Byte Name Address (Hex) Bit Map Reset Value (Hex)
PCSD_CONF_0
0502
5-0
00
b5-b4:
PCSD_FFLAGMODE_0
00=Frame flag bit is always set to `0'; 01=Frame flag bit is set to `1' only for the first byte of TSCC1; 10=Frame flag bit is set to `1' for the first byte of all PRCs;
96/117
STA400A
11=Frame flag bit is set to `1' for the first byte of all PRCs. b3: b2: b1: b0: PCSD_FRAMEFLAG_0 PCSD_ODDPARITY_0 PCSD_ADDPARITY_0 PCSD_LSBFIRST_0 1=Frame flag bit is appended to each data byte 0=Even parity bit is generated; 1=Odd parity bit is generated. 1=Parity bit is appended to each data. 0=Parallel data sent out MSB first; 1=Parallel data sent out LSB first.
PCSD_CONF_1 - Data Configuration for PC interface #1
Type: SingleByte - R/W Word Length: 6 Byte Name Address (Hex) Bit Map Reset Value (Hex)
PCSD_CONF_1
0503
5-0
00
b5-b4:
PCSD_FFLAGMODE_1
00=Frame flag bit is always set to `0'; 01=Frame flag bit is set to `1' only for the first byte of TSCC1; 10=Frame flag bit is set to `1' for the first byte of all PRCs; 11=Frame flag bit is set to `1' for the first byte of all PRCs.
b3: b2: b1: b0: first.
PCSD_FRAMEFLAG_1 PCSD_ODDPARITY_1 PCSD_ADDPARITY_1 PCSD_LSBFIRST_1
1=Frame flag bit is appended to each data byte. 0=Even parity bit is generated; 1=Odd parity bit is generated. 1=Parity bit is appended to each data. 0=Parallel data sent out MSB first; 1=Parallel data sent out LSB
PCSYNC_CONF - Synchronization Signals Configuration for both Interfaces
Type: SingleByte - R/W Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
PCSYNC_CONF
0504
7-0
77
b7: b6: b5: b4: b3: b2: b1:
PCTS_EF_SWITCH_1 PCTS_SYNCH_1 PCFS_SYNCH_1 PCBS_SYNCH_1 PCTS_EF_SWITCH_0 PCTS_SYNCH_0 PCFS_SYNCH_0
0=PCTS_EF1 pin send out the TDM frame synchronization. 1=PCTS_EF1 pin send out the PC Interface output error flag. 0=PCTS1 set to `1' with first bit of TSCC1 1=PCTS1 set to `1' one PCDC cycle before the first bit of TSCC. 0=PCFS1 set to `1' with first bit of each PRC. 1=PCFS1 set to `1' one PCDC cycle before the first bit of PRC. 0=PCBS1 set to `1' with the first bit of each byte. 1=PCBS1 set to `1' one PCDC cycle before the first bit of byte. 0=PCTS_EF0 pin send out the TDM frame synchronization. 1=PCTS_EF0 pin send out the PC Interface output error flag. 0=PCTS0 set to `1' with first bit of TSCC1 1=PCTS0 set to `1' one PCDC cycle before the first bit of TSCC. 0=PCFS0 set to `1' with first bit of each PRC.
97/117
STA400A
1=PCFS0 set to `1' one PCDC cycle before the first bit of PRC. b0: PCBS_SYNCH_0 0=PCBS0 set to `1' with the first bit of each byte. 1=PCBS0 set to `1' one PCDC cycle before the first bit of byte. PC_ALARM - Alarm Signal for Interface #0 and #1
Type: SingleByte - R/W Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
PC_ALARM
0506
1-0
00
b1: b0: Note:
PC_ALARM_1 1=Data trasmission error in the interface #1; 0=Interface #1 operating properly. PC_ALARM_0 1=Data trasmission error in the interface #0; 0=Interface #0 operating properly. These bits are automatically set to `0' after read.
98/117
STA400A
2.8 TDM (Section 2) DeltaRefCyc_M - Delta Reference Cycles for MCM Frame Sync Given in samples and per MCM-frame. Format: siii,fffffffff with s=sign; i=integer part; f=fractional part
Type: MultiBytes - R Word Length: 13 Byte Name Address (Hex) Bit Map Reset Value (Hex)
DeltaRefCyc2_M DeltaRefCyc1_M
0611 0610
12-8 7-0
---
MfpSyncMax_S1 - Sat1 MFP Sync Rightmost Distance Sets the rightmost distance of sat1 MFP sync to the point, when the frame is read. The initial value corresponds to a time of 12ms.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpSyncMax_S1
0620
7-0
46
MfpSyncMin_S1 - Sat1 MFP Sync Leftmost Distance Sets the leftmost distance of sat1 MFP sync to the point, when the frame is read. The initial value corresponds to a time of 8ms.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpSyncMin_S1
0621
7-0
2F
MfpSyncMax_S2 - Sat2 MFP Sync Rightmost Distance Sets the rightmost distance of sat1 MFP sync to the point, when the frame is read. The initial value corresponds to a time of 12ms.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpSyncMax_S2
0622
7-0
46
MfpSyncMin_S2 - Sat2 MFP Sync Leftmost Distance Sets the leftmost distance of sat1 MFP sync to the point, when the frame is read. The initial value corresponds to a time of 8ms.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpSyncMin_S2
0623
7-0
2F
99/117
STA400A
MfpSyncMax_T - Terrestrial MFP Sync Rightmost Distance
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpSyncMax_T
0624
7-0
11
MfpSyncMin_T - Terrestrial MFP Sync Leftmost Distance
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MfpSyncMin_T
0625
7-0
29
Xmem_Type - External Memory Device Type
Type: SingleByte - R/W Word Length: 1 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Xmem_Type
0630
0
00
b0:
0= 64 Mbit memory
1= 128Mbit memory
XmemRefCyc - External Memory Refresh Cycle Period
Type: MultiBytes - R/W Word Length: 9 Byte Name Address (Hex) Bit Map Reset Value (Hex)
XmemRefCyc2 XmemRefCyc1
0632 0631
8 7-0
01 75
XmemMode - External Memory Management Mode
Type: SingleByte - R/W Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
XmemMode
0634
1-0
00
b1-b0:
00= Normal 01= Memory Dump
10= Unused 11= Self Test
XmemStatus - External Memory Management Status TDM external memory management self test error status
Type: SingleByte - R Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
XmemStatus
0635
1-0
--
100/117
STA400A
b1-b0: 00= No Error 01= Memory error, 1st test sequence 10= Unused 11= Memory error, 2nd test sequence
XmemStErrAdr - External Memory Management Self-Test Error Address TDM external memory error address. Only one error address will be stored.
Type: MultiBytes - R Word Length: 24 Byte Name Address (Hex) Bit Map Reset Value (Hex)
XmemStErrAdr3 XmemStErrAdr2 XmemStErrAdr1
0638 0637 0636
23-9 15-8 7-0
----
b23-b12: b11-b9: b8-b0:
Row Address Memory Bank Number Column Address
UdCycDelta_T - MFP Cycle Number Up-Down Delta Sets the number of system clock cycles the MFP cycle number is shortened or extended if tdm_rd_sync is not at the allowed position. This register influences delta_ref_cyc.
Type: MultiBytes - R/W Word Length: 11 Byte Name Address (Hex) Bit Map Reset Value (Hex)
UdCycDelta2_T UdCycDelta1_T
0641 0640
10-8 7-0
00 00
Cnt_Prio - MFP Cycles Time Interval Setting Sets the time interval in MFP cycles the priority is decremented
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cnt_Prio
0642
7-0
80
UdCycles - MFP Cycle Number Adjustment Sets the number of system clock cycles the MFP cycle number is shortened or extended if tdm_rd_sync is not at the allowed position. This directly influences the jitter of the MFP clock.
Type: MultiBytes - R/W Word Length: 11 Byte Name Address (Hex) Bit Map Reset Value (Hex)
UdCycles2 UdCycles1
0644 0643
10-8 7-0
00 9C
101/117
STA400A
FrameLen - TDM Frame Length Sets the nominal TDM frame length in system clock cycles. This value is used for the prediction of the MFP clock. The default value corresponds to 432ms at nominal system clock.
Type: MultiBytes - R/W Word Length: 24 Byte Name Address (Hex) Bit Map Reset Value (Hex)
FrameLen3 FrameLen2 FrameLen1
0647 0646 0645
23-9 15-8 7-0
9D AD 00
DeltaCycles - MFP Clock Period Monitor Displays the deviation of the actual MFP clock period from the nominal value set in register FrameLen (0x0645/ 46/47). The value is given in number of system clock cycles.
Type: MultiBytes - R Word Length: 11 Byte Name Address (Hex) Bit Map Reset Value (Hex)
DeltaCycles2 DeltaCycles1
0649 0648
10-8 7-0
---
MFC - Master Frame Counter
Type: MultiBytes - R Word Length: 11 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MFC2 MFC1
064B 064A
10-8 7-0
---
MFC_lsb - Master Frame Counter (LSB)
Type: SingleByte - R Word Length: 7 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MFC_lsb
064C
6-0
--
TDM2Enable - TDM Management Block Enable This register enables/disables the TDM2 internal blocks. The single block is enabled loading '1' in the corresponding bit.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TDM2Enable
064D
7-0
FF
102/117
STA400A
b7: b6: b5: b4: b3: b2: b1: b0: trs_en mcg_en pdc_en trm_en tam_en tmc_en twm_en trb_en enable TDM read synchronization enable MFP clock generation enable PRC demultiplex controller enable TDM read management enable TDM external memory access management enable TDM external memory controller enable TDM write management enable TDM bookkeeping
XmemFifoLevel - External Memory Write Access Buffer Filling Level External memory write access buffer filling level. Maximum value is 12dec.
Type: SingleByte - R Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
XmemFifoLevel
064E
3-0
--
PcidDataRd - PCID Table Read Register Using this register the internal prc demux table can be read together with the address register PcidAddr ( 0x0653) . In this register the pcid value together with the control flags for both pc interfaces is provided. PcidDataWr1 (0x0651) contains the pcid number. PcidDataWr2 (0x0652) contains whether the pcid interface 0 (b8) or 1 (b9) is enabled (=1) or disabled (=0)
Type: MultiBytes - R Word Length: 10 Byte Name Address (Hex) Bit Map Reset Value (Hex)
PcidDataRd2 PcidDataRd1
0650 064F
9-8 7-0
---
PcidDataWr - PCID Number Write and PC Interface Port Enable Using this register the internal prc demux table can be configured together with the address register PcidAddr (0x0653). In this register the pcid value together with the control flags for both pc interfaces is provided. PcidDataWr1 (0x0651) contains the pcid number. PcidDataWr2 (0x0652) contains whether the pcid interface 0 (b8) or 1 (b9) is enabled (=1) or disabled (=0)
Type: MultiBytes - WRT Word Length: 10 Byte Name Address (Hex) Bit Map Reset Value (Hex)
PcidDataWr2 PcidDataWr1
0652 0651
9-8 7-0
00 00
PcidAddr - Payload Channel Identifier Table Address Using this register the internal PRC demux table can be configured. The table has 28dec entries. This register holds the address where the PCID entry contained in register PcidDataWr (0x0652/51) is written into the table. In order to program the PCID table this register has to be set first. Starting with writing of PcidDataWr, the entry
103/117
STA400A
is taken over into the internal PCID table.
Type: SingleByte - R/W Word Length: 5 Byte Name Address (Hex) Bit Map Reset Value (Hex)
PcidAddr
0653
4-0
00
PRC_ti - Time Interval Between two PRCs The number written in this register must be multiplied by 1024 to get the time interval (in number of master clock cycles ).
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
PRC_ti
0654
7-0
C8
Clock cycles between two PRCs: Prc_ti * 1024 + 1. Since there are maximum 50 PRCs in a 432ms frame, with the reset value of this register the PRCs in the frame occupy the following time interval:
116 1024 + 1 ------------------------------------ 50 = 248.3ms 23.926
WARNING: This value must be greater than 8 and less than 202 to have a correct function of the PC Interface. TSCW_Err - Action Setting After Uncorrected TSCW Determines the behaviour in case of an uncorrected TSCC1 of a TDM frame, i.e. possible corrupted TSCW.
Type: SingleByte - R/W Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TSCW_Err
0655
1-0
00
b1-b0:
00 = 01 = 10 = 11 =
The TSCW of the last received error free TDM frame are used for decoding the PCs No PCs are decoded in case of TSCC1 RS uncorrected errors The received TSCWs are used for decoding NOT VALID.
TSCW_AddrRd - Word Address in the TSCW Table This register addresses the word in the TSCW table the user wants to read. Whenever register Tscw_Data (0x0657) is read, this address is automatically incremented.
Type: SingleByte - WRT Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TSCW_AddrRd
0656
7-0
00
104/117
STA400A
TSCW_Data - Addressed TSCW Word Contents Contains the TSCW word which shall be read.
Type: SingleByte - RT Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
TSCW_Data
0657
7-0
--
StatusErr_T - Management Error and Error Flag If trm_error=1 the next time interval has been started although not all data of the previous time interval have been processed.
Type: SingleByte - R Word Length: 2 Byte Name Address (Hex) Bit Map Reset Value (Hex)
StatusErr_T
0658
1-0
--
b1: b0:
trm_error trm_status
TDM Read Management error flag 0= TDM Read Management disabled 1= TDM Read Management operational
MgmtCtrl_T - TDM Management Control Vector If trm_first_proc=0/1 the satellite/terrestrial PRC packet is processed first in a time interval. If trm_terr_sat_comb_en=1 both terrestrial and satellite PRC packets are read. If trm_terr_sat_comb_en=0 only the PRC packets indicated by trm_first_proc (0:sat, 1:terr) are processed.
Type: SingleByte - R/W Word Length: 4 Byte Name Address (Hex) Bit Map Reset Value (Hex)
MgmtCtrl_T b3: b2: b1: b0: trm_sat_format trm_terr_format trm_terr_sat_comb_en trm_first_proc
0659
3-0
03
0= satellite data from SDRAM in 2's complement 1= satellite data from SDRAM in offset binary 0= terrestrial data from SDRAM in 2's complement 1= terrestrial data from SDRAM in offset binary 0= Terr-Sat Combining disabled 1= Terr-Sat Combining enabled 0= satellite PRC packet first 1= terrestrial PRC packet first
Tswc_AddCurr - TSCW Table Current Register Address
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Tscw_AddCurr
065B
7-0
--
105/117
STA400A
BK1-BK144 - TDM Management Book-Keeping Matrix
Type: SingleByte - TRT Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
BK1 BK2 ... BK144
0661 0662 ... 06F0
7-0 7-0 ... 7-0
FF FF ... FF
IrqMask_T - TDM Interrupt Mask
Type: SingleByte - INT Word Length: 3 Byte Name Address (Hex) Bit Map Reset Value (Hex)
IrqMask_T
06F5
2-0
00
b2: b1: b0:
RFU RFU RFU
IrqStatus_T - TDM Interrupt Status
Type: SingleByte - INT Word Length: 3 Byte Name Address (Hex) Bit Map Reset Value (Hex)
IrqStatus_T
06F6
2-0
00
b2: b1: b0:
RFU RFU RFU
2.9 Terrestrial Demodulator (Section 2) CfCntGood_M - Counter for Coarse Frequency Good Event Each time the Coarse Frequency calculates a new estimate that is good and is delivered to the Frequency Control this counter is incremented.
Type: MultiBytes - PR Word Length: 16 Byte Name Address (Hex) Bit Map Reset Value (Hex)
CfCntGood2_M CfCntGood1_M
0711 0710
15-8 7-0
00 00
106/117
STA400A
CfCntBad_M - Counter for Coarse Frequency Bad Event Each time the Coarse Frequency calculates a new estimate that is bad (and then not used) this counter is incremented.
Type: MultiBytes - PR Word Length: 16 Byte Name Address (Hex) Bit Map Reset Value (Hex)
CfCntBad2_M CfCntBad1_M
0716 0715
15-8 7-0
00 00
CfCtrl_M - Coarse Frequency Control
Type: SingleByte - R/W Word Length: 1 Byte Name Address (Hex) Bit Map Reset Value (Hex)
CfCtrl_M
0708
0
00
b0 :
Use_All_AMSS `0'=Use AMSS samples only in case of frame sync detection. `1'=Use AMSS samples even predidted ones.
Cf_MinKexpLow_M - Coarse Frequency Estimation Confidence Threshold Control of threshold value for good/bad decision of cf algorithm. This value determines the absolute minimum of the confidence threshold value for the distinction between good and bad estimates independently of the history stored within the sliding window buffer (see register 0x072D).
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_MinKexpLow_M
0720
7-0
90
Cf_DiffKexpMaxLow_M - Coarse Frequency Estimation Confidence Threshold Control of threshold value for good/bad decision of cf algorithm. This value is used to determine the relative minimum of the confidence threshold value for the distinction between good and bad estimates dependent on the maximum frequency estimate confidence value stored in the sliding window buffer (see register 0x072D). The relative minimum is calculated by the maximum estimate confidence value within the sliding window buffer minus the register value. The maximum value of both absolute and relative minimum values determines the lowest confidence threshold used by the algorithm.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_DiffKexpMaxLow_M
0721
7-0
08
Cf_Delta_KexpLow_M - Coarse Frequency Estimation Confidence Threshold Control of threshold value for good/bad decision of cf algorithm. This value is the decrement of the threshold
107/117
STA400A
value each time the algorithm lowers the confidence threshold due to bad estimates.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_Delta_KexpLow_M
0722
7-0
01
Cf_DeltaCntLow_M - Coarse Frequency Estimation Confidence Threshold Coarse Frequency Estimation Confidence Threshold Control. This value is the number of subsequent bad estimates for lowering the confidence threshold by a decrement of register 0x0722
Type: SingleByte - R/W Word Length: 10 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_DeltaCntLow2_M Cf_DeltaCntLow1_M
0724 0723
9-8 7-0
00 20
Cf_MaxKexpHigh_M - Coarse Frequency Estimation Confidence Threshold Control of threshold value for good/bad decision of cf algorithm. This value determines the absolute maximum of the confidence threshold value for the distinction between good and bad estimates independent of the history stored within the sliding window buffer (see register 0x072D).
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_MaxKexpHigh_M
0726
7-0
FF
Cf_DiffKexpMaxHigh_M - Coarse Frequency Estimation Confidence Threshold Control of threshold value for good/bad decision of cf algorithm. This value is used to determine the relative maximum of the confidence threshold value for the distinction between good and bad estimates dependent on the maximum frequency estimate confidence value stored in the sliding window buffer (see register 0x072D). The relative maximum is calculated by the maximum estimate confidence value within the sliding window buffer minus the register value. The minimum value of both absolute and relative maximum values determines the highest confidence threshold used by the algorithm.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_DiffKexpMaxHigh_M
0727
7-0
06
Cf_DeltaKexpHigh_M - Coarse Frequency Estimation Confidence Threshold Control of threshold value for good/bad decision of cf algorithm. This value is the increment of the threshold value each time the algorithm enlarges the confidence threshold due to good estimates.
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_DeltaKexpHigh_M
0728
7-0
01
108/117
STA400A
Cf_DeltaCntHigh_M - Coarse Frequency Estimation Confidence Threshold This value is the number of subsequent good estimates for enlarging the confidence threshold by an increment of register 0x0728
Type: SingleByte - R/W Word Length: 10 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_DeltaCntHigh2_M Cf_DeltaCntHigh1_M
072A 0729
9-8 7-0
00 01
Cf_InitDelay_M - Coarse Frequency Estimation Initial Delay This value determines the minimum number of AMSS estimates stored in the sliding window average before the first estimate is put out. For the calculation of the first cf estimate, Cf_InitDelay_M+1 estimates are taken into account. Within the initial phase no confidence threshold is applied and all estimates are good. Nevertheless the confidence threshold is calculated and used for the Cf_InitDelay_M+2nd estimate.
Type: SingleByte - R/W Word Length: 5 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_InitDelay_M
072B
4-0
17
Cf_KexpThAct_M - Current Confidence Threshold Value This register hold the current confidence threshold value the CF algorithm takes to distinguish between good and bad Coarse Frequency estimates. If the internally calculated confidence value is equal or larger than the current threshold the estimate is considered as good.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_KexpThAct_M
072D
7-0
--
Cf_EstAct_M - Coarse Frequency Estimation of AMSS Before Averaging With each received AMSS sequence a new frequency estimate is calculated together with a confidence value. Then an averaging over good estimates is performed. Within this register the coarse frequency estimate of the received AMSS before averaging is held.
Type: SingleByte - R/W Word Length: 16 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_EstAct2_M Cf_EstAct1_M
0731 0730
15-8 7-0
---
109/117
STA400A
Cf_KexpActExp_M - Coarse Frequency Confidence Exponent of AMSS Before Averaging With each received AMSS sequence a new frequency estimate is calculated together with a confidence value. Then an averaging over good estimates is performed. Within this register the confidence exponent of the coarse frequency estimate of the received AMSS before averaging is held.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_KexpActExp_M
0735
7-0
--
Cf_Est_M - Coarse Frequency Estimation of AMSS After averaging With each received AMSS sequence a new frequency estimate is calculated together with a confidence value. Then an averaging over good estimates is performed. Within this register the coarse frequency estimate of the received AMSS after averaging is held.
Type: SingleByte - R/W Word Length: 16 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_Est2_M Cf_Est1_M
0741 0740
15-8 7-0
---
Cf_EstExp_M - Coarse Frequency Confidence Exponent of AMSS After Averaging With each received AMSS sequence a new frequency estimate is calculated together with a confidence value. Then an averaging over good estimates is performed. Within this register the confidence exponen of the coarse frequency estimate of the received AMSS after averaging is held._
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_EstExp_M
0745
7-0
--
AvgEst_M - Current Coarse Frequency Averager Estimates This register shows the current CF estimate after the MCM CF Averager which is applied to the MCM Frequency Control. With each received CF estimate an new averaged CF estimte is put out when the corresponding confidence value exceeds the required threshold.
Type: SingleByte - R/W Word Length: 16 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_AvgEst2_M Cf_AvgEst1_M
0751 0750
15-8 7-0
---
110/117
STA400A
Cf_AvgEstExp_M - Current Coarse Frequency Averager Confidence Estimates This register shows the CF confidence value after the MCM CF Averager block. This confidence value is applied to the MCM Frequency Control.
Type: SingleByte - R Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_AvgEstExp_M
0755
7-0
--
Cf_AvgCtrl - Coarse Frequency Averager Control Register
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_AvgCtrl
0780
7-0
B0
b7 : b6 :
avg_en init_th_en
0 = Disabled; 1 = Enabled 0 = Disabled; 1 = Enabled TBD TBD
b5-b3 : avg_len b2-b0 : init_avg_delay
Cf_AvgMinEstConf - Threshold for Coarse Frequency Confidence
Type: SingleByte - R/W Word Length: 8 Byte Name Address (Hex) Bit Map Reset Value (Hex)
Cf_AvgCtrl
0780
7-0
B0
111/117
STA400A
3 I/O CELL DESCRIPTION
1) CMOS Output Pad Buffer, 2mA with slew rate control.
EXTERNAL PIN
MAX. LOAD
A
Z
D98AU920
Z
50pF
2) CMOS Output Pad Buffer, 4mA with slew rate control.
EXTERNAL PIN
MAX. LOAD
A
Z
D98AU920
Z
100pF
3) CMOS Schmitt Trigger Input Pad Buffer
A
Z
EXTERNAL PIN CAPACITANCE
A
D99AU1072
1pF
4) CMOS BiDir Pad Buffer, 2mA with slew rate control.
EN IO
EXTERNAL PIN
A
INPUT CAP
MAX. LOAD
I/O
ZI
D99AU1074A
1.5pF
50pF
5) CMOS Schmitt Trigger BiDir Pad Buffer, 4mA with slew rate control
EN IO A
EXTERNAL PIN
INPUT CAP
MAX. LOAD
I/O
ZI
D98AU921
1.9pF
100pF
112/117
STA400A
6) CMOS Input Pad Buffer, High Drive
A Z
EXTERNAL PIN CAPACITANCE
A
D98AU906
1.0pF
7) CMOS Input Pad Buffer with Active Pull-Down (50k resistor)
A Z
EXTERNAL PIN CAPACITANCE
A
D98AU923
1.0pF
8) Analog Pad Buffer
I/O I/O 460 Z
EXTERNAL PIN
INPUT CAP
MAX. LOAD
I/O (when input) I/O (when output)
D02AU1414
1.9pF 200pF
Max Voltage Swing
min: gnd-0.8 V max: vdd+0.8 V Vdd = 1.8 V
113/117
STA400A
9 TIMING DIAGRAMS 9.1 AC Characterictics (Guaranteed by Design) Figure 17. Clocks and I/O Timing Diagram
t
WH
t
WL
XTI/MCLK
t
RXC
t
FXC
MCLKO
t
MCLKON
FXCN
t
RXCN
t
IF2TD[9:0] IF2SD[7:0] MAI1 MDQ[7:0]
SU
t
HOLD
0000000000 0000000000 0000000000 0000000000 0000000000 0000000000
000000000000000000 000000000000000000 000000000000000000 000000000000000000 000000000000000000 000000000000000000
000000000 000000000 000000000 000000000 000000000 000000000
t
DIGITAL OUTPUTS
DATA(1)
DXO
DATA(2)
DATA(3)
Symbol
Parameter
Min
Max
Unit
tWH tWL tRXC tRXCN tFXC tFXCN tSU tHOLD tDXO
Clock High Pulse Width Clock Low Pulse Width Rise Delay (XTI/MCLK Clock Input to MCLKO Clock Output) Rise Delay (XTI/MCLK Clock Input to MCLKON Clock Output) Fall Delay (XTI/MCLK Clock Input to MCLKO Clock Output) Fall Delay (XTI/MCLK Clock Input to MCLKON Clock Output) Input Set-up Time Input Hold Time Output Data Valid Delay
6 6 7 10 7 9 1 5 13
nsec nsec nsec nsec nsec nsec nsec nsec nsec
Load Circuit: 50 pF to ground.
114/117
STA400A
9.2) Output Buffer Drive Characterictics (Guaranteed by Design) Figure 18. Slew Rate Load Circuit
Vdd3
tr
1 KOhm
0.6*Vdd3
tf
Vr
10pF 1 KOhm
0.2*Vdd3
Vf
RVSR=Vr/tr
FVSR=Vf/tf
Symbol
Parameter
Buffer
Codition
Min
Typ
Max
Unit
RVSR
Rise Voltage Slew Rate
2mA Driver 1)
With Load 2) No Load)
0.8 4.0 0.8 3.6 1.1 4.6 1.2 3.8
1.2 6.1 1.2 5.3 1.8 6.8 1.8 5.4 8.0 6.0
1.9 8.3 1.9 7.9 2.8 9.6 2.6 9.2
V/ns V/ns V/ns V/ns V/ns V/ns V/ns V/ns mA/ns mA/ns
FVSR
Fall Voltage Slew Rate
2mA Driver
With Load 2) No Load
RVSR
Rise Voltage Slew Rate
4mA Driver 1)
With Load 2) No Load
FVSR
Fall Voltage Slew Rate
4mA Driver
With Load 2) No Load
CSR 3)
Current Slew Rate
2mA Driver 4) 4mA Driver 5)
35pF load 6) 35pF load 6)
1) See PIN DESCRIPTION. 2) Load Circuit: see fig.17. 3) The Current Slew Rate values are the mean values between currents in Vdd=3.3V and GND power lines for one buffer. 4) Typical Peak Current in GND: 24mA. 5) Typical Peak Current in GND: 50mA. 6) Temperature 25 C, Vdd=3.3V.
115/117
STA400A
mm DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.17 0.09 22.00 20.00 17.50 0.50 22.00 20.00 17.50 0.60 1.00 0.75 0.018 1.40 0.22 TYP. MAX. 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.003 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.009 0.057 0.011 0.008 0.866 0.787 0.689 0.020 0.866 0.787 0.689 0.024 0.0393 0.030
OUTLINE AND MECHANICAL DATA
3.5 (min.), 7(max.)
TQFP144 (20x20x1.40mm)
Note 1: Exact shape of each corner is optional
0099183
116/117
STA400A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
117/117

▲Up To Search▲

Price & Availability of STA400A

	To Download STA400A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .