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TQ8025
32 DIO-15 (differential)
PECL/CML Input Buffers
16 x 16 Crosspoint Switch Matrix
32
PRELIMINARY DATA SHEET
DOO-15 (differential)
PECL/CML Output Buffers
RESET- LDMODE CONFIG
16 x 4 Configuration Latches 4-Bit Shift Register
READY
2.5 Gigabit/sec 16x16 Digital Crosspoint Switch
Features
* 16 PECL/CML fully differential (back-terminated) outputs * >2.5 Gb/s data bandwidth per channel * >40 Gb/s aggregate bandwidth
SWITCHING PRODUCTS
ADD15
+5V GND
ADDO
4-Bit Shift Register
LOAD CLOCK ADDREN AUTOCONFIG
Address Generator and Control
RADDO RADD1
TQ8025
The TQ8025 is a non-blocking 16 x 16 digital crosspoint switch capable of data rates greater than 2.5 gigabits per second per port. With a fully differential internal data path and PECL/CML I/O, the TQ8025 offers an extremely high data rate with exceptional signal fidelity. The use of fully differential logic results in low crosstalk, jitter, and signal skew. The TQ8025 is ideally suited for digital video, data communications, telecommunication switching, and cross-connect applications. The non-blocking architecture uses 16 fully independent 16:1 multiplexers which allow each output port to be independently programmed to any input port. The TQ8025 offers two programming options: a flexible port-by-port option, and a fast configuration option. Using the fast configuration option, all 16 switch ports are programmed within 80ns by serially loading four 16-bit input port selection words. Two output pins (RADD0,1) are provided to drive an external RAM (n x 4 x 16 bits) used to store the switch configuration. An Autoconfigure option automatically transfers the new configurations into the switch core. Autoconfiguration occurs after the last input selection word is clocked into the programming registers. Data integrity is maintained on all unchanged data paths for both the portby-port and fast configuration options.
* Non-blocking architecture * 80 ns configuration time * Autonomous control of external RAM for configuration data * Low jitter and signal skew * 100 ps delay match (one input to all outputs) * Fully differential data path * 132-pin MLC package with heat spreader
Applications
* SONET OC-48 data path * Double-speed Fibre Channel * Hubs and routers * High-definition video switching * Parallel processing
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1
TQ8025
PRELIMINARY DATA SHEET
Specifications
Table 1. Absolute Maximum Ratings 4
Storage temperature Junction temperature Case temperature with bias 1 Supply voltage 2 Voltage to any input 2 Voltage to any output 2 Current to any input 2 Current from any output 2 Power dissipation of output 3
TSTORE TCH TC VCC VIN VOUT IIN IOUT POUT -65 C to +150 C 150 C TJ = 150 C 0 V to +7.0 V -0.5 V to VCC + 0.5 V -0.5 V to VCC + 0.5 V -1.0 mA to +1.0 mA 40 mA 50 mW
Notes: 1. TC is measured at the case top. 2. All voltages are measeured with respect to GND 0V and are continuous. 3. POUT = (VCC - VOUT) x IOUT. 4. Absolute maximum ratings in this table are those beyond which the device's performance may be impaired and/or permanent damage may occur.
Table 2. Recommended Operating Conditions 4
Symbol
TC VCC VTT ICC RLOAD JC
Parameter
Case Operating Temperature Supply Voltage Load Termination Supply Voltage Current Positive Supply Output Termination Load Resistance Thermal Resistance Channel to Case
Min
0 4.75 --
Typ
-- -- VCC - 2.0 -- 50
Max
85 5.25 2.1 4.5
Units
C V V A C/W
Notes
1, 3 2 2
Notes: 1. 2. 3. 4.
TC measured at case top. Use of adequate heatsink is required. The VTT and RLOAD combination is subject to maximum output current and power restrictions. Contact the Factory for extended temperature range applications. Functionality and/or adherence to electrical specifications is not implied when the device is subjected to conditions that exceed, singularly or in combination, the operating range specified.
2
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TQ8025
PRELIMINARY DATA SHEET
Table 3. DC Characteristics -- CML I/O 5
Symbol
VCOM VDIFF VIH VIL VOH VOL IOH IOL
Description
Common mode voltage Differential voltage Input HIGH voltage Input LOW voltage Output HIGH voltage Output LOW voltage Output HIGH current Output LOW current
Test Conditions
(Note 1) (Note 1) (Note 2)
Min
VCC - 600 400 VCC - 1100
Nom
-- -- -- -- -- -- 23 5
Max
VCC 1200 VCC VCC VCC - 600 30 8
Unit
mV mV mV mV mV mV mA SWITCHING PRODUCTS mA
(Note 3) (Note 3) (Note 3, 4) (Note 3, 4)
VCC - 100 VCC - 1100 20 0
Table 4. DC Characteristics -- PECL I/O 5
Symbol
VCOM VDIFF VIH VIL VOH VOL IOH IOL CIN COUT VESD
Description
Common mode voltage Differential voltage Input HIGH voltage Input LOW voltage Output HIGH voltage Output LOW voltage Output HIGH current Output LOW current Input capacitance Output capacitance ESD breakdown rating
Test Conditions
(Note 1) (Note 1) (Note 2) (Note 3) (Note 3) (Note 4) (Note 4)
Min
VCC - 1500 400 VCC - 2100 VCC - 1100 VCC - 2100 20 0 -- --
Nom
-- -- -- -- -- -- 23 5 -- -- --
Max
VCC - 1100 1200 VCC - 500 VCC - 600 VCC - 1600 30 8 TBD TBD --
Unit
mV mV mV mV mV mV mA mA pF pF
(Note 5)
Class I
Table 5. DC Characteristics -- TTL I/O 5
Symbol
VIH VIL IIH IIL VOH VOL CIN COUT VESD
Description
Input HIGH voltage Input LOW voltage Input HIGH current Input LOW current Output HIGH voltage Output LOW voltage Input capacitance Output capacitance ESD breakdown rating
1. 2. 3. 4. 5.
Test Conditions
Min
2.0 0
Nom
-- -- -- -200 -- -- -- -- --
Max
VCC 0.8 200 -- VCC 0.4 TBD TBD --
Unit
V V uA uA V V pF pF
V(IHMAX) V(ILMIN) IOH = 50 mA IOH = -20 mA
-- -400 2.4 0 -- -- Class I
(Note 5)
Notes (Tables 3, 4, and 5):
Differential inputs. VREF = 1300 mV. RLOAD = 50 ohms to VTT = VCC - 2.0 V. Not tested; consistent with VOH and VOL tests. Specifications apply over recommended operating ranges.
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3
TQ8025
PRELIMINARY DATA SHEET
Table 6. AC Characteristics
Symbol
TPW TR/F TPD TSKEW TJITTER
Description
O(0:15) rise/fall time 20-80% D(0:15), O(0:15) delay time Path delay matching Jitter
Test Conditions
(Note 1) (Note 1) (Note 1) (Note 2)
Min
360 -- -- --
Typ
-- -- -- 300 50
Max
-- 150 2.5 --
Unit
ps ps ns ps ps pk-pk
D(0:15) minimum pulse width (Note 1)
Notes: 1. Minimum VOH to maximum VOL levels. 2. Crossing of (On)--(NOn) measured with 223 - 1 PRBS, measured over extended time.
Table 7. TQ8025 Timing -- Normal Configure Mode 1
Symbol
T1 T2 T3 T4 T5 T6
Parameter
Hold LOAD low to SAD0:3, DAD0:3 Setup DAD0:3 to LOAD high CONFIGURE pulse low time Setup LOAD low to CONFIGURE low CONFIGURE low to SIGNAL PATHS updated LOAD pulse width high
Min.
2 0 10 3 4 TBD
Max.
Units
ns ns ns ns ns ns
Notes: 1. LDMODE = 0; AUTOCONFIG = Don't Care, RESET- = 1, CLOCK = Don't Care.
Figure 1. TQ8025 Timing -- Normal Configure Mode
DAD0:3 DEST ADDR 1 T1 SAD0:3 SRCE ADDR 1 T6 LOAD T4 CONFIGURE T5 SIGNAL PATHS OLD CONFIGURATION NEW CONFIGURATION T3 T2 SRCE ADDR 2 DEST ADDR 2 T1
LDMODE=0; AUTOCONFIG = Don't Care, RESET- = 1, CLOCK = Don't Care.
4
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TQ8025
PRELIMINARY DATA SHEET
Table 8. TQ8025 Timing -- RAM Loading, Auto-Configure Mode 1
Symbol
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
Parameter
LOAD high to READY low CLOCK low to READY high ADDREN low to RADD enabled Setup LOAD high to CLOCK high CLOCK low to RADD increment AD0:15 setup before CLOCK low AD0:15 hold time after CLOCK low CLOCK low to INT CONFIGURE high CONFIGURE low pulse width ADDREN high to RADD tristate LOAD low prior to 3rd CLOCK low LOAD high pulse CLOCK low to SIGNAL PATHS updated CLOCK period LOAD high to INT CONFIGURE low
Min.
3 3 3 4 2 0 2 2 10 3 4 TBD 4 20 TBD
Max.
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SWITCHING PRODUCTS
Notes: 1. LDMODE = 1; AUTOCONFIG = 1, RESET- = 1, CONFIG = 1.
Figure 2. TQ8025 Timing -- RAM Loading, Auto-Configure Mode
T14 CLOCK T4 T12 LOAD ADDREN T10 T3 RADD0:1 T1 0 T5 1 2 3 T2 0 T1
T11
READY
T6 AD0:15 D0
T7 D1 D2 D3 T15
T15 INT CONFIGURE
T8
T9
T13 SIGNAL PATHS OLD CONFIGURATION NEW CONFIGURATION
LDMODE = 1; AUTOCONFIG = 0, RESET- = 1.
Note: INT CONFIGURE is an internal signal shown for clarity of operation.
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5
TQ8025
PRELIMINARY DATA SHEET
Table 9. TQ8025 Timing -- RAM Loading, External Configure Pulse Mode 1
Symbol
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
Parameter
LOAD high to READY low CLOCK low to READY high ADDREN low to RADD enabled Setup LOAD high to CLOCK high CLOCK low to RADD increment AD0:15 setup before CLOCK low AD0:15 hold time after CLOCK low Setup last CLOCK before CONFIGURE low CONFIGURE low pulse width ADDREN high to RADD tristate LOAD low prior to 3rd CLOCK low LOAD high pulse CONFIGURE low to READY low CONFIGURE low to SIGNAL PATHS updated CLOCK period
Min.
3 3 3 4 2 0 2 2 10 3 4 TBD TBD 4 20
Max.
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. LDMODE = 1; AUTOCONFIG = 0, RESET- = 1.
Figure 3. TQ8025 Timing -- RAM Loading, External Configure Pulse Mode
T15 CLOCK T4 T12 LOAD ADDREN T3 RADD0:1 T1 READY T6 AD0:15 CONFIGURE T14 SIGNAL PATHS OLD CONFIGURATION NEW CONFIGURATION D0 T7 D1 D2 D3 T8 T9 0 T5 1 2 3 T2 T13 0 T10
T11
LDMODE = 1; AUTOCONFIG = 1, RESET- = 1, CONFIG = 1.
6
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TQ8025
PRELIMINARY DATA SHEET
Typical Performance
Data Rate: 2.5Gb/s Data Pattern: 2^7 PRBS
Note: Measured jitter is 68ps pk-pk. Signal source jitter is 32ps pk-pk.
SWITCHING PRODUCTS
Rise and Fall
Data Rate: 2.5Gb/s Rise Time: 115ps Fall Time: 109ps
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7
TQ8025
PRELIMINARY DATA SHEET
Figure 4. TQ8025 pinout -- top view
Vcc Vcc N.C. N.C. VTT VTT Vcc DI08P DI08N DI09P DI09N Vcc DI10P DI10N DI11P DI11N Vcc DI12P DI12N DI13P DI13N Vcc DI14P DI14N DI15P DI15N Vcc DO15N DO15P DO14N DO14P Vcc GND
33 32 31 30 29 2827 26 25 24 23 22 21 20 19 18 17 16 15 14 1312 11 10 9 8 7 6 5 4 3 2 1
GND Vcc AD15 AD14 AD13 AD12 Vcc AD11 AD10 AD09 AD08 Vcc AD07/DAD3 AD06/DAD2 AD05/DAD1 AD04/DAD0 Vcc AD03/SAD3 AD02/SAD2 AD01/SAD1 AD00/SAD0 Vcc RADD0 RADD1 LOAD RESETVcc AUTOCONFIG CLOCK CONFIG READYVcc Vcc
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
TQ8025
132-pin Heat Spreader Cavity Down Top View
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
Vcc Vcc DO13N DO13P DO12N DO12P Vcc DO11N DO11P DO10N DO10P Vcc DO09N DO09P DO08N DO08P Vcc DO07N DO07P DO06N DO06P Vcc DO05N DO05P DO04N DO04P Vcc DO03N DO03P DO02N DO02P Vcc GND
67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 8788 89 90 91 9293 94 95 9697 98 99
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GND Vcc LDMODE ADDREN VTT VTT Vcc DI00P DI00N DI01P DI01N Vcc DI02P DI02N DI03P DI03N Vcc DI04P DI04N DI05P DI05N Vcc DI06P DI06N DI07P DI07N Vcc DO00P DO00N DO01P DO01N Vcc Vcc
TQ8025
PRELIMINARY DATA SHEET
Table 10. TQ8025 Pin Descriptions
Signal
DI00P-DI15P DI0N-DI15N DO0P-DO15P, DO0N-DO15N AD00:15 RADD0:1 ADDREN CLOCK AUTOCONFIG READY
Name/Level
Data input true and complement Differential CML/PECL input Data output true and complement Differential CML/PECL output Input address; TTL input RAM address; TTL output, tristate Enable RADD0:2; TTL input Clock; TTL input Configure mode; TTL input READY; open-drain output
Description
Differential data input ports. VH = 0 V, VL = -300 mV max. Internal 50-ohm terminations to VTT (CML = 0 V;ECL = -2.0 V). Differential data output ports. 600 mV min. differential swing. Serial input address, LSB first in time; ADn programs output port n. Used to generate address 0-3 during configure load from RAM. Controls cycle time of address generator and AUTOCONFIG. When high, internal CONFIGURE is automatically generated. Indicates end of AUTOCONFIG or end of address LOAD cycle when high. Reset low by RESET-, CONFIG low, or LOAD rising. Requires external pullup to VCC. For LDMODE=1, ADDREN=0: AUTOCONFIG=0, rising LOAD causes ADDR0:1 to generate RAM addresses, then READY is asserted after four clock ticks. For AUTOCONFIG=1, LOAD rising causes ADDR0:1 to generate addresses, causing an internal CONFIG to be generated, after which READY is asserted. For LDMODE=0, see SAD0:3 and DAD0:3. Used to load address contents of internal address registers. Active LOW. Crosspoint will be configured within 4 ns (objective) of CONFIG falling low. When floated high, AD0-15 are used for configuration. When tied low, SAD0-3 and DAD0-3 are used for configuration. When AUTOCONFIG is disabled, and AD08-15 are ignored. When LDMODE is low, specifies input address to be connected to output port specified by DAD0:3. Latched by falling LOAD (LDMODE=0). When LDMODE is low, specifies output address to be connected to input port specified by SAD0:3. Latched by falling LOAD (LDMODE=0). Power and ground pins. VTT = GND for CML inputs; VTT = VCC - 2V for PECL inputs. While low, programs all output ports to connect to input port 0. Strobing CONFIG after reset restores user port programming if device power was stable since last user programming and during RESET-. Active low, Schmitt triggered. SWITCHING PRODUCTS When low, enables RADD0:1; when high, forces RADD0:1 tristate.
LOAD
LOAD; TTL input
CONFIGURE
CONFIGURE; TTL input
LDMODE
Load Mode; TTL input
SAD0:3
Source Address; TTL inputs
DAD0:3
Destination Address; TTL input
VCC, GND, VTT RESET-
+5V, Ground; Termination Voltage Reset; TTL Input
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9
TQ8025
PRELIMINARY DATA SHEET
Figure 5. Mechanical Dimensions Bottom view Top view
132
1.170 +.006 .950 +.006 .800
PIN 1 INDEX
1
CERAMIC OR METAL LID
A
A
0.325 .005 .025
CHIP CAPACITOR, 4 PLACES
.010 +.0015 BSC 1. Part is symmetrical about the center axes. 2. Centerline bisects center pin in both directions. 3. See pad detail below.
Section A-A
.060 HEAT SPREADER DEVICE .125
0.025 centers 0.015 CL
SEATING PLANE .064
0.010
0.525 CL
0.105
PAD LAYOUT DETAIL
Ordering Information
TQ8025
Additional Information
2.5 Gb/s 16x16 Crosspoint Switch
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: sales@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900
For technical questions and additional information on specific applications: Email: applications@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or ommisions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright (c) 1998 TriQuint Semiconductor, Inc. All rights reserved. Revision 0.3.A August 1998
10
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