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APU428
4-Bit Micro-controller With LCD Driver
Features
Low power dissipation Powerful instruction set (148 instructions) Binary addition, subtraction, BCD adjustment, logical operation in direct addressing mode and index addressing mode Single-bit manipulation (set, reset, decision for branch) Various conditional branches 16 working registers and manipulation LCD driver data transfer Look-up table Programmable option System clock selection Memory capacity Instruction ROM capacity 2048 x 16 bits Index ROM capacity 256 x 8 bits Internal RAM capacity 256 x 4 bits (low-address 128 nibbles can be accessed by direct addressing, full-range 256 nibbles can be accessed by index addressing) Input/output ports Port IOA 4 pins (with internal pull-low, chattering clock, MUX with CX, RR, RT, RH/ SEG 37~40 by mask option) Port IOB 4 pins (MUX with ELC, ELP, BZB, BZ/SEG41, 42 by mask option) Port IOC 4 pins (with internal pull-low, low-level hold, chattering clock, MUX option with AN1~4 by mask option) Port IOD 4 pins (MUX with PWM1, 2/SEG33~36 by mask option) 8-level subroutine nesting Interrupt function External factor 2 (INT pin & port IOA, IOC input) Internal factor 4 (predivider, 2 timers & RFC) Built-in EL-light driver, alarm, frequency or melody generator (MUX with IOB/ SEG41, 42) Built-in R to F converter circuit (MUX with IOA/SEG37~40) Built-in comparator, 6/8-bit PWM output, 4-bit D/A converter, low-battery detector; this structure can be used as a 4/6/8-bit full range ADC Port PWM 2 pins (MUX with SEG35, 36) Port ADC 4 pins (MUX with IOC) 2 6-bit programmable timers with programmable clock source Watchdog timer LCD/LED driver output 42 LCD/LED driver outputs (up to 168 LCD segments are drivable) Mask option is used to select static, 1/2 bias 1/2 duty, 1/2 bias 1/3 duty, 1/2 bias 1/4 duty, 1/3 bias 1/3 duty and 1/3 bias 1/4 duty drive modes of the LCD panel Mask option is used to select DC output, and static, 1/2 duty, 1/3 duty and 1/4 duty drive modes of the LED panel Mask option is used to select SEG28~32 as P open-drain DC outputs Single instruction stops all segments that are either in LCD or LED Built-in voltage doubler, halver, tripler charge pump circuit Dual clock operation HALT function Stop function
General Description
APU428 is an embedded high-performance 4-bit microcomputer with an LCD/LED driver. It contains all the necessary functions in a single chip: 4-bit parallel processing ALU, ROM, RAM, I/O ports, timer, clock generator, dual clock, ADC, RFC, alarm, EL-light, LCD driver, look-up table and watchdog timer. The instruction set consists of 148 instructions which include nibble operation, manipulation, various conditional branch instructions and LCD data transfer instructions which are powerful and easy to follow. The HALT function stops any internal operations other than the oscillator, divider and LCD driver in order to minimize the power dissipation. The stop function stops all clocks in the chip.
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Block Diagram
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Pad Assignment
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Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Pad Name SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 X 560 675 790 905 1020 1135 1250 1365 1480 1595 1710 1840 1970 1970 1970 1970 1970 1970 1970 Y 70 70 70 70 70 70 70 70 70 70 70 70 160 290 420 535 650 765 880 3 Pad No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Pad Name SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 IOB3 IOB4 GND VDD CFIN CFOUT XTIN XTOUT TESTA RESET X 1480 1365 1250 1135 1020 905 790 675 560 445 330 200 70 70 70 70 70 70 70 Y 2265 2265 2265 2265 2265 2265 2265 2265 2265 2265 2265 2265 2175 2045 1915 1800 1685 1570 1455 Ver. 0.0
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Pad No. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Pad Name SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 X 1970 1970 1970 1970 1970 1970 1970 1970 1970 1970 1970 1840 1710 1595 Y 995 1110 1225 1340 1455 1570 1685 1800 1915 2045 2175 2265 2265 2265 Pad No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Pad Name INT IOM1 IOM2 IOM3 IOM4 VDD1 VDD2 VDD3 CUP1 CUP2 COM1 COM2 COM3 COM4 X Y 70 1340 70 1225 70 1110 70 995 70 880 70 765 70 650 70 535 70 420 70 290 70 160 200 70 330 70 445 70 Chip size: 84.65 x 96.45 mil2
Pad Descriptions
Pad Name BAK VDD1 VDD2 VDD3 RESET I/O Description Positive back-up voltage. In Li mode, connects a 0.1u capacitance to GND. LCD drives the voltage and positive supply voltage. While in Ag mode, connects +1.5V to VDD1. While in Li/ExtV mode, connects +3.0V to VDD2. Input pin from LSI reset request signal. Internal pull-down resistor. Input pin for external INT request signal. Falling or rising edge triggered by mask option. Internal pull-down or pull-up resistor or none is selected by mask option. Test signal input pin. Switching pins for supplying the LCD driving voltage to the VDD1, 2, 3 pins. Connects the CUP1 and CUP2 pins with nonpolarized electrolytic capacitor if 1/2 or 1/3 bias mode has been selected. In the static mode, these pins should be open. Time-based counter frequency (clock-specified, LCD alternating frequency, alarm signal frequency) or system clock oscillation. 32kHz crystal oscillator. Oscillation stops at the execution of STOP instruction. System clock oscillation. Connected with ceramic resonator. Connected with RC oscillation circuit. Oscillation stops at the execution of STOP or SLOW instruction. Output pins for supplying voltage to drive the common pins of the LCD or LED panel. Output pins for LCD or LED panel segment. Input/Output port A can use software to define the internal pull-low resistor and chattering clock in order to reduce input bounce and generate interrupt. This port shares pins with SEG37~40 and is set by mask option. This port also shares pins with CC, RR, RT and RH, and is set by mask option. 4 Ver. 0.0
I
INT TESTA CUP1 CUP2 XIN XOUT
I I O
I O I O O O I/O
CFIN CFOUT COM1~4 SEG1~42 IOA1~4
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Pad Name IOB1~4 I/O I/O Description I/O Input/Output port B. IOB1, 2 shares pins with SEG41, 42, or ELC, ELP and is set by mask option. IOB3, 4 shares pins with BZ, BZB and is set by mask option. I/O Input/Output port C can use software to define the internal pull-low/ low-level hold resistor and chattering clock in order to reduce input bounce and generate interrupt. This port shares pins with AN1-4 and is set by mask option. Input / Output port D. This port shares pins with SEG33~36 and is set by mask option. IOD3,4 shares pins with PWM1,2 and is set by mask option. 1 input pin and 3 output pins for RFC application. This port shares pins with SEG37~40 and is set by mask option. This port shares pins with IOA1~4 and is set by mask option. Output port for the EL-light. These ports share pins with SEG41, 42 and are set by mask option. These ports share pins with IOB1, 2 and are set by mask option. Output port for alarm, frequency or melody generator. This port shares pins with IOB3,4 and is set by mask option. Negative supply voltage.
IOC1~4
I/O
IOD1~4 RFC RR RT RH EL ELP ALM Z GND CC
I/O I O O O O O O O
ELC
BZB
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Absolute Maximum Rating
Name Maximum Supply Voltage Maximum Input Voltage Maximum Output Voltage Maximum Operating Temperature Maximum Storage Temperature Symbol VDD1 VDD2 VDD3 VIN VOUT1 VOUT2 tOPG tSTG Rating -0.3 ~ +5.5 -0.3 ~ +5.5 -0.3 ~ +8.5 -0.3 to VDD1/2+0.3 -0.3 to VDD1/2+0.3 -0.3 to VDD3+0.3 0 to +70 -25 to +125 Ta = 0 to 70 Condition Min. 1.2 2.4 2.4 1.3 1.2 1.2 2.4 VDD1-0.7 -0.7 VDD2-0.7 -0.7 0.8VDD1 0 0.8VDD2 0 0.8VDD2 0 0.8VDDO 0 32 32 1000 Max. 5.25 5.25 8.0 GND=0V Unit V V V V V V V V V V V V V V V V V V V kHz kHz kHz Ta = 0 to 70 GND=0V Unit V V V V V V
Allowable operating conditions
Name Supply Voltage Oscillator Start-up Voltage Oscillator Sustain Voltage Supply Voltage Supply Voltage Input H Voltage Input L Voltage Input H Voltage Input L Voltage Input H Voltage Input L Voltage Input H Voltage Input L Voltage Input H Voltage Input L Voltage Input H Voltage Input L Voltage Operating Freq. Symbol VDD1 VDD2 VDD3 VDDB VDDB VDD1 VDD2 VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VIH4 VIL4 VIH5 VIL5 VIH6 VIL6 fOPG1 fOPG2 fOPG3
Crystal Mode Crystal Mode Ag Mode EXT-V, Li Mode Ag Battery Mode Li Battery Mode OSCIN at Ag Battery Mode OSCIN at Li Battery Mode CFIN at Li Battery or EXT-V Mode RC Mode Crystal Mode External RC Mode CF Mode
1.65 5.25 VDD1+0.7 0.7 VDD2+0.7 0.7 VDD1 0.2VDD1 VDD2 0.2VDD2 VDD2 0.2VDD2 VDDO 0.2VDDO 3580 1000 3580
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Electrical Characteristics
Input resistance Name L -Level Hold tR (IOC) IOC/IOA Pull-Down tR Symbol RIIH1 RIIH2 RIIH3 RMSD1 RMSD2 RMSD3 RINTU1 INT Pull-Up tR RINTU2 RINTU3 RINTD1 INT Pull-Down tR RINTD2 RINTD3 RRES1 RES Pull-Down tR RRES2 RRES3 Condition VI=0.2VDD1, #1 VI=0.2VDD2, #2 VI=0.2VDD2, #3 VI=VDD1, #1 VI=VDD2, #2 VI=VDD3, #3 VI=VDD1, #1 VI=VDD2, #2 VI=VDD3, #3 VI=GND, #1 VI=GND, #2 VI=GND, #3 VI=GND or VDD1, #1 VI=GND or VDD2, #2 VI=GND or VDD2, #3 Min. 10 10 5 200 200 100 200 200 100 200 200 100 5 5 5 Typ. 40 40 20 500 500 250 500 500 250 500 500 250 20 20 20 Max. 100 100 50 1000 1000 500 1000 1000 500 1000 1000 500 50 50 50 Unit k k k k k k k k k k k k k k k Ta=0 to 70
Note: #1: VDD1= 1.2V ( Ag ), #2: VDD2= 2.4V ( Li ), #3: VDD2= 4V (Ext-V). DC output characteristics Name Output H Voltage Symbol VOH1a VOH2 a VOH3 a VOL1 a Output L Voltage VOL2 a VOL3 a VOH1c Output H Voltage VOH2c VOH3c VOL1c VOL2c VOL3c Condition IOH=-10 A, #1 IOH=-50 A, #2 IOH=-200 A, #3 IOL=20 A, #1 IOL=100 A, #2 IOL=400 A, #3 IOH=-200 A, #1 IOH=-1mA, #2 IOH=-3mA, #3 IOL=400 A, #1 IOL=2mA, #2 IOL=6mA, #3 SEG33~ SEG42, IOB3~4, IOC-n SEG1~ SEG32 For Min. 0.8 1.5 2.5 0.2 0.3 0.5 0.8 1.5 2.5 0.2 0.3 0.5 Typ. 0.9 1.8 3 0.3 0.6 1.0 0.9 1.8 3 0.3 0.6 1.0 Max. 1.0 2.1 3.5 0.4 0.9 1.5 1.0 2.1 3.5 0.4 0.9 1.5 Unit V V V V V V V V V V V V
Output L Voltage
Note: #1: VDD1= 1.2V ( Ag ), #2: VDD2= 2.4V ( Li ), #3: VDD2= 4V (Ext-V).
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Segment driver output characteristics Name Static display mode Output H Voltage Symbol VOH1d VOH2d VOH3d VOL1d VOL2d VOL3d VOH1e VOH2e VOH3e VOL1e VOL2e VOL3e VOH12f VOH3f VOL12f VOL3f VOH12g VOH3g VOM12g VOM3g VOL12g VOL3g VOH12i VOH3i VOM12i VOM13i VOM22i VOM23i VOL12i VOL3i VOH12j VOH3j VOM12j VOM13j VOM22j VOM23j VOL12j VOL3j Condition IOH=-1 A, #1 IOH=-1 A, #2 IOH=-1 A, #3 IOL=1 A, #1 IOL=1 A, #2 IOL=1 A, #3 IOH=-10 A, #1 IOH=-10 A, #2 IOH=-10 A, #3 IOL=10 A, #1 IOL=10 A, #2 IOL=10 A, #3 IOH=-1 A, #1, #2 IOH=-1 A, #3 IOL=1 A, #1, #2 IOL=1 A, #3 IOH=-10 A, #1, #2 IOH=-10 A, #3 IOI/H= 10 A, #1, #2 IOI/H= 10 A, #3 IOL=10 A, #1, #2 IOL=10 A, #3 IOH=-1 A, #1, #2 IOH=-1 A, #3 IOI/H= 10 A, #1, #2 IOI/H= 10 A, #3 IOI/H= 10 A, #1, #2 IOI/H= 10 A, #3 IOL=1 A, #1, #2 IOL=1 A, #3 IOH=-10 A, #1, #2 IOH=-10 A, #3 IOI/H= 10 A, #1, #2 IOI/H= 10 A, #3 IOI/H= 10 A, #1, #2 IOI/H= 10 A, #3 IOL=10 A, #1, #2 IOL=10 A, #3 For Min. 1.0 2.2 3.8 0.2 0.2 0.2 1.0 2.2 3.8 0.2 0.2 0.2 2.2 3.8 0.2 0.2 2.2 3.8 1.0 1.8 Typ. Max. Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
SEG-n
Output L Voltage
Output H Voltage
COM-n
Output L Voltage 1/2 bias display mode Output H Voltage Output L Voltage Output H Voltage Output M Voltage Output L Voltage 1/3 bias display mode Output H Voltage Output M1 Voltage Output M2 Voltage Output L Voltage Output H Voltage Output M1 Voltage Output M2 Voltage Output L Voltage
SEG-n
COM-n
1.4 2.2 0.2 0.2
SEG-n
3.4 5.8 1.0 1.8 2.2 3.8
1.4 2.2 2.6 4.2 0.2 0.2
COM-n
3.4 5.8 1.0 1.8 2.2 3.8
1.4 2.2 2.6 4.2 0.2 0.2
Note: #1: VDD1= 1.2V ( Ag ), #2: VDD2= 2.4V ( Li ), #3: VDD2= 4V (Ext-V).
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Functional Description
Index SRAM The 256 X 4 bits index SRAM is used for applications that need more SRAM or need to load addresses by operation, and data SRAM is included at a lower-half address in the index SRAM. Index ROM The 256 X 8 bits index ROM can be used in the 4-bit or 8-bit mode. I/O ports The IOA port can be selected by software separately as input or output. It can also be selected with/without internal pull-low and different chattering clocks for a HALT release / interrupt trigger in order to reduce the input bounce for the key scan: PH6: 512Hz, PH8: 128Hz, PH10: 32Hz. The pull-low of IOA will be masked off for those pins defined as output pins: The IOA port can be used as a pseudo serial output port. The IOB port can be selected by software separately as input or output. Th e IOC port can be selected by software separately as input or output, and with/without internal pull-low and different chattering clocks for a HALT release /interrupt trigger in order to reduce the bounce of the key scan. The pull-low of the IOC will be masked off for those pins defined as output pins. The IOD port can be selected by software separately as input or output. The IOD port can be used as a pseudo serial output port. The initial state of all I/O ports is the standard input state, and IOA and C have pull-low. Before setting the I/O ports from input to output, execute the output function first to ensure the output state. Resistor to frequency converter We use an RC oscillation circuit and a 16-bit counter to calculate the relative resistance of temperature and humidity sensor. The diagram is shown below:
ELP RTP RT ENX EHM RH TMS
RHM
Timer & R/F Controller
PH9 MRF
FIN ERR Freq. CL LD
Rref RR
ENX CX FIN
Freq.
CL
LD
16-Bit Counter
CX
4-Bit Data Bus
There are 2 methods for measuring the input frequency. First, set FIN (i.e. CX) as the clock input and use timer 2 or the software directly as interval control. Second, if the FIN (CX) frequency is too low (either because of a poor resolution for a fixed interval or a longer interval for better resolution but a longer read-out rate, ex.10 seconds per read-out), you can switch the measure mode to set FIN (CX) as the interval control. It will
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enable the counter from the first FIN rising edge to the next rising edge, then will generate an interrupt. It may also use FREQ (internal frequency generator output) as clock input, hence counting the CX interval. For measuring the resistor value of the temperature and humidity sensor, we must first measure the frequency of Rref, then the frequency of Sensor: Fref= K / Rref CX and Fsensor= K / Rsensor CX, hence Rsensor = Rref * Freq / Fsensor. The CX input can be used as a clock counter. Analog-to-Digital converter The diagram is shown below:
LHCP ENCP AN1 ADF1
AN2 ADF2
AN3 ADF3
AN4
2 1 Analog Switch 2 1 Analog Switch LBR Low Battery Reference 4-Bit Ladder DAC 0123
ADF4
ENLBR ENDAC MDA
DAC
MPW1
6 / 8-Bit PWM DAC 0123 4567
MPW1
MPW2
6 / 8-Bit PWM DAC 0123 4567
MPW2
The use of these blocks is illustrated below: Comparator: Sets negative input as AN4, compare with AN1, 2, 3. 4-bit ADC: Sets negative input as internal 4-bit DAC, positive input as AN4, software control for AN1, 2, 3, 4 analog value archive. Low battery detector: Sets negative input as internal 4-bit DAC, positive input as LBR (low battery reference). If the DAC level is lower than LBR, it means there is a low-battery condition. PWM DAC output: With an external RC network, 6-bit or 8-bit PWM DAC can be used. 6-bit/ 8-bit ADC: Sets negative input as AN4, connects from PWM with an external RC network. You can get analog value from AN1, 2, 3. Supply voltage measurement: Sets negative input as AN4, connects from PWM with an external RC network, positive input is LBR. If comparative data is N, the supply voltage is LBR (about 1.26V) * 255 / N. Note: The internal 4-bit DAC level is 1/32 VDD for 0, 3/32 for 1, 29/32 for E and 31/32 for F. The level of 6-bit PWM is 0/63, 1/63, 62/63 and 63/63, and the level of 8-bit PWM is 0/255, 1/255, 254/255 and 255/255.
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An example of ADC timing is shown below:
TCK4 IR SW (LBR/AN4) SW (AN4/DAC) En LBR SAD 1Bh LBR DAC SAD 28h LBR DAC SAD 11h AN4 DAC SAD 20h
AN4 DAC
En DAC LHCP ENCP T1h
Note: Power Supply = 1.2V Power Supply = 2.4V
T1h needs 5ms T1h needs 10 s
EL-light Sets ELC and ELP clock and duty cycle using ELC X instruction, then turn on and off ELC and ELP output by SF X and RF X instruction. With external transistor, diode, inductor and resistor, we can pump the EL panel to AC 100~250V.
L1 D1 R1 ELP
Q1 EL-plane
R2 ELC
Q2
LIT
ELP
ELC
When the EL-light is turned on, the ELC will turn on before ELP, but when the EL-light is off, the ELP and ELC will turn off after the next falling edge of ELC in order to make sure no voltage is left on the EL plane. Timer The 6-bit programmable timer can select PH3/PH9/PH15/FREQ (Timer 2 can also select PH5/PH7/PH11/ PH13 by TM2X instruction) as the clock source. When it underflows, HALT release signals are generated.
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Predivider The predivider is a 15-sage counter that uses PH0 as clock source. The output of T-FF is changed when the input signal is changed from H to L. PH11~15 are reset to L when PLC 100H instruction is executed, power-on reset or external reset is used. When PH14 is changed from H to L, the HALT release signal is generated. Alarm/frequency/melody There is an 8-bit programmable counter and an 8-bit envelope control for alarm, frequency or melody output from BZ/BZB. The frequency counter can use software to select 1/2 duty, 1/3 duty,1/4 duty drive modes.
Frequency
1/2 Duty Frequency
1/3 Duty Frequency
1/4 Duty Frequency
INT function The INT pin can be selected by mask option as pull-high/pull-low or none, and as a rising edge/falling edge trigger. Watchdog Timer The watchdog timer automatically generates a device reset when it overflows. The interval of overflow is 8/64/512 x PH10 (set by mask option). You can use software to enable and disable this function. The watchdog enable flag will be disabled by power on reset or reset pin reset condition, but cannot be disabled by watchdog reset itself. HALT function The HALT instruction disables all clocks except the predivider, timer, frequency counter, PWM, EL-light generator and chattering clock in order to minimize the operating current. STOP function The STOP instruction disables all clocks to minimize the standby current, so only two external factors (INT, IOA/IOC) can release the stop condition.
Instruction Table
Instruction NOP LCT Lz, Ry LCB Lz, Ry LCP Lz, Ry LCD Lz, @HL OPA Rx OPAS Rx, D OPB Rx Machine Code 0000 0000 0000 0000 0000 001Z ZZZZ YYYY 0000 010Z ZZZZ YYYY 0000 011Z ZZZZ YYYY 0000 100Z ZZZZ 0000 0000 1010 0XXX XXXX 0000 1011 DXXX XXXX 0000 1100 0XXX XXXX No Operation Lz { 7SEG Lz Lz Lz { 7SEG Ry , AC T@HL Rx Rx0, Rx1, D, Pulse Rx Function Ry} Ry} Flag/Remark
Port(A) A1, 2, 3, 4 Port(B)
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Instruction OPC Rx OPD Rx OPDS Rx FRQ Rx, D Machine Code 0000 1101 0XXX XXXX 0000 1110 0XXX XXXX 0000 1111 DXXX XXXX 0001 00DD 0XXX XXXX Port(C) Port(D) D1, 2, 3, 4 Function Rx Rx Rx0, Rx1, D, Pulse Flag/Remark
FRQ D,@HL FRQX D,X MVL Rx MVH Rx MPW1 Rx MPW2 Rx ADC Rx ADC @HL ADC* Rx ADC* @HL SBC Rx SBC @HL SBC* Rx SBC* @HL ADD Rx ADD @HL ADD* Rx ADD* @HL SUB Rx SUB @HL SUB* Rx SUB* @HL ADN Rx ADN @HL ADN* Rx ADN* @HL AND Rx AND @HL AND* Rx AND* @HL EOR Rx EOR @HL EOR* Rx EOR* @HL
0001 01DD 0000 0000 0001 10DD XXXX XXXX 0001 1100 0XXX XXXX 0001 1101 0XXX XXXX 0001 1110 0XXX XXXX 0001 1111 0XXX XXXX 0010 0000 0XXX XXXX 0010 0000 1000 0000 0010 0001 0XXX XXXX 0010 0001 1000 0000 0010 0010 0XXX XXXX 0010 0010 1000 0000 0010 0011 0XXX XXXX 0010 0011 1000 0000 0010 0100 0XXX XXXX 0010 0100 1000 0000 0010 0101 0XXX XXXX 0010 0101 1000 0000 0010 0110 0XXX XXXX 0010 0110 1000 0000 0010 0111 0XXX XXXX 0010 0111 1000 0000 0010 1000 0XXX XXXX 0010 1000 1000 0000 0010 1001 0XXX XXXX 0010 1001 1000 0000 0010 1010 0XXX XXXX 0010 1010 1000 0000 0010 1011 0XXX XXXX 0010 1011 1000 0000 0010 1100 0XXX XXXX 0010 1100 1000 0000 0010 1101 0XXX XXXX 0010 1101 1000 0000
FREQ Rx, AC DD=00: 1/4 Duty DD=01: 1/3 Duty DD=10: 1/2 Duty T@HL FREQ FREQ L H Rx Rx Rx , AC Rx , AC Rx+AC+CF @HL+AC+CF Rx+AC+CF @HL+AC+CF Rx+ACB+CF @HL+ACB+CF Rx+ACB+CF @HL+ACB+CF Rx+AC @HL+AC Rx+AC @HL+AC Rx+ACB+1 @HL+ACB+1 Rx+ACB+1 @HL+ACB+1 Rx+AC @HL+AC Rx+AC @HL+AC Rx AND AC @HL AND AC Rx AND AC @HL AND AC Rx EXOR AC @HL EXOR AC Rx EXOR AC @HL EXOR AC Ver. 0.0 CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF X
PWM1 PWM2 AC AC AC, Rx AC, @HL AC AC AC, Rx AC, @HL AC AC AC,Rx AC, @HL AC AC AC, Rx AC,@HL AC AC AC, Rx AC,@HL AC AC AC, Rx AC,@HL AC AC AC, Rx AC,@HL
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Instruction OR Rx OR @HL OR* Rx OR* @HL ADCI Ry,D ADCI* Ry,D SBCI Ry,D SBCI* Ry,D ADDI Ry,D ADDI* Ry,D SUBI Ry,D SUBI* Ry,D ADNI Ry,D ADNI* Ry,D ANDI Ry,D ANDI* Ry,D EORI Ry,D EORI* Ry,D ORI Ry,D ORI* Ry,D INC* Rx INC* @HL DEC* Rx DEC* @HL IPA Rx IPB Rx IPC Rx IPD Rx MAF Rx Machine Code 0010 1110 0XXX XXXX 0010 1110 1000 0000 0010 1111 0XXX XXXX 0010 1111 1000 0000 0011 0000 DDDD YYYY 0011 0001 DDDD YYYY 0011 0010 DDDD YYYY 0011 0011 DDDD YYYY 0011 0100 DDDD YYYY 0011 0101 DDDD YYYY 0011 0110 DDDD YYYY 0011 0111 DDDD YYYY 0011 1000 DDDD YYYY 0011 1001 DDDD YYYY 0011 1010 DDDD YYYY 0011 1011 DDDD YYYY 0011 1100 DDDD YYYY 0011 1101 DDDD YYYY 0011 1110 DDDD YYYY 0011 1111 DDDD YYYY 0100 0000 0XXX XXXX 0100 0000 1000 0000 0100 0001 0XXX XXXX 0100 0001 1000 0000 0100 0010 0XXX XXXX 0100 0100 0XXX XXXX 0100 0111 0XXX XXXX 0100 1000 0XXX XXXX 0100 1010 0XXX XXXX AC AC AC, Rx AC,@HL AC AC, Ry AC AC, Ry AC AC, Ry AC AC, Ry AC AC, Ry AC AC, Ry AC AC, Ry AC AC, Ry AC, Rx AC, @HL AC, Rx AC, @HL AC, Rx AC, Rx AC, Rx AC, Rx AC,Rx Function Rx OR AC @HL OR AC Rx OR AC @HL OR AC Ry+D+CF Ry+DB+CF Ry+DB+CF Ry+D Ry+D Ry+DB+1 Ry+DB+1 Ry+D Ry+D Ry AND D Ry AND D Ry EXOR D Ry EXOR D Ry OR D Ry OR D Rx+1 @HL+1 Rx-1 @HL-1 Port(A) Port(B) Port(C) Port(D) STS1 B3: CF B2: AC=0 B1: (No use) B0: (No use) B3: (No use) B2: SCF2(HRx) B1: SCF1(CPT) B0: BCF B3: SCF7(PDV) B2: PH15 B1: SCF5(TMR1) B0: SCF4(INT) B3: SCF9(RFC) B2: SCF0(APT) B1: SCF6(TMR2) B0: (No use) Ver. 0.0 CF CF CF CF CF CF CF Ry+D+CF CF Flag/Remark
MSB Rx
0100 1011 0XXX XXXX
AC,Rx
STS2
MSC Rx
0100 1100 0XXX XXXX
AC,Rx
STS3
MCX Rx
0100 1101 0XXX XXXX
AC,Rx
STS3X
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Instruction MSD Rx Machine Code 0100 1110 0XXX XXXX AC,Rx Function STS4 Flag/Remark B3: (No use) B2: RFOVF B1: WDF B0: CSF B3: ADF4 B2: ADF3 B1: ADF2 B0: ADF1
MDX Rx
0100 1111 0XXX XXXX
AC,Rx
STS4X
SR0 Rx SR1 Rx SL0 Rx SL1 Rx DAA DAA* Rx DAA* @HL DAS DAS* Rx DAS* @HL LDS Rx,D LDH Rx,@HL LDH* Rx,@HL LDL Rx,@HL LDL* Rx,@HL MRF1 Rx MRF2 Rx MRF3 Rx MRF4 Rx STA Rx STA @HL LDA Rx LDA @HL MRA Rx MRW @HL,Rx MWR Rx,@HL MRW Ry,Rx MWR Rx,Ry JB0 X
0101 0000 0XXX XXXX 0101 0001 0XXX XXXX 0101 0010 0XXX XXXX 0101 0011 0XXX XXXX 0101 0100 0000 0000 0101 0101 0XXX XXXX 0101 0101 1000 0000 0101 0110 0000 0000 0101 0111 0XXX XXXX 0101 0111 1000 0000 0110 0000 0XXX XXXX 0110 0001 0XXX XXXX 0110 0010 0XXX XXXX 0110 0011 0XXX XXXX 0110 0100 0XXX XXXX 0110 0101 0XXX XXXX 0110 0110 0XXX XXXX 0110 0111 0XXX XXXX 0110 1000 0XXX XXXX 0110 1000 1000 0000 0110 1100 0XXX XXXX 0100 1100 1000 0000 0110 1101 0XXX XXXX 0110 1110 0XXX XXXX 0110 1111 0XXX XXXX 0111 0YYY YXXX XXXX 0111 1YYY YXXX XXXX 1000 0XXX XXXX XXXX
ACn, Rxn AC3, Rx3 ACn, Rxn AC3, Rx3 ACn, Rxn AC0, Rx0 Can, Rxn AC0, Rx0 AC AC, Rx AC, @HL AC AC, Rx AC, @HL D AC, Rx
Rx(n+1) 0 Rx(n+1) 1 Rx(n-1) 0 Rx(n-1) 1 BCD(AC) BCD(AC) BCD(AC) BCD(AC) H(T@HL)
BCD(AC)
BCD(AC)
0101 1DDD DXXX XXXX AC, Rx
AC, Rx H(T@HL) HL HL + 1 AC, Rx L(T@HL) AC, Rx L(T@HL) HL @HL + 1 AC,Rx AC,Rx AC,Rx AC,Rx Rx @HL AC AC CF AC,Rx AC,Ry PC X 15 AC AC Rx @HL Rx3 Rx @HL Rx if AC0 = 1 Ver. 0.0 CF RFC3-0 RFC7-4 RFC11-8 RFC15-12
AC,@HL
AC,Rx Ry
Preliminary
APU428
Instruction JB1 X JB2 X JB3 X JNZ X JNC X JZ X JC X CALL X JMP X RTS Machine Code 1000 1XXX XXXX XXXX 1001 0XXX XXXX XXXX 1001 1XXX XXXX XXXX 1010 0XXX XXXX XXXX 1010 1XXX XXXX XXXX 1011 0XXX XXXX XXXX 1011 1XXX XXXX XXXX 1100 0XXX XXXX XXXX 1101 0XXX XXXX XXXX 1101 1000 0000 0000 PC PC PC PC PC PC PC X X X X X X X PC+1 Function Flag/Remark if AC1 = 1 if AC2 = 1 if AC3 = 1 if AC 0 if CF = 0 if AC = 0 if CF = 1
STACK PC X PC PC X
STACK
CALL Return
SCC X
1101 1001 0X0X 0XXX
SCA X
1101 1010 00XX 0000
SAD X
1101 1011 00XX XXXX
SPA X SPB X SPC X SPD X TMS Rx TMS @HL
1101 1100 000X XXXX 1101 1101 0000 XXXX 1101 1110 000X XXXX 1101 1111 0000 XXXX 1110 0000 0XXX XXXX 1110 0001 0000 0000
X6 = 1: Cfq = BCLK X6 = 0: Cfq = PH0 X5 = 1: Cpw = BCLK X5 = 0: Cpw = PH0 X,4 = 1: Set P(A) X,4 = 0: Set P(C) X2,1,0=001: Cch = PH10 X2,1,0=010: Cch = PH8 X2,1,0=100: Cch = PH6 X5: A1-4 Enable (SEF5) X4: C1-4 Enable (SEF4) X5: Enable Cmp. output X4: Latch Data to Cmp. X3=1: CP4(+) = LBR X3=0: CP4(+) = AN4 X2=1: CP1~4(-) = AN4 X2=0: CP1~4(-) = DAC X1: Enable LBR X0: Enable DAC X4: Set A4~1 Pull-Low X3~0: Set A4~1 I/O X3~0: Set B4~1 I/O X4: Set C4-1 Pull-Low /Low-Level-Hold X3~0: Set C4-1 I/O X3-0: Set D4~1 I/O Timer1 Rx, AC Timer1 T@HL
TMSX MDA Rx TM2 Rx TM2 @HL
X7,6=11: Ctm=FREQ X7,6=10: Ctm=PH15 X 1110 0010 XXXX XXXX X7,6=01: Ctm=PH3 X7,6=00: Ctm=PH9 X5~0: Set Timer1 Value 1110 0011 0XXX XXXX DAC Rx 1110 0100 0XXX XXXX 1110 0101 0000 0000 Timer2 Rx, AC Timer2 T@HL
Preliminary
16
Ver. 0.0
APU428
Instruction Machine Code Function X8,7,6=111 : Ctm=PH13 X8,7,6=110 : Ctm=PH11 X8,7,6=101 : Ctm=PH7 X8,7,6=000 : Ctm=PH5 X8,7,6=011 : Ctm=FREQ X8,7,6=010 : Ctm=PH15 X8,7,6=001 : Ctm=PH3 X8,7,6=000 : Ctm=PH9 X5~0: Set Timer2 Value X6: Enable HEF6(RFC) X4: Enable HEF4(TMR2) X3: Enable HEF3(PDV) X2: Enable HEF2(INT) X1: Enable HEF1(TMR1) X6: Enable IEF6(RFC) X4: Enable IEF4(TMR2) X3: Enable IEF3(PDV) X2: Enable IEF2(INT) X1: Enable IEF1(TMR1) X0: Enable IEF0(A,CPT) X8: Reset PH15~11 X6, 4~0: Reset HRF6, 4~0 X5: Enable Cx Control X4: Enable Timer2 Control X3: Enable Counter X2: Enable RH Output X1: Enable RT Output X0: Enable RR Output X6~4: Enable SRF6~4 Flag/Remark
TM2X X
1110 011X XXXX XXXX
SHE X
1110 1000 0XXX XXX0
SIE* X
1110 1001 0XXX XXXX
PLC X
1110 101X 0XXX XXXX
SRF X
1110 1100 00XX XXXX
SRE X FAST SLOW
1110 1101 X0XX 0000 1110 1110 0000 0000 1110 1111 0000 0000
ENX EHM ETP ERR SRF6 (A Port) SRF5 (HRF2) SRF4 (M Port)
SF X
1111 0000 X00X XXXX
RF X
1111 0100 X00X 0XXX
SF2 X
1111 1000 0000 0XXX
RF2 X
1111 1001 0000 0XXX
SCLK: High Speed Clock SCLK: Low Speed Clock X7: Reload Set X4: WDT Enable X3: HALT after EL LIGHT X2: EL LIGHT On X1: BCF Set X0: CF Set X7: Reload Reset X4: WDT Reset X2: EL LIGHT Off X1: BCF Reset X0: CF Reset X0: Reload Set X1: Dis-ENX Set X2: Close all segments X0: Reload Reset X1: Dis-ENX Reset X2: Release all Segments 17
RL1 WDF BCF CF RL1 WDF BCF CF RL2 DED RSOFF RL2 DED RSOFF Ver. 0.0
Preliminary
APU428
Instruction Machine Code Function X8,7,6=111: FREQ X8,7,6=100: DC1 X8,7,6=011: PH3 X8,7,6=010: PH4 X8,7,6=001: PH5 X8,7,6=000: DC0 X5~0 PH15~10 X8=1 BCLKX X8=0 PH0 X7,6=11 BCLK/8 X7,6=10 BCLK/4 X7,6=01 BCLK/2 X7,6=00 BCLK X5,4=11 1/1 X5,4=10 1/2 X5,4=01 1/3 X5,4=00 1/4 X3,2=11 PH5 X3,2=10 PH6 X3,2=01 PH7 X3,2=00 PH8 X1,0=11 1/1 X1,0=10 1/2 X1,0=01 1/3 X1,0=00 1/4 HALT operation STOP operation ELP - CLK BCLKX Flag/Remark ALM X 1111 101X XXXX XXXX
ELP - DUTY
ELC X
1111 110X XXXX XXXX
ELC - CLK
ELC - DUTY
HALT STOP
1111 1110 0000 0000 1111 1111 0000 0000
Symbol description AC: Accumulator ACn: Accumulator bit-n X: Address Rx: Memory of address X WDF: Watchdog timer enable flag HL: Index register BCLK: System clock address IEFn: Interrupt enable flag SRFn: Stop release enable flag SCFn: Start condition flag Cch: Clock source of chartering detector TMR: Timer overflow release flag SEFn: Switch enable flag FREQ: Frequency generator setting value ADF: ADC flag DAC: Digital-to-analog converter output signal LBR: Low-battery voltage reference H: High address of index HT@HL: High nibble of index ROM
D: PC: CF: Rxn: Ry: BCF: @HL: HRFn: HEFn: Cfq: Ctm: PDV: Lz: T@HL: CSF:
Immediate data Program counter Carry flag Memory bit-n of address X Memory of working register Y Back-up flag Memory of index RAM HALT release flag HALT release enable flag Clock source of frequency generator Clock source of timer Predivider LCD latch Memory of index ROM Clock source flag
L: Low address of index RFOVF: RFC overflow flag LT@HL: Low nibble of index ROM
Preliminary
18
Ver. 0.0

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