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LapCoderTM UR5HCFJ8 Low-Power Keyboard Encoder for Portable Systems
HID & SYSTEM MANAGEMENT PRODUCTS, KEYCODERTM FAMILY DESCRIPTION The LapCoder is a versatile, lowpower keyboard encoder for portable systems. The UR5HCFJ8 provides two bi-directional channels for communication with a BIOScompatible system as well as any optional keyboard-compatible devices, such as a 101/102 desktop keyboard.
TM
FEATURES * Interfaces the Fujitsu FKB7211 or other similar laptop/notebook keyboards to a BIOS-compatible systems * AT / PS/2-compatible * Interfaces an external keyboard / keypad or other 8042-compatible devices * Low-power, single IC suitable for 3V battery-operated systems * Implements all functions of an 101/102 keyboard with only 82-keys * Available in DIP, PLCC and Quad Flat packages * Custom versions available in small or large quantities
The UR5HCFJ8 fully supports the IBM standard keyboard communication protocol; each key press generates one of the scan codes designated in the IBM Technical Reference Manuals. The keyboard encoder handles the scanning, debounce, and encoding of 82 keys organized on an 8x16 matrix and supports embedded numeric keypad functions as well as alternate scan codes for specific keys, so that a keyboard with only 82 keys is able to emulate the functionality of a 101/102 keyboard. In addition to the system's keyboard communication port the UR5HCFJ8 provides a fully functional keyboard input port that can be used by a standard 82/101/102 keyboard or another 8042-compatible device, such as an external numeric keypad, an OCR, or a bar-code reader. Input from both the matrix and the external device is multiplexed and presented to the system as if it were coming from a single source. The features of UR5HCFJ8 make it ideal for use in PC/AT/PS/2 laptop/notebook designs that utilize the Fujitsu FKB7211 low-profile, fulltravel membrane keyboard.
APPLICATIONS * Laptop/Notebook * Portable Equipment * Industrial Keyboards PIN DESCRIPTIONS * POS Terminals * Public Information Kiosks
6 RP KD KC EKC EKD CL C0 C1 C2 C3 C4 7 1
R6 NL VX VXA _IRQ _RESET VCC OSCI OSC0 EKC1 NC 40 39
_RESET _IRQ VX NL R6 RP KD KC EKC EKD CL C0 C1 C2 C3 C4 C5 C6 C7 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32
VCC OSCI OSCO EKC1 R7 SL R5 R4 R3 R2 R1 R0 C8 C9 C10 C11 C12 C13 C14 C15
12
PLCC
34
17 18
23
29 28
R7 SL R5 R4 R3 R2 R1 R0 C8 C9 C10
DIP
31 30 29 28 27 26 25 24 23 22 21
NL NC VX C5 _IRQ C6 _RESET C7 NC GND NC NC VCC C15/KT C14 OSCI C13 OSCO C12 EKC1 C11 R7
R6 RP KD KC EKC EKD CL C0 C1 C2 C3
QFP
SL R5 R4 R3 R2 R1 R0 C8 C9 C10 C11
LapCoder is a trademark of Semtech Corp. All other trademarks belong to their respective companies.
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C4 C5 C6 C7 NC GND C15 C14 C13 C12 NC
ORDERING CODE
Package options 40-pin Plastic DIP 44-pin, Plastic PLCC 44-pin, Plastic QFP Pitch In mm's 2 54 mm 1.27 mm 0.8 mm TA = -40C to +85C UR5HCFJ8-P UR5HCFJ8-FN UR5HCFJ8-FB
FUNCTIONAL DIAGRAM
NL/CL/SL
3
Data Buffer
Status LEDs
Row Data Inputs EKC1 Interrupt Control Column Select Ouputs 16 Keyboard Encoder KC KD PC Communication Channel 8
R0R7
C0C15
EKC EKD
8042 Emulation (External Keyboard) Communication Channel
Mode Control
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FUNCTIONAL DESCRIPTION The UR5HCFJ8 consists functionally of six major sections (see Functional Diagram, previous page). These are the Keyboard Encoder, the Mode Control Unit, the PC Communication Channel, the Data Buffer, the Interrupt Control and the 8042 Emulation Channel. All sections communicate with each other and operate concurrently. KEYBOARD ENCODER The controller continuously scans a keyboard organized as an 8 row by 16 column matrix for a maximum of 128 keys. Smaller-size keyboards are supported provided that all unused row lines are pulled to Vcc. The IC selects 1 of the 16 column lines (C0-C15) every 512 mS and then reads the row data lines (R0R7). A key closure is detected as a 0 in the corresponding position of the matrix. A complete scan cycle for the entire keyboard takes approximately 9.2 mS. Each key found pressed is debounced for a period of 20 mS. Once the key is verified, the corresponding key code(s) are loaded into the transmit buffer of the PC Communication Channel.
PIN DEFINITIONS
Mnemonic VCC VSS OSCI OSCO _RESET EKC1 DIP 40 20 39 38 1 37 PLCC 44 22 43 42 1 41 QFP 38 17 37 36 41 35 Type I I I O I Name and Function Power Supply: +5V Ground Oscillator input Oscillator output Reset: Apply 0V to provide orderly start-up External Keyboard Clock 1: Connects to external keyboard Clock Line and is used to generate an interupt for every Clock Line transition. Tie to Vcc Tie to Vcc Reserved: Ties to Vcc Keyboard Clock: Connects to PC keyboard port clock line Keyboard Data: Connects to PC port data line External Keyboard Data: Connects to external keyboard Data Lne External Keyboard Clock: Connects to external keyboard Clock Line Interrupt Line: Reserved for low-power applications Row Data Inputs
VX VXA RP KC KD EKD ECK _IQR R0-R5 R6 R7 C0-C7 C8-C15 CL NL SL NC
3 6 8 7 10 9 2 29-34 5 36 12-19 28-21 11 4 35
4 3 7 9 8 11 10 2 32-37 6 39 13-17 19-21 31-24 12 5 38 18 23,40
43 2 4 3 6 5 42 27-32 1 34 8-15 26-23 21-18 7 44 33 16,22 39,40
I I I I/O I/O I/O I/O I I I I O O O O O O O
Column Select Outputs: Selects 1 of 16 columns
Caps Lock LED Num Lock LED Scroll Lock LED No Connects: These pins are unused.
Note: An underscore before a pin mnemonic denotes an active low signal.
Switch Matrix Encoding
Each matrix location is programmed to represent either a single key or a key combination of the IBM 101/102 standard keyboard.
Scan Code Table Sets
The UR5HCFJ8 supports all three scan code table sets. Scan Code Sets 1 and 2 are the default sets for AT/PS/2 systems. Scan Code Table Set 3 allows the user to program individual key attributes such as Make/Break and Typematic or Single-Touch Action. For more information, refer to the IBM Technical Reference Manuals.
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KEYBOARD ENCODER, (CON'T)
MODE CONTROL Operating modes are defined by the logic level of the mode pin in the Mode Control Unit.
Embedded Numeric Keypad
The UR5HCFJ8 implements an embedded numeric keypad. The Numeric Keypad Function is invoked by pressing the Num Lock Key.
N-Key Rollover
In this mode, the code(s) corresponding to each key press are transmitted to the host system as soon as that key is debounced, independently of the release of other keys. If a key is defined to be Typematic, the corresponding code(s) will be transmitted while that key is held pressed. When the key is released, the corresponding break code(s) are then transmitted to the host system. If the released key happens to be the most recently pressed, then Typematic Action is terminated. There is no limitation to the number of keys that can be held pressed at the same time. However, two or more key closures, occurring within a time interval of less than 5 mS, will set an error flag and will not be processed. This procedure protects against the effects of accidental key presses.
FN Key
A special FN Key has been implemented to perform the following functions while it is held pressed: * * * * Function Key F1 becomes F11 Function Key F2 becomes F12 Ctrl Left Key becomes Ctrl Right Alt Left Key becomes Alt Right
"Ghost" Keys
In any scanned contact switch matrix, whenever three keys defining a rectangle on the switch matrix are held pressed at the same time, a fourth key positioned on the fourth corner of the rectangle is sensed as being pressed. This is known as the "ghost" or "phantom" key problem. Although the problem cannot be totally Actual key presses eliminated without using external hardware, there are methods to neutralize its negative effects for most practical applications. Keys that are intended to be used in combinations or are likely to be pressed at the same "Ghost" Key time by a fast typist (i.e., keys located in adjacent positions on the keyboard) should be placed in the same row or column of the matrix, whenever possible. Shift keys (Shift, Alt, Ctrl) should not reside in the same row (or Figure 1: "Ghost" or "Phantom" Key Problem column) with any other keys. The UR5HCFJ8 has built-in mechanisms to detect the presence of "ghost" keys, thus eliminating the necessity of external hardware.
If Num Lock is set: * Embedded numeric keypad keys become regular keys. If Num Lock is not set: * Embedded numeric keypad keys provide the same codes as a numeric keypad when the Num Lock is not set (Arrow Keys, PgUp, PgDn, etc.)
Status LED indicators
The controller provides interfacing for three LED shift status indicators. All three pins are active low to indicate the status of the host system (Num Lock, Caps Lock and Scroll Lock). They are set by the system (AT/PS/2 protocol).
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SPECIAL HANDLING
PC COMMUNICATION The UR5HCFJ8 implements all the standard functions of communication with a BIOScompatible PC/XT or AT/PS/2 host system. Two lines, KC and KD, provide bi-directional clock and data signals. In addition, the UR5HCFJ8 supports all commands from and to the system, as described in the IBM Technical Reference Manuals. The following table shows the commands that the system may send and their values in hex.
Command Set/Reset Status Indicators Echo Invalid Command Select Alternate Scan Codes Invalid Command Read ID Set Typematic Rate/Delay Enable Default Disable Hex Value ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE Command Key Detection Error/Overrun Keyboard ID BAT Completion Code BAT Failure Code Echo Acknowledge (Ack) Resend Key Detection Error/Overrun Hex Value 00* 83AB AA FC EE FA FE FF**
Hot Plug-Ins of External Device
The UR5HCFJ8 will detect the presence of an external device. If an external keyboard or other device was not connected during power-on and is connected at a later time, the encoder will proceed with the normal reset routine in order to properly initialize the external keyboard. After communication has been established, the encoder will continue to check for the presence of the external keyboard. While the external device is connected, the encoder will not enter the sleep mode. If the device is disconnected at a later time, the encoder will become aware of it. If a subsequent connection takes place, the controller will reinitiate a reset sequence. This unique feature allows the user to connect or disconnect an external device at any time without having to reset the system.
*Code Sets 2 and 3 **Code Set 1 Table 3: Keyboard Commands to the System (AT/PS/2 protocol)
8042 Emulation Channel The UR5HCFJ8 fully emulates a system's keyboard port, available to a standard 82/101/102 external keyboard or other 8042-compatible device. Communication with a keyboard-compatible device is accomplished by clock and data lines via EKC and EKD pins, respectively. A third pin, EKC1, connects to the Clock Line and interrupts the controller whenever the external device initiates a communication session. When power is first applied, the controller proceeds with the standard reset sequence with the external device. Data and commands initiated from the external device are buffered in the controller's FIFO along with data from the scanned matrix, and then are presented to the system as if they were coming from a single source. After they are acknowledged, commands and data from the system are transmitted to the external device.
Shift Status LEDs
Shift Status LEDs (Num Lock, Caps Lock and Scroll Lock) indicate the status of the system and are controlled by commands sent from the system. Set/Reset Status Indicator commands from the system will be executed both by the external keyboard and the scanned matrix. For example, if the user presses the Caps Lock Key on either keyboard, the Caps Lock LED will be affected in both keyboards. The LED status indicators are properly set after every new connection of an external keyboard.
Set Default Set All Keys Typematic Make/Break Make Typematic/Make/Break Set Key Type Typematic Make/Break Make Resend
Reset FF Table 2: Keyboard Commands from the System (AT/PS/2 protocol)
These commands are supported in the AT/PS/2 protocol and can be sent to the keyboard at any time.The following table shows the commands that the keyboard may send to the system.
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KEY MAP FOR FKB7211 (UR5HCFJ8)
Columns (C0-C13) 6 7 8 (BkQt) Insert C B D T F7 7 Pad 7 R N F Y F8 8 Pad 8 G . (per) Pad . M Pad 0 J Pad 1 U Pad 4 F9 9 Pad 9 H
0 LCtrl*
1 Esc F1* 1
2 Tab Z CapLk A 3 F5 % 5 W
3 Fn
4 LAlt*
5 Space X V S 4 F6 6 E
9 Delete / Pad / , (com) K Pad 2 I Pad 5 F10 0 Pad * [
10 ArrLft
11 ArrDn ArrUp
12 LShift RShift
13 ArrRt End PgDn PgUp BkSpc PrtScr Pause Home
, (appos) Enter L Pad 3 O Pad 6 NumLk ; Pad + P Pad ScrLk
Rows (R0-R7)
F2 2 F4 F3 Q
- (dash) = ] \
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KEYBOARD LAYOUTS (US ENGLISH) Depending on the status of the Num Lock and the FN Key, the UR5HCFJ8 implements one of four keyboard layouts. (Key numbering of a standard 101/102 keyboard is shown.)
Layout A (Default layout)
110 Esc
F1
112
113
F2 F3
114
F4
115
F5
116
F6
117 F7
118
F8
119
F9
120
121
F10
90 NmLk
125
ScLk
124
PrSc Brk
126
2 1 16 Tab 30 CpsLck
110 Esc
3 2 3 18 W 31 A S 46F2 3 2 FN
113
4 4 19 E 32 D 47 F3 4 3 60 Alt E 32 S D 47 X C
114
F3
5 5 20 R 33 F 48 F4 C 4 5
115
6 6 21 T 34 G 49 F5 V 5 6
116
7 7 22 Y 35 H 50F6 B
117
8 8 23 U 36 J 51 F7 N
118
9 9 24 I 37 K 38
10 0 25 0 39 L
11
12
13
26 P 40
= [
27
15 BkSp 28
80 Home 85 PgUp 86 PgDn
126 Brk
17 Q
]
41
\
29
; /
12
,
43 Enter
125 124
PrSc
44 Shift 1 58
F1
112
114
52 119 53 120 54 121 55 90 F8 F9 F10 NmLk
2
Z
X
Ctrl 16 Tab 30 CpsLck 44 Shift
110 Esc58
17 Q 31 A 46 Z
F1
18 W
19 R 33
20
9 7 8 10 11 6 7 9 0 8 75 1 61 SPACE , Ins 23 21 22 24 25 26 T Y I 0 P U 35 G H 50 B
116
F5
M
,
.
57 ScLk Shift 13
[
40
76 Del 27
= ]
81 End 80 15 BkSp84 Home 89 79 83
28
\
29
85 PgUp 86 PgDn 81 End
Brk 126 89
34 F
36 J 51 N
F6 117 F7
37 K 52 M
118
F8 61
38 L 53
39
;
54 55
,
41
43 Enter 57 83
Layout B (Num Lock is set)
48 V
115
F4
49
,
119
.
,
F9
/
75121 F10 Ins 100
Shift 76 90 NmLk Del 12 79 ScLk
13
125
PrSc
112
Ctrl
1 16 Tab 30 CpsLck 44 Shift 58 Ctrl
FN
2
F2
2
113 60 Alt 3
120 1
124 84
4 3 4 19 E
5
SPACE 6 7 5 6
20 21 T 34 F G 49 V B 50 35
91 7 22 92 4 36 H 51 N 0 1 99 93 8
96
101 9 102 6 98 2 53
*
105
106
= [
27
15 BkSp 28
80 Home 85 PgUp 86 PgDn 81 End 89
17 Q 31 A 46 Z FN
18 W 32 S 47 X 60 Alt
97 5
R 33 D 48 C
Y
]
41
\
29
103 3
+
95
,
43 Enter 57 83
,
61
.
,
1
104
/
75 Ins 76 Del
Shift 79 84
SPACE
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KEYBOARD LAYOUTS (US ENGLISH) Depending on the status of the Num Lock and the FN Key, the LapCoderTM implements one of four keyboard layouts. (Key numbering of a standard 101/102 keyboard is shown.)
Layout C (FN key pressed)
110 Esc
F11
122
123
F12 F3
114
F4
115
F5
116
F6
117 F7
118
F8
119
F9
120
121
F10
90 NmLk
125
ScLk
124
PrSc Brk
126
2 1 16 Tab 30 CpsLck 44 Shift 64 Ctrl 17 Q 31 A 46 Z FN 2
3 3 18 W 32 S 47 X 62 Alt
4 4 19 E 33 D 48 C
5 5 20 R 34 F 49 V
6 6 21 T 35 G 50 B
7
91 Home 22 92
96
101 PgUp 102
100
12
13
*
105
[
27
= ]
41 28
15 BkSp
80 Home 85 PgUp 86 PgDn 81 End 89
97 5
Y 36 H 51 N 93 End 99 Ins
\
29
98
103 PgDn 104 Del
106
+
95
,
43 Enter 2 83
53
,
61
/
75 Ins 76 Del
Shift 79 84
SPACE
,
1
Layout D (Num Lock set and FN key pressed)
110 Esc F1
122
123
F2 F3
114
F4
115
F5
116
F6
117 F7
118
F8
119
F9
120
121
F10
90 NmLk
125
ScLk
124
PrSc Brk
126
2 1 16 Tab 30 CpsLck 44 Shift 64 Ctrl 17 Q 31 A 46 Z FN 2
3 3 18 W 32 S 47 X 62 Alt
4 4 19 E 33 D 48 C
5 5 20 R 34 F 49 V
6 6 21 T 35 G 50 B
7 7 22 Y 36 H 51 N
8 8 23 U 37 J 52 M
9 9 24 I 38 K 53
10 0 25 0 39 L
11
12
13
26 P 40
= [
27
15 BkSp 28
80 Home 85 PgUp 86 PgDn 81 End 89
]
41
\
29
;
54 55
,
43 Enter 57 83
,
61
.
,
1
/
75 Ins 76 Del
Shift 79 84
SPACE
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IMPLEMENTATION NOTES FOR THE UR5HCFJ8 The following notes pertain to the suggested schematics found on the next pages. The Built-in Oscillator on the UR5HCFJ8 requires the attachment of the 4.00 MHz Ceramic Resonators with built-in Load Capacitors.. You can use either an AVX, part number PBRC-1.00 BR; or a Murata part number CSTCC4.00MG ceramic resonator. It may also be possible to operate with the 4.00 MHz Crystal, albeit with reduced performance. Due to their high Q, the Crystal oscillator circuits start-up slowly. Since the LapCoderTM constantly switches the clock on and off, it is important that the Ceramic Resonator is used (it starts up much quicker than the Crystal). Resonators are also less expensive than Crystals. Also, if Crystal is attached, two Load Capacitors (33pF to 47pF) should be added, a Capacitor between each side of the Crystal and ground. In both cases, using Ceramic Resonator with built-in Load Capacitors, or Crystal with external Load Capacitors, a feedback Resistor of 1 Meg should be connected between OSCin and OSCout. Troubleshoot the circuit by looking at the Output pin of the Oscillator. If the voltage it half-way between Supply and Ground (while the Oscillator should be running) --- the problem is with the Load Caps / Crystal. If the voltage it all the way at Supply or Ground (while the Oscillator should be running) --there are shorts on the PCB. NOTE: when the Oscillator is intentionally turned OFF, the voltage on the Output pin of the Oscillator is High (at the Supply rail).
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SUGGESTED INTERFACING FOR THE LAPCODERTM UR5HCFJ8
Vcc Vcc 100K STATUS LEDs
1uF GND Vcc 1 RST
Vcc 44 Vcc 5 NL 12 CL SL C15 C14 C13 C12 C11 C10 C9 C8 COLUMN C7 SELECT C6 OUTPUTS C5 C4 C3 C2 C1 C0 C4A R7A R7 R6 R5 R4 R3 R2 R1 R0 24 25 26 27 28 29 30 31 21 20 19 17 16 15 14 13 18 40 39 6 37 36 35 34 33 32 CS15 CS14 CS13 CS12 CS11 CS10 CS9 CS8 CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 TO SWITCH MATRIX RDAT7 RDAT6 RDAT5 RDAT4 RDAT3 RDAT2 RDAT1 RDAT0 38
4.7K 4.7K 2K EKDAT EKBCLK
2K 11 10 41 Vcc 2 IRQ KC KD PC KEYBOARD PORT COMMUNICATIONS EKD EKC EKC1 8042 EMULATION PORT
44 Pin PLCC
KBCLK KBDAT 4 x 47 Pf
9 8
ROW DATA INPUTS GND 23 NC
OSCI LINE INTERFACE 43 1 MEG
OSCO 42
Vss 22 GND
RP VXA 7 3
VX 4 Vcc
Vcc Vcc 4.00 MHz Vcc
8 x 22K
22pF
GND
22pF
GND
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MECHANICALS FOR THE UR5HCFJ8-P
40
21 B L
1
20
A
C J N M F K
Seating Plane
Notes: 1. Positional tolerance of leads (D) shall be within 0.25 mm (0.010) at maximum material condition, in relation to the seating plane and each other. 2. Diminsion L is to the center of the leads when the leads are formed parallel. 3. Dimension B does not include mold flash.
H
G
D
MILLIMETERS
INCHES
DIM A B C D F G H J K L M N
MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 00 15 0 0.51 1.02
MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.015 0.135 0.600 BSC 00 15 0 0.020 0.040
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MECHANICALS FOR THE UR5HCFJ8-FN
N
Y BRK
D
L
44 Leads PLCC
M
B
0.18 (0.007) M T N S -P S L S -M S
U W Z1
D
0.18 (0.007)
M
T N S -P S L S -M S
Note 1
(Note 1) 44
1
P V A Z
0.18 (0.007)
M
T L S -M S N S -P S
X View D-D
G1
0.25 (0.010)
M
T N S -P S L S -M S
R
0.18 (0.007)
M
T L S -M S N S -P S
H C
+ +
0.18 (0.007) M T L S -M S N S -P S 0.18 (0.007) M T N S -P S L S -M S
E G
K1 K F
44 (Note 1)
0.18 (0.007) 0.18 (0.007)
M M
T L S -M S N S -P S T N S -P S L S -M S
J G1
0.25 (0.010)
M
Detail S
0.010 (0.004) T
Detail S
Seating Plane
MILLIMETERS INCHES
T L S -M S N S -P S
Notes: 1. Due to space limitation, the chip is represented by a general (smaller) case outline drawing rather than showing all 44 leads. 2. Datums L, M, N, and P determine where the top of the lead shoulder exits plastic body at mold parting line 3. DIM G1, true position to be measured at Datum T, Seating Plane 4. DIM R and U do not include mold protusion. Allowable mold protusion is 0.25 (0.010) per side. 5. Dimensioning and tolerancing per Ansi Y14.5M, 1982 6. Controlling dimension: Inch
DIM A B C E F G H J K R U V W X Y Z G1 K1 Z1
MIN MAX 17.40 17.65 17.40 17.65 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 0.64 16.51 16.66 16.51 16.66 1.07 1.21 1.07 1.21 1.07 1.42 - 0.50 20 10 0 15.50 16.00 1.02 20 10 0
MIN MAX 0.685 0.695 0.685 0.695 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 0.025 0.650 0.656 0.650 0.656 0.042 0.048 0.042 0.048 0.042 0.056 - 0.020 20 10 0 0.610 0.630 0.040 2 10 0
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MECHANICALS FOR THE UR5HCFJ8-FB
L
33 34 23
DS
B
22
DS
A,B,D
B
0.20 (0.008) M C A-B S 0.05 (0.002) A-B
A
L
B
V
0.20 (0.008)
M
H A-B S
Detail A
Detail A
44 1 11
12
D A
0.20 (0.008) M C A-B S 0.05 (0.002) A-B DS
Notes 1. Dimensioning and tolerancing per Ansi Y14.5-M, 1982 2. Controlling dimension: Millimeter 3. Datum Plane "H" is located at the bottom of the lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. Datums -A-, -B-, and -D- to be determined at Datum Plane -H-. 5. Dimensions S and V to be determined at seating plane -C-. 6. Dimensions A and B do not include Mold protusion. Allowable protusion is 0.25 (0.010) per side. Dimensions A and B do include mold mismatch and are determined at Datum Plane -H-. 7. Dimension D does not include Danbar protrusion. Allowable Danbar protrusion is 0.08 (0.003) total in excess of the D dimension at Maximum Material Condition. Danbar cannot be located on the lower radius or the foot.
MILLIMETERS INCHES
F S
0.20 (0.008)
M
H A-B S
DS
Base Metal
J
N
M T
Datum Plane
D
0.20 (0.008)
M
C A-B S
DS
R
Section B-B
DIM A B C D E F G H J K L M N Q R S T U V W X
H W X M
Detail C
K Q
Detail C
C C Seating Plane
E
H
Datum Plane
0.01 (0.004)
G H M
MIN MAX 9.90 10.10 9.90 10.10 2.10 2.45 0.30 0.45 2.00 2.10 0.30 0.40 0.80 BSC - 0.25 0.13 0.23 0.65 0.95 8.00 REF 50 10 0 0.13 0.17 00 70 0.13 .30 12.95 13.45 0.13 00 12.95 13.45 0.40 1.6 REF
MIN MAX 0.390 0.398 0.390 0.398 0.083 0.096 0.012 0.018 0.079 0.083 0.012 0.016 0.031 BSC - 0.010 0.005 0.009 0.026 0.037 0.315 REF 50 10 0 0.005 0.007 00 70 0.005 0.012 0.510 0.530 0.005 00 0.510 0.530 0.016 0.063 REF
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ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings Ratings Supply Voltage Input Voltage Current Drain per Pin (not including Vss or Vdd) Operating Temperature UR5HCFJ8-XX Storage Temperature Range Thermal Characteristics Characteristic Thermal Resistance Plastic DIP Plastic PLCC Symbol VDD VIN I TA TSTG Value -0.3 to +7.0 Vss -0.3 to VDD +0.3 25 T low to T high -40 to +85 -65 to +150 Unit V V mA C C
Symbol TJA
Value 60 70
Unit C per W
DC Electrical Characteristics (VDD=5.0 VDC +/-10%, VSS=0 VDC, Temperature Characteristic Symbol Min Output Voltage (I load<10A) VOL VOH VDD-0.1 Output High Voltage (I load=0.8mA) VOH VDD-0.8 Output Low Voltage (I load=1.6mA) VOL Input High Voltage VIH 0.7xVDD Input Low Voltage VIL Vss User Mode Current IPP Data Retention Mode (0 to 70C) VRM 2.0 Supply Current* (Run) IDD I/O Ports Hi-Z Leakage Current IIL Input Current IIN I/O Port Capacitance CIO *In a typical application circuit, including external A/D.
range=T low to T high unless otherwise noted) Typ Max Unit 0.1 V V V V V mA V mA A A pF
5 4.7
0.4 VDD 0.2xVDD 10 7.0 +/-10 +/- 1 12
8
Control Timing (VDD=5.0 VDC +/-10%, VSS=0 VDC, Temperature range=T low to T high unless otherwise noted) Characteristic Symbol Min Max Frequency of Operation fOSC Crystal Option 2.0 External Clock Option dc 2.0 Crystal Oscillator Startup Time fOP Crystal (FOSC/2) 2.0 External Clock Option dc 2.0 Cycle Time tCYC 1000 Crystal Oscillator Startup Time toxov 100 Stop Recovery Startup Time tiLCH 100 Reset Pulse Width tRL 8 Interrupt Pulse Width Low tLIH 125 Interrupt Pulse Period tiLIL *
Unit MHz
MHz
ns ms ms tcyc ns
OSC1Pulse Width
tOH,
TOL
90
tcyc ns
*The minimum period tiLIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tcyc.
Copyright Semtech, 1997-2001 DOC5-FJ8-DS-107
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UR5HCFJ8 BILL OF MATERIALS FOR PAGE 10 SCHEMATIC
UR7HCFJ8-XX Description Bare PCB PCB Capacitors: C1, C2 C3, C4 C5, C7 C6 C8, C9, C10, C11 ICs: U1 Connectors: J1 J2 J5 J6 JP1-JP2 E1, E2 Diode: D1-D8 LED: J4 Resistors: R1, R6, R7 R2, R3, R4 R5 R8, R9 R10, R11 R12 R13-R16 R20 Resistor Net: RP1, RP2, RP3 RP4 Crystal: Y1 Shunts: E1-S, JP1-S, JP2-S Socket: U1_S BOM Quantity 1 2 2 2 1 4 1 1 1 1 1 1 2 8 3 3 3 1 2 2 1 4 1 3 1 1 3 1 Generic Generic Generic Generic Generic Semtech Molex Molex AMP AMP AMP S.E. Generic King Bright Generic Generic Generic Generic Generic Generic Generic Generic CTS KOA ECS Solid Electronics McKenzie Manufacturer Part# PCB5-FJ8-100 Any Any Any Any Any UR7HCFJ8 39-51-3144 39-51-3084 640456-5 640456-6 103322-3 PH1-025-2G Any L113GDT Any Any Any Any Any Any Any Any 761-3-332G RKC82223G EC2-040-4.00 MJ-254M PLCC44P-T Description PCB for UR5EVB. Thru Hole .1uF Ceramic disk or Monolythic cap, THD 22pF, Ceramic disk cap, THD .01uF Ceramic disk cap, THD 10uF, 16V Tantalum Cap, THD 47pF Ceramic disk cap, THD LapCoderTM 14 pos, ZIF Conn, Straight 8 pos ZIF Conn, Straight 5 positions .1"ST/Header 6 positions .1"ST/HeaderJP1, JP2 Header, 2x3 positions, 1" Male Str Header 1x2 pos Diode, small signal, THD, DO-35 Rect LED, cross to SSL-LX2573GD, THD 1M Resistor, Carbon Film, THD 330 Ohm Resistor, Carbon Film 1M Resistor, Carbon Film 4.7K Resistor, Carbon Film, THD 2K Resistor, Carbon Film, THD 100K Resistor, Carbon Film, THD 47 Ohm Resistor, Carbon Film, THD 22K Resistor, Carbon Fil, THD 3.3K, 8 Resistor, 16 pins, THD, DIP 22K, 8 Resistor, 9 pins, THD, SIP 4.00MHz Low Profile Crystal, THD Standard Gold 2 Position Jumper 44PLCC THD Socket
Notes: J3 not installed. Install shunts as follow: JP1, JP2 between pins 2 & 3; also installs in E1 Updated 2000/08/01
Copyright Semtech, 1997-2001 DOC5-FJ8-DS-107
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For sales information and product literature, contact: HID & System Mgmt Division Semtech Corporation 568 Broadway New York, NY 10012 hidinfo@semtech.com http://www.semtech.com 212 226 2042 Telephone 212 226 3215 Telefax
Semtech Western Regional Sales 805-498-2111 Telephone 805-498-3804 Telefax Semtech Central Regional Sales 972-437-0380 Telephone 972-437-0381 Telefax Semtech Eastern Regional Sales 203-964-1766 Telephone 203-964-1755 Telefax Semtech Asia-Pacific Sales Office +886-2-2748-3380 Telephone +886-2-2748-3390 Telefax Semtech Japan Sales Office +81-45-948-5925 Telephone +81-45-948-5930 Telefax Semtech Korea Sales Sales +82-2-527-4377 Telephone +82-2-527-4376 Telefax Northern European Sales Office +44 (0)2380-769008 Telephone +44 (0)2380-768612 Telefax Southern European Sales Office +33 (0)1 69-28-22-00 Telephone +33 (0)1 69-28-12-98 Telefax Central European Sales Office +49 (0)8161 140 123 Telephone +49 (0)8161 140 124 Telefax
Copyright 1997-2001 Semtech Corporation. All rights reserved. KeyCoder, LapCoder, Zero-Power and Self-Power Management are trademarks of Semtech Corporation. Semtech is a registered trademark of Semtech Company. All other trademarks belong to their respective companies. INTELLECTUAL PROPERTY DISCLAIMER This specification is provided "as is" with no warranties whatsoever including any warranty of merchantability, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. A license is hereby granted to reproduce and distribute this specification for internal use only. No other license, expressed or implied to any other intellectual property rights is granted or intended hereby. Authors of this specification disclaim any liability, including liability for infringement of proprietary rights, relating to the implementation of information in this specification. Authors of this specification also do not warrant or represent that such implementation(s) will not infringe such rights.
Copyright Semtech, 1997-2001 DOC5-FJ8-DS-107
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