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IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
FEATURES:
* * * *
IDT5V2528/A
* * * * * * *
Operates at 3.3V VDD/AVDD and 2.5V/3.3V VDDQ 1:10 fanout 3-level inputs for output control External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal No external RC network required for PLL loop stability Configurable 2.5V or 3.3V LVTTL outputs tPD Phase Error at 100MHz to 166MHz: 150ps Jitter (peak-to-peak) at 133MHz and 166MHz: 75ps Spread spectrum compatible Operating Frequency: - Std: 25MHz to 140MHz - A: 25MHz to 167MHz Available in TSSOP package
DESCRIPTION:
The IDT5V2528 is a high performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
The IDT5V2528 inputs, PLL core, Y0, Y1, and FBOUT buffers operate from the 3.3V VDD and AVDD power supply pins. One bank of ten outputs provide low-skew, low-jitter copies of CLK. Of the ten outputs, up to seven may be configured for 2.5V or 3.3V LVTTL outputs. The number of 2.5V outputs is controlled by 3-level input signals G_Ctrl and T_Ctrl, and by connecting the appropriate VDDQ pins to 2.5V or 3.3V. The 3-level input signals may be hard-wired to high-mid-low levels. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. The outputs can be enabled or disabled via the G_Ctrl input. When the G_Ctrl input is mid or high, the outputs switch in phase and frequency with CLK; when the G_Ctrl is low, all outputs (except FBOUT) are disabled to the logic-low state. Unlike many products containing PLLs, the IDT5V2528 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the IDT5V2528 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVDD to ground.
FUNCTIONAL BLOCK DIAGRAM
28 G_Ctrl 1 3 TY0, VDDQ pin 4 26
T_Ctrl
TY1, VDDQ pin 25
24 TY2, VDDQ pin 25 MODE SELECT 17 TY3, VDDQ pin 15 16
TY4, VDDQ pin 15
13 TY5, VDDQ pin 11 12
TY6, VDDQ pin 11
CLK
6 PLL
10 TY7, VDDQ pin 11 20 Y0, VDD pin 21 19
FBIN
7
AVDD
5 22
Y1, VDD pin 21
FBOUT, VDD pin 21
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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c 2002 Integrated Device Technology, Inc.
JUNE 2003
DSC 5971/11
IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
T_Ctrl GND TY0 VDDQ AVDD CLK FBIN AGND GND TY7 VDDQ TY6 TY5 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 G_Ctrl GND TY1 VDDQ TY2 GND FBOUT VDD Y0 Y1 GND TY3 TY4 VDDQ
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDD, VDDQ, AVDD VI (2) VO(2) IIK (VI < 0) IOK (VO < 0 or VO > VDD) IO (VO = 0 to VDD) VDD or GND TSTG TJ Continuous Current Storage Temperature Range Junction Temperature 200 -65 to +150 +150 mA C C Continuous Output Current 50 mA Rating Supply Voltage Range Input Voltage Range Voltage Range applied to any output in the HIGH or LOW state Input Clamp Current Output Clamp Current Max. -0.5 to +4.6 -0.5 to +5.5 -0.5 to VDD+0.5 -50 50 mA mA Unit V V V
TSSOP TOP VIEW
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
CAPACITANCE(1)
Symbol CIN CO CL Description Input Capacitance VI = VDD or GND Output Capacitance VI = VDD or GND Load Capacitance 2.5V outputs Min Typ. 5 6 20 30 Max. Unit pF pF pF
-- -- -- --
-- -- -- --
3.3V outputs
NOTE: 1. Unused inputs must be held HIGH or LOW to prevent them from floating.
RECOMMENDED OPERATING RANGE
Symbol VDD, AVDD (1) VDDQ (1) TA Description Power Supply Voltage Power Supply Voltage Ambient Operating Temperature 2.5V Outputs 3.3V Outputs Min. 3 2.3 3 -40 Typ. 3.3 2.5 3.3 +25 Max. 3.6 2.7 3.6 +85 Unit V V C
NOTE: 1. All power supplies should operate in tandem. If VDD or VDDQ is at a maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.
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IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Terminal Name CLK(1) FBIN G_Ctrl(2) No. 6 7 28 Type I I 3-level Description Clock input Feedback input 3-level input for 2.5V / 3.3V Output Select/ Output bank enable. When G_Ctrl is LOW, all outputs except FBOUT are disabled to a logic-LOW state. When G_Ctrl is MID or HIGH, all outputs are enabled and switch at the same frequency as CLK (see OUTPUT SELECTION table). T_Ctrl(2) FBOUT TY (7:0) Y (1:0) AVDD(3) AGND VDD VDDQ GND 1 22 3, 10, 12, 13, 16, 17, 24, 26 19, 20 5 8 21 4, 11, 15, 25 2, 9, 14, 18 23, 27
NOTES: 1. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time of 1ms is required for the PLL to phase lock the feedback signal to the reference signal. 2. 3-level inputs will float to MID logic level if left unconnected. 3. AVDD can be used to bypass the PLL for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the outputs.
3-level O O O Power Ground Power Power Ground
3-level input for 2.5V / 3.3V Output Select (see OUTPUT SELECTION table) Feedback output 2.5V or 3.3V Clock outputs. 1, 2, 3, 5, or 7 of these outputs may be selected as 2.5V outputs (see OUTPUT SELECTION table). 3.3V Clock Outputs 3.3V Analog power supply. AVDD provides the power reference for the analog circuitry. Analog ground. AGND provides the ground reference for the analog circuitry. 3.3V Power supply 2.5V or 3.3V Power supply for TY outputs Ground
STATIC FUNCTION TABLE (AVDD = 0V)(1)
G_Ctrl L L Inputs T_Ctrl X X CLK L H H L running TY(7:0) L L H L running Outputs Y(1:0) L L H L running FBOUT L H H L running
OUTPUT SELECTION
G_Ctrl M M M H H H T_Ctrl L M H L M H TY(7:0) TY0 (2.5V) TY1 - TY7 (3.3V) TY1, TY2 (2.5V) TY0, TY3 - TY7 (3.3V) TY0 - TY2 (2.5V) TY3 - TY7 (3.3V) TY0 - TY4 (2.5V) TY5 - TY7 (3.3V) TY1 - TY7 (2.5V) TY0 (3.3V) TYo - TY7 (3.3V) VDDQ Configuration Pin 4 (2.5V) Pins 11, 15, 25 (3.3V) Pin 25 (2.5V) Pins 4, 11, 15 (3.3V) Pins 4, 25 (2.5V) Pins 11, 15 (3.3V) Pins 4, 15, 25 (2.5V) Pin 11 (3.3V) Pins 11, 15, 25 (2.5V) Pin 4 (3.3V) Pins 4, 11, 15, 25 (3.3V)
see OUTPUT SELECTION table
NOTE: 1. AVDD should be powered up along with VDD, before setting AVDD to ground, to put the control pins in a valid state.
DYNAMIC FUNCTION TABLE (AVDD = 3.3V)
Inputs G_Ctrl T_Ctrl L X L X see OUTPUT SELECTION table CLK L H L H TY(7:0) L L L H Outputs Y(1:0) L L L H FBOUT L H L H
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IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol VIK VIH VIL VIHH VIMM VILL VOH VOH VOL VOL I3 Parameter Input Clamp Voltage Input HIGH Level Input LOW Level Input HIGH Voltage Level(2) Input MID Voltage Level(2) Input LOW Voltage Level(2) Output HIGH Voltage Level (3.3V Outputs) Output HIGH Voltage Level (2.5V Outputs) Output LOW Voltage Level (3.3V Outputs) Output LOW Voltage Level (2.5V Outputs) 3-Level Input DC Current (G_Ctrl, T_Ctrl) Input Current Test Conditions II = -18mA CLK, FBIN CLK, FBIN 3-Level Inputs Only 3-Level Inputs Only 3-Level Inputs Only IOH = -100A IOH = -12mA IOH = -100A IOH = -12mA IOL = 100A IOL = 12mA IOL = 100A IOL = 12mA VIN = VDD VIN = VDD/2 VIN = GND VI = VDD or GND Min. 2 VDD - 0.6 VDD/2 - 0.3 VDD - 0.2 2.4 VDD - 0.1 2 Typ.(1) Unit V V 0.8 V V VDD/2 + 0.3 V 0.6 V V Max - 1.2
HIGH Level MID Level LOW Level
-50 -200
0.2 0.4 0.1 0.4 +200 +50 5
V V V
A A
II
NOTES: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. 2. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias floating inputs to VDD/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
POWER SUPPLY CHARACTERISTICS
Symbol IDDPD IDDA IDD IDDD Parameter Power Down Supply Current AVDD Supply Current Dynamic Power Supply Current Dynamic Power Supply Current per Output Test Conditions VDD = 3.6, VDDQ = 2.7V / 3.3V, AVDD = 0V VDD = AVDD = 3.6V, VDDQ = 2.7V / 3.3V, CLK = 0 or VDD VDD = AVDD = 3.6V, VDDQ = 2.7V / 3.3V, CL = 0pF VDD = AVDD = VDDQ = 3.6V CL = 30pF, CLK = 100MHz VDD = AVDD = 3.6V, VDDQ = 2.7V CL = 20pF, CLK = 100MHz Typ.(1) 8 3.5 500 15 12 Max 40 10 -- -- -- Unit A mA A/MHz mA
NOTE: 1. For nominal voltage and temperature.
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IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
INPUT TIMING REQUIREMENTS OVER OPERATING RANGE
5V2528 Min fCLOCK tLOCK Clock frequency Input clock duty cycle Stabilization time(1) 25 40% Max 140 60% 1 Min 25 40% 5V2528A Max 167 60% 1 ms Units MHz
NOTE: 1.Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - 5V2528(1)
Symbol tPHASE error tPHASE error - jitter(3) tSK1(0)(4) tSK2(0)(4) tSK3(0)(4,5) tJ tR tF tR tF Parameter(2) Phase Error from Rising Edge CLK to Rising Edge FBIN (100MHz-133MHz) Phase Error minus Jitter from Rising Edge CLK to Rising Edge FBIN (133MHz) Output Skew between 3.3V Outputs Output Skew between 2.5V Outputs Output Skew between 2.5V and 3.3V Outputs Cycle-to-Cycle Output Jitter (Peak-to-Peak) at 133MHz Duty Cycle Output Rise Time for 3.3V Outputs (20% to 80%) Output Fall Time for 3.3V Outputs (20% to 80%) Output Rise Time for 2.5V Outputs (20% to 80%) Output Fall Time for 2.5V Outputs (20% to 80%) Min. -150 -50 -- -- -- -75 45 0.8 0.8 0.5 0.5 Typ. -- -- -- -- -- -- -- -- -- -- -- Max. 150 50 150 150 200 75 55 2.1 2.1 1.5 1.5 Unit ps ps ps ps ps ps % ns ns ns ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - 5V2528A(1)
Symbol tPHASE error tPHASE error - jitter(3) tSK1(0)(4) tSK2(0)(4) tSK3(0)(4,5) tJ tR tF tR tF Parameter(2) Phase Error from Rising Edge CLK to Rising Edge FBIN (100MHz-166MHz) Phase Error minus Jitter from Rising Edge CLK to Rising Edge FBIN (166MHz) Output Skew between 3.3V Outputs Output Skew between 2.5V Outputs Output Skew between 2.5V and 3.3V Outputs 25MHz to 133MHz 133MHz to 166MHz Cycle-to-Cycle Output Jitter (Peak-to-Peak) at 166MHz Duty Cycle Output Rise Time for 3.3V Outputs (20% to 80%) Output Fall Time for 3.3V Outputs (20% to 80%) Output Rise Time for 2.5V Outputs (20% to 80%) Output Fall Time for 2.5V Outputs (20% to 80%) Min. -150 -50 -- -- -- -- -75 45 0.8 0.8 0.5 0.5 Typ. -- -- -- -- -- -- -- -- -- -- -- -- Max. 150 50 150 150 200 250 75 55 2.1 2.1 1.5 1.5 Unit ps ps ps ps ps ps % ns ns ns ns
NOTES: 1. All parameters are measured with the following load conditions: 30pF || 500 for 3.3V outputs and 20pF || 500 for 2.5V outputs. 2. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 3. Phase error does not include jitter. 4. All skew parameters are only valid for equal loading of all outputs. 5. Measured for VDDQ = 2.3V and 3V, 2.5V and 3.3V, or 2.7V and 3.6V.
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IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUIT AND VOLTAGE WAVEFORMS
From Output Under Test
From Output Under Test
CL=30pF(2)
500
CL=20pF(2)
500
Test Circuit for 3.3V Outputs
Test Circuit for 2.5V Outputs
VDD/2 CLK VDD/2 tPHASE ERROR CLK IDT5V2528/A CL (2) CF (4) FBIN 500 PCBTRACE VDDQ/2 Any TY (2.5V) VDDQ/2 tSK2(o) tR VDDQ/2 tF FBOUT Y, TY FBOUT or Any Y, TY (3.3V) Any Y, TY (3.3V) VDDQ/2 tR VDDQ/2 tSK1(o) VDDQ/2 tSK3(o)
80% 20% 80% 20%
FBIN
500 on each Y, TY output
tF
Any TY (2.5V)
PHASE ERROR AND SKEW CALCULATIONS(3,4)
NOTES: 1. All inputs pulses are supplied by generators having the following characteristics: PRR 100MHz ZO = 50, tR 1.2 ns, tF 1.2 ns. 2. CL includes probe and jig capacitance. 3. The outputs are measured one at a time with one transition per measurement. 4. Phase error measurements require equal loading at outputs Y, TY, and FBOUT. CF = CL - CFBIN - CPCBtrace; CFBIN 5pF.
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IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXX Device Type XX Package X Process
I
-40C to +85C (Industrial)
PG PGG 5V2528 5V2528A
Thin Shrink Small Outline Package TSSOP - Green 2.5V / 3.3V Phase-Lock Loop Clock Driver
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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