View 74LVT373_54122.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Philips Semiconductors Low Voltage Products
Objective specification
3.3 Volt ABT octal transparent latch (3-State)
74LVT373
FEATURES
* Designed for use in the 3.3V
high-performance market
* Latch-up protection exceeds 500mA per
JEDEC JC40.2 Std 17
independently by Enable (E) and Output Enable (OE) control gates. The data on the D inputs are transferred to the latch outputs when the Latch Enable (E) input is High. The latch remains transparent to the data inputs while E is High, and stores the data that is present one setup time before the High-to-Low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance "OFF" state, which means they will neither drive nor load the bus.
* Supports mixed-mode signal operation; 5V * Bus-hold inputs eliminate the need for
input and output voltages with 3.3V VCC external pull-up resistors to hold unused pins
* ESD protection exceeds 2000 V per MIL
STD 883 Method 3015 and 200 V per Machine Model
DESCRIPTION
The 74LVT373 device is designed specifically for low-voltage (3.3V) VCC operation, but can provide a TTL interface to a 5V system environment. The 74LVT373 high-performance BiCMOS device combines zero static and low dynamic power dissipation with high speed and high output drive. The 74LVT373 device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled
* Live insertion/extraction permitted * No bus current loading when output is tied
to 5V bus
* 8-bit transparent latch * 3-State output buffers * Zero-static power dissipation * Pin and function compatibility with ABT * AC and DC performance compatibility with
ABT
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COUT ICCZ PARAMETER Propagation delay Dn to Qn Input capacitance Output capacitance Total supply current CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC VI = 0V or VCC Outputs disabled; VCC =5.5V TYPICAL 4.2 4 7 50 UNIT ns pF pF A
ORDERING INFORMATION
PACKAGES 20-Pin Plastic SOL 20-Pin Plastic SSOP 20-Pin Plastic TSSOP TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C ORDER CODE 74LVT373D 74LVT373DB 74LVT373PW DRAWING NUMBER 0172D 1640B TBD
PIN DESCRIPTION
PIN NUMBER 1 3, 4, 7, 8, 13, 14, 17, 18 2, 5, 6, 9, 12, 15, 16, 19 11 10 20 SYMBOL OE D0-D7 Q0-Q7 E GND VCC Output enable input (active-Low) Data inputs Data outputs Enable input (active-High) Ground (0V) Positive supply voltage FUNCTION
July 1993
2
Philips Semiconductors Low Voltage Products
Objective specification
3.3 Volt ABT octal transparent latch (3-State)
74LVT373
FUNCTION TABLE
INPUTS OE L L L L L H H H= h= L= l= NC= X= Z= = E H H L Dn L H i h X INTERNAL REGISTER L H L H NC OUTPUTS Q0 - Q7 L H L H NC Enable and read register Latch and read register Hold OPERATING MODE
L X NC Z Disable outputs H Dn Dn Z High voltage level High voltage level one set-up time prior to the High-to-Low E transition Low voltage level Low voltage level one set-up time prior to the High-to-Low E transition No change Don't care High impedance "off" state High-to-Low E transition
LOGIC DIAGRAM
D0 3 D1 4 D2 7 D3 8 D4 13 D5 14 D6 17 D7 18
D
D
D
D
D
D
D
D
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
11 E 1 OE 2 Q0 5 Q1 6 Q2 9 Q3 12 Q4 15 Q5 16 Q6 19 Q7
July 1993
3
Philips Semiconductors Low Voltage Products
Objective specification
3.3 Volt ABT octal transparent latch (3-State)
74LVT373
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING -0.5 to +4.6 -18 -1.2 to +5.5 -50 -0.5 to +5.5 64 -65 to 150 UNIT V mA V mA V mA C
DC output diode current DC output voltage3
DC output current Storage temperature range
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER Min VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 0 2.7 0 2.0 0.8 -32 64 10 +70 LIMITS Max 3.6 VCC V V V V mA mA ns/V C UNIT
July 1993
4
Philips Semiconductors Low Voltage Products
Objective specification
3.3 Volt ABT octal transparent latch (3-State)
74LVT373
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIK Input clamp voltage VCC = 2.7V; IIK = -18mA VCC = 2.7 to 3.6V; IOH = -100A VOH High-level output voltage VCC = 2.7V; IOH = -8mA VCC = 3.0V; IOH = -32mA VCC = 2.7V; IOL = 100A VCC = 2.7V; IOL = 24mA VOL Low-level output voltage VCC = 3.0V; IOL = 16mA VCC = 3.0V; IOL = 32mA VCC = 3.0V; IOL = 64mA VCC = 3.6V; VI = VCC or GND VCC = 0 or 3.6V; VI = 5.5V II Input leakage current VCC = 3.6V; VI = 5.5V VCC = 3.6V; VI = VCC VCC = 3.6V; VI = 0 IOFF IHOLD Output off current Bus Hold current A or B ports IEX ICCH ICCL ICCZ ICC IPU/PD CI CO Additional supply current per input pin2 Power up/down 3-State output current3 Input capacitance Output capacitance Quiescent supply current Current into an ouptut in the High state when VO > VCC VCC = 0V; VI or VO = 0 to 4.5V VCC = 3V; VI = 0.8V VCC = 3V; VI = 2.0V VO = 5.5V; VCC = 3.0V VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0 VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0 VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 0 VCC = 3V to 3.6V; One input at VCC-0.6V, Other inputs at VCC or GND VCC 1.2V; VO = 0.5V to VCC; VI = GND or VCC; OE/OE = X VI = 3V or 0 VO = 3V or 0 4 11 0.13 3 0.13 75 -75 100 0.19 12 0.19 0.2 100 mA A pF pF mA Data pins4 Control pins VCC-0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 1 10 20 1 -5 100 A A A A A V V TYP1 MAX -1.2 V UNIT
NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25C. 2. This is the increase in supply current for each input at the specificed voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.3V with a transition time of up to 10msec. From VCC = 1.3V to VCC = 3.3V 0.3V a transition time of 100sec is permitted. X = Don't care. 4. Unused pins at VCC or GND.
July 1993
5
Philips Semiconductors Low Voltage Products
Objective specification
3.3 Volt ABT octal transparent latch (3-State)
74LVT373
AC CHARACTERISTICS
GND = 0V; tR = tF = 6ns; CL = 50pF; RL = 500, Tamb = -40C to +85C. LIMITS SYMBOL PARAMETER WAVEFORM MIN tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay An to Yn Output enable time OEn to Yn Output disable time OEn to Yn NO TAG NO TAG NO TAG VCC = 3.3V 0.3V TYP1 2.7 2.9 3.4 3.4 3.7 2.6 MAX VCC = 2.7V MAX ns ns ns UNIT
NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
E
VM
VM
VM
Dn
VM
VM
tw(H) tPHL
tPLH tPLH
tPHL
Qn
Qn
VM VM
VM
VM
Waveform 1. Propagation Delay, Enable to Output, and Enable Pulse Width
Dn
VM
ts(H)
E
VM
Waveform 3. Data Setup and Hold Times
OE
VM tPZH
VM tPHZ VOH -0.3V
Qn
VM
0V
Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
July 1993
EEEEEEEEEE E EEEEEEEEEE E EEEEEEEEEE E EEEEEEEEEE E EEEEEEEEEE E
VM VM VM th(H) ts(L) th(L) VM
EEE EEE EEE EEE EEE
Waveform 2. Propagation Delay for Data to Outputs
OE
VM tPZL
VM tPLZ
Qn
VM
VOL +0.3V 0V
Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
6
Philips Semiconductors Low Voltage Products
Objective specification
3.3 Volt ABT octal transparent latch (3-State)
74LVT373
TEST CIRCUIT AND WAVEFORM
VCC
6V
90% OPEN NEGATIVE PULSE VM 10% tTHL (tF)
tW VM 10%
90%
AMP (V)
VIN PULSE GENERATOR RT D.U.T
VOUT
RL
GND
0V tTLH (tR) tTHL (tF) 90% VM 10% tW 0V AMP (V)
CL
RL POSITIVE PULSE 10%
tTLH (tR) 90%
Test Circuit for 3-State Outputs
VM
SWITCH POSITION
TEST tPHZ/tPZH tPLZ/tPZL tPLH/tPHL SWITCH GND 6V open
VM = 1.5V Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS FAMILY Amplitude 74LVT VCC(Min) Rep. Rate 1MHz tW tR tF
500ns 2.5ns 2.5ns
July 1993
7

▲Up To Search▲

Price & Availability of 74LVT373

	To Download 74LVT373 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .