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| VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7961 Features 3.125Gb/s PECL Limiting Amplifier with LOS Detect Applications * SONET/SDH at 622Mb/s, 1.244Gb/s, 2.488Gb/s, and 3.125Gb/s * Full-Speed Fibre Channel (1.062Gb/s) * Small Form Factor (SFF) Receivers * ATM Optical Receivers * 3.3V or 5V Power Supply * Typical Supply Current of 32mA * Positive Emitter-Coupled Logic (PECL) Outputs * Optional Output Squelch * Loss of Signal Detect * Output Offset Correction * Rise/Fall Times Faster than 100ps * Packages: TSSOP-16, Bare Die General Description The VSC7961 is a single-supply limiting amplifier with Loss of Signal (LOS) detect for SONET/SDH and Fibre Channel applications up to 3.125Gb/s. The VSC7961 provides a constant output signal swing for a wide range of input voltages and has Positive Emitter-Coupled Logic (PECL). The VSC7959 provides the same functionality as the VSC7961 with Current-Mode Logic (CML) outputs. Key features of the VSC7961 are its RMS power detectors for programmable LOS detection, optional output squelch, adjustable output levels, excellent jitter performance, and fast edge rates. The VSC7961 is available in die form or in a TSSOP-16 package. Block Diagram VSC7961 VCC 8k LOS VCC 8k TH RMS Power Detect and Control IN+ LOS SQUELCH Output Control LEVEL OUT+ 100 IN- OUT- Lowpass Filter 10pF CZ1 CZ2 Offset Correction G52360-0, Rev 2.0 02/09/01 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 1 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 3.125Gb/s PECL Limiting Amplifier with LOS Detect VSC7961 Electrical Characteristics Table 1: DC Specifications Symbol VCC ICC IEE ICCSQ IEESQ ISQ PSSR Parameter Power Supply Voltage Power Supply Current(1) Power Supply Current(1) Power Supply Current when Squelched(1) Power Supply Current when Squelched(1) Squelch Input Current Power Supply Rejection Ratio Min 3.135 Typ 59 62 31 35 58 62 20 23 Max 5.5 Units V mA mA mA m mA mA mA mA Conditions VCC = 3.3V VCC = 5V VCC = 3.3V VCC = 5V VCC = 3.3V VCC = 5V VCC = 3.3V VCC = 5V f < 2MHz 0 20 400 A dB NOTE: (1) See Figure 4 for supply current measurement setup. Table 2: DC Specifications Symbol VIN JD JR tR, tF VN RDIFF fL VSQ VOH VOL ZO Parameter Data Rate Input Voltage Range Deterministic Jitter Random Jitter Rise and Fall Times Input Referred Noise Differential Input Resistance Low Frequency Cutoff Output Signal When Squelched PECL Output High Voltage PECL Output Low Voltage Output Resistance Min 3.125 10 Typ Max 1200 25 8 100 230 Units Gb/s mV ps ps ps V MHz kHz mV mV mV mV mV Conditions Peak-to-peak See Note 1 See Note 2, RMS 20% to 80% RMS, IN+ to ININ+ to INCZ open CZ = 0.1F Output AC-coupled Squelched Squelched Single-ended 55 100 2 2 -1025 -1810 100 20 -850 -850 -1620 -1620 NOTES: (1) Deterministic jitter measured peak-to-peak with K28.5 pattern. (2) Random jitter measured with minimum input. Page 2 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com G52360-0, Rev 2.0 02/09/01 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7961 Table 3: Loss of Signal Specifications Symbol HLOS ILOS VTHA 3.125Gb/s PECL Limiting Amplifier with LOS Detect Parameter LOS Hystersis LOS Assert/Deassert Time LOS Assert Threshold Min 3.1 0.22 12.8 Typ 3.3 0.25 8.2 19.8 57.2 11.4 Max 5.5 0.28 21.8 Units dB s mV mV mV mV Conditions HLOS = 20 log (VTHD/VTHA) RTH = 2.5k RTH = 7k RTH = 20k RTH = 2.5k RTH = 7k RTH = 20k ILOS = -30A ILOS = +1.2A VTHD VLOSH VLOSL LOS Deassert Threshold LOS Output HIGH Voltage LOS Output LOW Voltage 26.2 3.3 29.0 75.2 0.168 31.6 mV mV V V Table 4: Loss of Signal Truth Table SQUELCH High Low High Low LOS Low High Low Low Output Off On On On Absolute Maximum Ratings(1) Power Supply Voltage (VCC)............................................................................................................. -0.5V to +6V Maximum Junction Temperature Range .........................................................................................................TBD Storage Temperature Range (TS)................................................................................................. -55C to +150C NOTE: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Recommended Operating Conditions Positive Voltage Rail (VCC).................................................................................................................. 3.3V or 5V Junction Temperature Range (TJ)................................................................................................ -40C to +100C Ambient Temperature Range (TA)................................................................................................. -40C to +85C G52360-0, Rev 2.0 02/09/01 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 3 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 3.125Gb/s PECL Limiting Amplifier with LOS Detect VSC7961 Package Pin Descriptions Figure 1: Pin Diagram Top View TSSOP-16 Package CZ1 CZ2 GND IN+ INGND NC TH 1 2 3 4 5 6 7 8 16 15 14 13 NC SQUELCH VCC OUT+ OUTVCC LOS LOS VSC7961 12 11 10 9 Table 5: Pin Identifications Pin Name CZ1 CZ2 GND IN+ INGND NC TH LOS LOS VCC OUTOUT+ VCC SQUELCH NC Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description Offset Correction Loop Capacitor. Place capacitor between this pin and CZ2 to alter time constant of offset correction loop. See Detailed Description section. Offset Correction Loop Capacitor. Place capacitor between this pin and CZ1 to alter time constant of offset correction loop. See Detailed Description section. Supply Ground Noninverted Input Signal Inverted Input Signal Supply Ground This pin may be either connected to ground of left unconnected. This pin does not effet the performance of the device. Loss of Signal (LOS) Threshold. Connect a resistor from this pin to ground to set the input signal level at which LOS outputs will be asserted. See Application Information section. Inverted Loss of Signal Output. LOS is HIGH for input signals above the threshold programmed by TH. See Detailed Description section. Noninverted Loss of Signal Output. LOS is LOW for input signals above the threshold programmed by TH. See Detailed Description section. Power Supply Inverted Data Output Noninverted Data Output Power Supply Squelch Input. Squelch is disabled if this pin is unconnected or set LOW. When SQUELCH is HIGH, OUT+ and OUT- are forced to static levels. See Detailed Description section. No Connection Page 4 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com G52360-0, Rev 2.0 02/09/01 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7961 Bare Die Descriptions 3.125Gb/s PECL Limiting Amplifier with LOS Detect Figure 2: Pad Assignments 1597m (0.06287") Pad1 CAZ1 Pad 2 CAZ2 Pad 3 GNDA Pad 4 LAINP Pad 16 NC Pad 15 SQ Pad 14 VCCA Pad 13 LAOP 1597m (0.06287") VSC7961 Pad 5 LAINM Pad 6 GNDA Pad 7 NC Pad 8 TH Pad 9 LOS Pad 12 LAOM Pad 11 VCCA Pad 10 LOS Die Size: Pad Pitch: Pad Passivation Opening: 1597m x 1597m (0.06287" x 0.06287") 180m (0.00709") 95m x 95m (0.00374" x 0.00374") The back side of the die may either be left floating or connected ot ground. G52360-0, Rev 2.0 02/09/01 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 5 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 3.125Gb/s PECL Limiting Amplifier with LOS Detect Table 6: Pad Coordinates Pad Name CZ1 VSC7961 Pin Name Pad/Pin Number 1 Coordinates (m) Description X 270.525 Y 1359.05 Offset Correction Loop Capacitor. Place capacitor between this pin and CZ2 to alter time constant of offset correction loop. See Detailed Description section. Offset Correction Loop Capacitor. Place capacitor between this pin and CZ1 to alter time constant of offset correction loop. See Detailed Description section. Supply Ground Noninverted Input Signal Inverted Input Signal Supply Ground This pin may be either connected to ground of left unconnected. This pin does not effet the performance of the device. Loss of Signal (LOS) Threshold. Connect a resistor from this pin to ground to set the input signal level at which LOS outputs will be asserted. See Application Information section. Inverted Loss of Signal Output. LOS is HIGH for input signals above the threshold programmed by TH. See Detailed Description section. Noninverted Loss of Signal Output. LOS is LOW for input signals above the threshold programmed by TH. See Detailed Description section. Power Supply Inverted Data Output Noninverted Data Output Power Supply Squelch Input. Squelch is disabled if this pin is unconnected or set LOW. When SQUELCH is HIGH, OUT+ and OUT- are forced to static levels. See Detailed Description section. No Connection CZ1 CZ2 GNDA LAINP LAINM GNDA NC CZ2 GND IN+ INGND NC 2 3 4 5 6 7 80.95 80.95 80.95 80.95 80.95 80.95 1170.525 990.525 810.525 630.525 450.525 270.525 TH TH 8 270.525 80.95 LOS LOS 9 1169.475 80.95 LOS VCCA LOAM LAOP VCCA SQ NC LOS VCC OUTOUT+ VCC SQUELCH -- 10 11 12 13 14 15 --/16 1359.05 1359.05 1359.05 1359.05 1359.05 1359.05 1169.475 270.525 450.525 630.525 810.525 990.525 1170.525 1359.05 Page 6 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com G52360-0, Rev 2.0 02/09/01 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7961 Detailed Description 3.125Gb/s PECL Limiting Amplifier with LOS Detect The VSC7961 is a high-speed limiting amplifier with Loss of Signal (LOS) detect. The device is designed to operate with a 3.3V or 5V supply in SDH/SONET and Fibre Channel applications up to 3.125Gb/s. The VSC7961 has positive emitter-coupled logic (PECL) outputs. The VSC7959 provides the same functionality as the VSC7961 with current-mode logic (CML) outputs. The key features of the VSC7961 are Loss-of-Signal (LOS) detect, output offset correction, output squelch, low power supply current, and fast rise and fall times. The inputs of the device provide 100 input impedance between IN+ and IN- and are intended to be DCcoupled. The PECL output circuits should be terminated through 50 to VCC - 2V. Loss of Signal (LOS) Detect This feature utilizes an rms power detector with programmable LOS indicator to provide two outputs, LOS and LOS. The input TH is used to set the threshold at which the loss of signal detector outputs, LOS and LOS, change state. See Loss of Signal Specifications (Table 3) for setting the resistor value between TH and ground. The Loss-of-Signal Truth Table (Table 4) clarifies how LOS and SQUELCH interact. Optional Squelch Squelch is disabled when SQUELCH is not connected or is set to TTL low level. When SQUELCH is set to TTL high level and LOS is asserted, the data outputs, OUT+ and OUT- are forced to static levels. If LOS is not asserted, the outputs will not be squelched. Offset Correction This feature is provided to ensure that the offsets in the amplifier coupled with its gain do not cause the output buffer to give a false output. Because of the high gain of the amplifier, offset correction using a low-frequency feedback loop reduces input offset. If no component is placed between pins CZ1 and CZ2, the low frequency cut-off is 2MHz. If a 0.1F capacitor is placed between CZ1 and CZ2, the low frequency cut-off is lowered to about 2kHz. For Fibre Channel and Gigabit Ethernet applications, leave pins CZ1 and CZ2 open. For ATM/SONET and other scrambled non-return-to-zero (NRZ) applications, place a 0.1F capacitor between CZ1 and CZ2. This maintains a one-decade separation between the lowest input frequency and the low frequency cut-off. The low frequency cut-off of the offset correction loop is given by the following equation: fOC = 43 / [2 * 35k (CZ + 100pF)] = 196* 10-6 / (CZ + 100pF) = 196* 10-6 / (0.1F + 100pF) = 1.96kHz G52360-0, Rev 2.0 02/09/01 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 7 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 3.125Gb/s PECL Limiting Amplifier with LOS Detect VSC7961 Output Level Control The LEVEL pin adjusts the output levels to 20mA when grounded and to 16mA when left unconnected. Figure 3: Supply Current Measurement VCC A ICC IOUT 100 100 100 100 IMOD VSC7961 A Supply Current (ICC and IEE) VEE IEE Applications Information Wire Bonding For best performance, gold ball-bonding techniques are recommended. To minimize inductance, keep wire bond lengths short. PCB Layout Guidelines Use high frequency PCB layout techniques with solid ground planes to minimize crosstalk and EMI. Keep high speed traces as short as possible for signal integrity. Short input and output traces will provide best performance. Page 8 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com G52360-0, Rev 2.0 02/09/01 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information VSC7961 Package Information TSSOP-16 3.125Gb/s PECL Limiting Amplifier with LOS Detect 1. All dimensioning and tolerancing per ASME. Y14.5-1994 2. Controlling dimension: millimeter 3. This outline conforms to JEDEC Publication 95 Registration MS-026 G52360-0, Rev 2.0 02/09/01 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 9 VITESSE SEMICONDUCTOR CORPORATION Advance Product Information 3.125Gb/s PECL Limiting Amplifier with LOS Detect VSC7961 Ordering Information The order number for this product is formed by a combination of the device type and package type. VSC7961 xx Device Type 3.125Gb/s PECL Limiting Amplifier with LOS Detect Package YD: TSSOP-16 W: Dice Waffle Pack Notice Vitesse Semiconductor Corporation ("Vitesse") provides this document for informational purposes only. This document contains pre-production information about Vitesse products in their concept, development and/or testing phase. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or will be suitable for or will accomplish any particular task. Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. Page 10 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com G52360-0, Rev 2.0 02/09/01 |
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