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CXA3017R
Decoder/Driver/Timing Generator for Color LCD Panels For the availability of this product, please contact the sales office.
Description The CXA3017R is an IC designed to drive the color LCD panels LCX005BK/BKB, LCX009AK/AKB, LCX024AK/AKB, LCX027AK/AKB and DCX501BK. This IC allows two-panel simultaneous and switching drive by simultaneously outputting the timing pulses for the LCX005BK/BKB, LCX009AK/AKB, LCX024AK/AKB, LCX027AK/AKB and DCX501BK. This IC greatly reduces the number of peripheral circuits and parts by incorporating an RGB decoder, driver, and timing generator for video signals onto a single chip. This chip has a built-in serial interface circuit and electronic attenuators which allow various settings to be performed by microcomputer control, etc. Features * Color LCD panel LCX005BK/BKB, LCX009AK/AKB, LCX024AK/AKB, LCX027AK/AKB and DCX501BK driver * Supports two-panel simultaneous and switching drive using the LCX005BK/BKB, LCX009AK/AKB, LCX024AK/AKB, LCX027AK/AKB and the DCX501BK * Supports NTSC and PAL systems * Supports 16:9 wide display (letter box and pulse elimination display) * Supports composite inputs, Y/C inputs and Y/color difference inputs * Serial interface circuit * Electronic attenuators (D/A converter) * VCO * BPF, trap and delay line * Sharpness function * 2-point correction circuit * R, G, B signal delay time adjustment circuit * Polarity inversion circuit (line inverted mode) * Supports external RGB input * D/A output pin (0 to 3V, 8 levels) * Supports AC drive for LCD panel during no signal 64 pin LQFP (Plastic)
Applications * Compact LCD monitors * LCD viewfinders * Compact liquid crystal projectors, etc. Structure Bi-CMOS IC Absolute Maximum Ratings (Ta = 25C) * Supply voltage VCC1 - GND1 6 V VCC2 - GND2 14 V VCC3 - GND3 14 V VDD1, 2 - VSS 4.5 V * Analog input pin voltage VINA -0.3 to VCC1 V * Digital input pin voltage VIND -0.3 to VDD1 + 0.3V * Operating temperature Topr -15 to +75 C * Storage temperature Tstg -40 to +125 C 1 * Allowable power dissipation PD (Ta 75C) Approximately 350mW Operating Conditions Supply voltage VCC1 - GND1 VCC2 - GND2 VCC3 - GND3 VDD1, 2 - VSS 1 With substrate
2.7 to 3.6 11.0 to 13.5 11.0 to 13.5 2.7 to 3.6
V V V V
Size: 30 x 30 x 1.6mm Material: Glass fabric base epoxy
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E98Y29-PS
CXA3017R
Block Diagram
SIG.CENTER
FB PSIG
R OUT
G OUT
B OUT
GND2
GND3
RGT1
PSIG
DWN
VCC3
FB R
FB G
VCC2
48
47 +12V
46
45
44
43
42 GND2
41
40
39 +12V
38
37 GND3
36
35
34
33 +3V
I/F Buf VCC1 49 +3.0V BLKLIM WHTLIM VXO OUT 50 POL SW INT/EXT VXO IN 51 COLOR APC 52 EXT COLOR & BALANCE HUE B-Y IN 53 CLAMP R-Y IN 54 APC C OUT 55 VXO HUE HUE V REG 56 REG COLOR CONT C IN 57 ACC DET RESET 58 KILLER Y IN 59 BPF R-CONT SUB CONTRAST B-CONT -1 GAMMA TEST2 60 ACC AMP FILT ADJ SYNC IN 61 PICTURE PIC CONT EXT SW CLP BGP SBLK CLAMP F0 ADJ 63 H.FILTER GND1 64 GND1 SYNC SEP V SEP VCO VCO 17 HCK2 TRAP DL1 HGATE H-SKEW DET PD 18 HCK1 HCNT H-PULSE -2 HAFC PLL-COUNTER & DECODER HD 21 HD RGB COLOR CONT CONTRAST S/H PS MATRIX USER BRIGHT LPF BRIGHT BRIGHT 27 VCK1 VWIN VPAL 26 VCK2 PALSW HUE COLOR BRIGHT CONT R-BRT B-BRT -1 VCO -2 PSIG-BRT R-CONT B-CONT PICTURE USER-BRT BLKLIM WHTLIM 25 VCK3 PAL ID DEMOD PALSW INT/EXT SUBBRIGHT R-BRT B-BRT FRP 28 XEN1 POL SW PSIGBRIGHT 30 EN2 PSIG-BRT VGATE WIDE VJOG 29 EN1 Buf Buf Buf D/A 32 DA OUT
VDD2
FB B
31 VD
USERBRT
24 VCK4
D/A
23 VST
22 XVST
20 PCG
VSEP TC 62
19 XPCG
SERIAL BAS I/F +3V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VSS 16
EXT R
LOAD
DATA
TEST1
VDD1
CLR
BLK
TRAP
RPD
-2-
XHST1
EXT B
SCLK
EXT G
HST2
HST1
VSS
CXA3017R
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol EXT R EXT G EXT B TRAP VDD1 LOAD DATA SCLK RPD TEST1 BLK CLR HST2 HST1 XHST1 VSS HCK2 HCK1 XPCG PCG HD XVST VST VCK4 VCK3 VCK2 VCK1 XEN1 EN1 EN2 VD DA OUT VDD2 DWN O O O O O O O O O O O O O O O O O I I I O I O O O O O I/O I I I O External digital R input External digital G input External digital B input External trap connection Digital 3V power supply for oscillation cell Serial interface load input Serial interface data input Serial interface clock input Phase comparator output Test (Connect to GND.) BLK pulse output CLR pulse output H start pulse 2 output H start pulse 1 output XH start pulse 1 output (reverse polarity of HST1) Digital 3V GND H clock pulse 2 output H clock pulse 1 output XPCG pulse output (reverse polarity of PCG) PCG (precharge) pulse output HD pulse output XV start pulse output (reverse polarity of VST) V start pulse output V clock pulse 4 output V clock pulse 3 output V clock pulse 2 output V clock pulse 1 output XEN pulse 1 output (reverse polarity of EN1) EN pulse 1 output EN pulse 2 output VD pulse output DAC output Digital 3V power supply DCX501BK up/down inverted display switching (open collector output) -3- L Description
Input pin processing for open status
CXA3017R
Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Symbol RGT1 FB PSIG GND3 PSIG VCC3 B OUT FB B GND2 G OUT FB G R OUT FB R VCC2 SIG.CENTER VCC1 VXO OUT VXO IN APC B-Y IN R-Y IN C OUT V REG C IN RESET Y IN TEST2 SYNC IN VSEP TC F0 ADJ GND1
I/O O I
Description DCX501BK right/left inverted display switching (open collector output) PSIG signal DC voltage feedback circuit capacitor connection Analog 12V GND for PSIG
Input pin processing for open status
O
PSIG output Analog 12V power supply for PSIG
O I
B signal output B signal DC voltage feedback circuit capacitor connection Analog 12V GND
O I O I
G signal output G signal DC voltage feedback circuit capacitor connection R signal output R signal DC voltage feedback circuit capacitor connection Analog 12V power supply
I
R, G, B and PSIG output DC voltage adjustment Analog 3V power supply
O I O I I O O I I I I I
VXO output VXO input APC detective filter connection B-Y color difference signal input R-Y color difference signal input Chroma signal output Constant voltage capacitor connection Chroma signal input System reset Y signal input Test (Connect to GND.) Video input for sync separation Capacitor connection for vertical sync separation (or external VSYNC input) L
O
Internal filter adjusting resistor connection Analog 3V GND RGT: RIGHT SCAN and LEFT SCAN
DWN: DOWN SCAN and UP SCAN
-4-
CXA3017R
Analog Block Pin Description Pin No. 1 Symbol Pin voltage Equivalent circuit Description External digital signal inputs. There are two thresholds: Vth1 (= 1.0V) and Vth2 (= 2.0V). When one of the RGB signals exceeds Vth1, all of the RGB outputs go to black level; when an input exceeds Vth2, only the corresponding output goes to white level. Connect these pins to GND when not used. External trap connection. Connect the trap between this pin and GND to eliminate the chroma component. Leave this pin open when using Y/C and Y/color difference mode.
EXT-R
VCC1 25A 1 300
2
EXT-G
--
2 3 50k 1.1V GND1
3
EXT-B
VCC1 75A 1k
4
TRAP
1.0V
300 4 200A GND1 VDD2 50k 50k
32
DA OUT
0.2 to 2.9V
32 50k VSS
DAC output. 8-level, 7-step DC voltage from approximately 0.2 to 2.9V is output from this pin.
34
DWN
--
VCC2 500 34 35
35
RGT1
--
GND2
DCX501BK up/down and right/left inversion switching. These pins are open collector outputs, so first connect a 100k resistor between these pins and the panel VDD (15.5V) and then connect to the DCX501BK.
36 41 44 46 37
FB PSIG FB B 1.5V FB G FB R GND3 0V
VCC1 1k 36 41 44 46 GND2 1k 100k
Smoothing capacitor connection for the feedback circuit of R, G, B and PSIG output DC level control. Use a low-leakage capacitor because of high impedance.
GND for the PSIG circuit. -5-
CXA3017R
Pin No.
Symbol
Pin voltage
VCC3
Equivalent circuit
Description
150
38
PSIG
VCC2 2
38 20
PSIG signal output.
GND3
39
VCC3 B OUT
12V
VCC2 40 43 45 20 40A GND2
12V power supply for the PSIG circuit.
40
43
G OUT
VCC2 2
20
RGB signal outputs.
45 42 47
R OUT GND2 VCC2 0V 12V
12V GND. 12V power supply.
VCC2 150k 10k
48
SIG. CENTER
VCC2 2
300 48 150k GND2
RGB/PSIG output DC voltage control. When used with a VCC2 or VCC3 of 12V or more, or when used with a signal center voltage of other than VCC2/2 or VCC3/2, apply voltage of 5.2 to 6.5V from an external source. 3.0V power supply.
49
VCC1
3.0V
VCC1
200
50
VXO OUT
1.2V
50 370A GND1
VXO output. Leave this pin open when using Y/color difference mode.
VCC1
500 51
51
VXO IN
1.6V
10k 10p GND1
3.5k 3.5k
VXO input. Leave this pin open when using Y/color difference mode.
1.6V
-6-
CXA3017R
Pin No.
Symbol
Pin voltage
VCC1
Equivalent circuit
Description
500 1k
52
APC
1.7V
52
APC detective filter connection. Leave this pin open when using Y/color difference mode.
GND1
53
B-Y IN
VCC1 4k 10k 5k
--
53 54
1k
54
R-Y IN
4k 40A GND1
30A
Y/color difference signal inputs. When using color difference input, the standard signal input level is 0.3Vp-p (75% color bar) and the clamp level is approximately 1.7V. During D-PAL, the COUT (Pin 55) chroma signal is U/V separated and then input. Input at low impedance (75 or less). Color adjusted chroma signal output during D-PAL. The output level is tripled in order to compensate for the attenuation of the external U/V separation delay line. The standard burst output level is approximately 200mVp-p. Leave this pin open in modes other than D-PAL. Smoothing capacitor connection for the internally generated constant voltage source circuit. Connect a capacitor of 1F or more.
VCC1
55
C OUT
1.2V
55 50A GND1
VCC1
56
56
V REG
2.0V
18.5k 30k GND1 VCC1 15A 50k 5p
57
C IN
--
57 50k 10p GND1 30A
Video signal input when using composite signal input. Chroma signal input when using Y/C signal input. Leave this pin open when using Y/color difference mode.
D-PAL is a demodulation method that uses an external delay line during demodulation. S-PAL is a demodulation method that internally processes chroma demodulation. -7-
CXA3017R
Pin No.
Symbol
Pin voltage
VDD1
Equivalent circuit
Description
2A 300
58
RESET
--
58 1k
TG block system reset pin. The system is reset when this pin is connected to GND. Connect a capacitor between this pin and GND.
GND1
VCC1 1k
59
Y IN
1.6V
59
20A GND1
Y signal input. The standard signal input level is 0.5Vp-p (100% white level from the sync tip). Input at low impedance (75 or less).
VDD1 1k
61
SYNC IN
1.6V
1k 61 500 0.6A GND1 12A
Sync input. Normally inputs the Y signal. The standard signal input level is 0.5Vp-p (100% white level from the sync tip). Input at low impedance (75 or less).
VDD1 500 1k
62
VSEP TC
1.7V
62 1k 20A GND1
Capacitor connection for vertical sync separation.
20A
VCC1 200 5p
63
F0 ADJ
1.5V
63
500 5p GND1 500
Filter reference current generation. Connect resistance of 15 k between this pin and GND1 to adjust the internal filters using the outflow current value. Leave this pin open when using Y/C or Y/color difference mode. 3.0V GND. Test. Connect to GND.
64 60
GND1 TEST2
0V 0V -8-
CXA3017R
Digital Block Pin Description Pin No. 5 6 7 8 9 33 10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Symbol VDD1 LOAD DATA SCLK RPD VDD2 TEST1 BLK CLR HST2 HST1 XHST1 HCK2 HCK1 XPCG PCG HD XVST VST VCK4 VCK3 VCK2 VCK1 XEN1 EN1 EN2 VD
11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VSS VDD2 6 7 8 VSS
Pin voltage
Equivalent circuit
Description Power supply for VCO.
1k
Serial bus inputs.
Phase comparator output. Power supply for digital block. Test. Connect to GND.
Digital block outputs.
-9-
CXA3017R
Setting Conditions for Measuring Electrical Characteristics Use the Electrical Characteristics Measurement Circuit on page 30 while measuring electrical characteristics. Also, the TG (timing generator) block must be initialized by performing Settings 1 and 2 below. Setting 1. System reset After turning on the power, set SW58 to ON and start up V58 from GND in order to activate the TG block system reset. (See Fig. 1-1.) The serial bus is set to the default values. Setting 2. Horizontal AFC adjustment Input SIG5 (VL = 0mV) to (A) and adjust serial bus register VCO so that the TP9 phase comparison output waveform (near VSYNC) is horizontal. SW48 = OFF, SW58 = ON, V58 = 3.0V (See Fig. 1-2.) Note) When measuring a band of 2MHz or more such as Y signal frequency response or sharpness characteristics among the items being measured, the measurement must be made with the sample-and-hold circuit set to through (sample and hold not performed) by the serial bus.
VDD
V58 (PWRST)
TR
TR > 10s
Fig. 1-1. System reset
SIG5 VSYNC VSYNC
TP9
TP9 Adjust to a horizontal waveform.
approximately 1/2VDD
Fig. 1-2. Horizontal AFC adjustment - 10 -
CXA3017R
Electrical Characteristics -- DC Characteristics Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required. VCC1 = 3.0V, VCC2 = VCC3 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = VDD2 = 3.0V, VSS = 0V, Ta = 25C SW1/SW2/SW3 = A, SW53/SW54/SW57 = B SW58 = ON, SW48 = OFF V58 = 3.0V Set the serial bus registers to the "Serial Bus Register Initial Settings". Unspecified items should be set to the default settings.
Item Symbol Conditions Min. Typ. Max. Unit
Current characteristics ICC11 Current consumption VCC1 Input SIG4 to (A) and SIG2 (0dB) to (B), and measure the ICC1 current value. COMP input mode. SW57 = A Input SIG4 to (A) and SIG2 (0dB) to (B), and measure the ICC1 current value. Y/C input mode. SW57 = A Input SIG4 to (A), (D) and (E) and measure the ICC1 current value. Y/color difference input mode. SW53 = SW54 = A Input SIG4 to (A) and SIG2 (0dB) to (B), and measure the ICC2 current value. SW57 = A Input SIG4 to (A) and SIG2 (0dB) to (B), and measure the IDD3 and IDD4 current values. IDD1 = IDD3 + IDD4, LCX009AK/AKB SW57 = A Input SIG4 to (A) and SIG2 (0dB) to (B), and measure the IDD3 and IDD4 current values. IDD2 = IDD3 + IDD4, LCX005BK/BKB SW57 = A 27 34 41 mA
ICC12
24
30
37
mA
ICC13 Current consumption VCC2, 3
19
25
30
mA
ICC2
6
8
10
mA
IDD1 Current consumption VDD1, 2 IDD2
8.5
11
13.5
mA
7.5
10
12.5
mA
Digital block I/O characteristics Low level input voltage High level input voltage VIL VIH Digital block input pins1 SW57 = A (A) = SIG4, (B) = SIG2 Digital block input pins1 SW57 = A (A) = SIG4, (B) = SIG2 VDD = 3.0V SW57 = A VOH1 VDD = 2.7V SW57 = A VOL1 IOH = -1.2mA2 (A) = SIG4, (B) = SIG2 IOH = -1.2mA2 (A) = SIG4, (B) = SIG2 0.7VDD 2.8 2.6 0.3 0.3VDD V V V V V
High level output voltage
Low level output voltage
IOL = 1.2mA2 SW57 = A (A) = SIG4, (B) = SIG2
1 Digital block input pins: SCLK, DATA, LOAD 2 Output pins except RPD: BLK, CLR, HST2, HST1, XHST1, HCK2, HCK1, XPCG, PCG, HD, XVST, VST, VCK4, VCK3, VCK2, VCK1, XEN1, EN1, EN2, VD - 11 -
CXA3017R
Electrical Characteristics -- AC Characteristics Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required. VCC1 = 3.0V, VCC2 = VCC3 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = VDD2 = 3.0V, VSS = 0V, Ta = 25C SW1, SW2, SW3 = A SW53, SW54, SW57 = B SW58 = ON SW48 = OFF V58 = 3.0V Set the serial bus registers to the "Serial Bus Register Initial Settings". Unspecified items should be set to the default settings. Unless otherwise specified, measure the non-inverted outputs for TP40, TP43 and TP45.
Item Y signal system Video maximum gain Contrast characteristics TYP Contrast characteristics MIN GV Input SIG4 to (A) and measure the ratio between the output amplitude (white-black) and input amplitude at TP43. Input SIG4 to (A) and measure the ratio between the output amplitude (white-black) and input amplitude at TP43. Input SIG4 to (A) and measure the ratio between the output amplitude (white-black) and input amplitude at TP43. Assume the output amplitude at TP43 when SIG1 (0dB, no burst, 100kHz) is input to (A) as 0dB. Vary the frequency of the input signal to obtain the frequency with an output amplitude of -3dB. CL = 400pF Y/C input Composite input (NTSC) Composite input (PAL) 2.5MHz MAX Assume the output amplitude at TP43 when SIG7 (100kHz) is 2.5MHz MIN input to (A) as 0dB. Obtain the amount by which the output amplitude of SIG7 (2.5MHz or 1.8MHz MAX 1.8MHz) changes when PICTURE is set to the MAX and MIN values. 1.8MHz MIN 19 21 23 dB Symbol Conditions Min. Typ. Max. Unit
GCNTTP
14
16
18
dB
GCNTMN
-3
1
3
dB
FCYYC Y signal frequency response FCYCMN FCYCMP Picture quality adjustment variable amount 1 (Y/C input) LCX009AK/AKB Picture quality adjustment variable amount 2 (Y/C input) LCX005BK/BKB Picture quality adjustment variable amount 3 (composite input) LCX005BK/BKB Picture quality adjustment variable amount 4 (composite input) LCX009AK/AKB
5.0 2.5 3.0
MHz MHz MHz
GSHP1X
11
14
dB
GSHP1N
-3
0
dB
GSHP2X
11
14
dB
GSHP2N
-1
2
dB
GSHP3X
1.8MHz MAX Assume the output amplitude at TP43 when SIG7 (100kHz) is 1.8MHz MIN input to (A) as 0dB. Obtain the amount by which the output amplitude of SIG7 (1.8MHz or 2.5MHz MAX 2.5MHz) changes when PICTURE is set to the MAX and MIN values. 2.5MHz MIN
8
11
dB
GSHP3N
-5
-2
dB
GSHP4X
6
9
dB
GSHP4N
-6
-3
dB
- 12 -
CXA3017R
Item
Symbol
Conditions Input SIG2 (0dB) to (A). Using a spectrum analyzer, measure the input and the 3.58MHz or 4.43MHz component of TP43, and obtain CRLEKY = 150mV x 10CLK/20 using their difference CLK. Y/C input Input SIG9 to (A). Measure the delay time from the 2T pulse peak of the input signal to the 2T pulse peak of the non-inverted output at TP43. Composite input (NTSC) Composite input (PAL) Y/color difference input SW53 = SW54 = A
Min.
Typ.
Max.
Unit
Carrier leak (residual carrier)
CRLEKY
30
mV
TDYYC TDYCMN Y signal I/O delay time TDYCMP TDYDEF Chroma signal block
260 520 520 100
360 620 620 200
460 720 720 300
ns ns ns ns
ACC amplitude characteristics 1
ACC1
ACC amplitude characteristics 2
ACC2
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB/+6dB/-20dB, 3.58MHz burst/chroma phase = 180, or 4.43MHz burst/chroma phase = 135) to (B). Measure the output amplitude at TP55, assuming the output corresponding to 0dB, +6dB and -20dB as V0, V1 and V2, respectively. ACC1 = 20 log (V1/V0) ACC2 = 20 log (V2/V0)
NTSC
-3
0
3
dB
PAL
-3
0
3
dB
NTSC
-3
0
3
dB dB
PAL
-3
0
3
APC pull-in range
FAPC
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz burst/chroma phase = 180, or 4.43MHz burst/chroma phase = 135) to (B). Vary the SIG2 burst frequency and measure the frequency f1 at which the TP40 output appears (the killer mode is canceled). NTSC: FAPCN = f1 - 3579545Hz PAL: FAPCP = f1 - 4433619Hz
NTSC
500
Hz
PAL
500
Hz
Color adjustment characteristics MAX Color adjustment characteristics MIN HUE adjustment characteristics MAX HUE adjustment characteristics MIN
GCOLMX
GCOLMN
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz burst/chroma phase = 180) to (B). Assume the chroma signal amplitude at TP55 when serial bus register COLOR = 128, 255 and 0 as V0, V1 and V2, respectively. GCOLMX = 20 log (V1/V0) GCOLMN = 20 log (V2/V0) Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, burst/chroma phase variable) to (B). Assume the phase at which the output amplitude at TP40 reaches a minimum when serial bus register HUE = 128, 255 and 0 as 0, 1 and 2, respectively. HUEMX = 1 - 0 HUEMN = 2 - 0 SW57 = A
+3
+5
dB
-25
-20
dB
HUEMX
-30
-40
deg
HUEMN
30
60
deg
- 13 -
CXA3017R
Item
Symbol
Conditions Input SIG5 (VL = 150mV) to (A) and SIG2 (level variable, 3.58MHz burst/chroma phase = 180, or 4.43MHz burst/chroma phase = 135) to (B), and measure the output amplitude at TP40. Gradually reduce the SIG2 amplitude level and measure the level at which the killer operation is activated. SW57 = A
Min.
Typ.
Max.
Unit
ACKN Killer operation input level ACKP
NTSC
-36
-30
dB
PAL
-36
-30
dB
VRBN Demodulation output amplitude ratio (NTSC) VGBN
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz) to (B) and vary the chroma phase. Assume the maximum amplitude at TP40 as VB, the maximum amplitude at TP43 as VG, and the maximum amplitude at TP45 as VR. VRBN = VR/VB, VGBN = VG/VB SW57 = A Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz) to (B) and vary the chroma phase. Assume the phase at which the amplitude at TP40, TP43 and TP45 reaches a maximum as B, G and R, respectively. RBN = R - B, GBN = G - B SW57 = A Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 4.43MHz) to (B) and vary the chroma phase. Assume the maximum amplitude at TP40 as VB, the maximum amplitude at TP43 as VG, and the maximum amplitude at TP45 as VR. VRBP = VR/VB, VGBP = VG/VB SW57 = A Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 4.43MHz) to (B) and vary the chroma phase. Assume the phase at which the amplitude at TP40, TP43 and TP45 reaches a maximum as B, G and R, respectively. RBP = R - B, GBP = G - B SW57 = A Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D). Assume the output amplitude at TP40 (100kHz) when serial bus register COLOR = 128 as VC0, when COLOR = 0 as VC2, and when SIG1 is set to -10dB and COLOR = 255 as VC1. GEXCMX = 20 log (VC1/VC0) + 10 GEXCMN = 20 log (VC2/VC0) SW53 = SW54 = A Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D) and (E). Assume the output amplitude at TP40 (100kHz) as VB and the output amplitude at TP45 (100kHz) as VR. VEXCBL = VR/VB SW53 = SW54 = A
0.53
0.63
0.73
0.25
0.32
0.39
RBN Demodulation output phase difference (NTSC)
99
109
119
deg
GBN
230
242
254
deg
VRBP Demodulation output amplitude ratio (PAL) VGBP
0.65
0.75
0.85
0.33
0.40
0.47
RBP Demodulation output phase difference (PAL)
80
90
100
deg
GBP
232
244
256
deg
Color difference input color adjustment characteristics MAX Color difference input color adjustment characteristics MIN
GEXCMX
+3
+5
dB
GEXCMN
-20
-15
dB
Color difference balance
VEXCBL
0.8
1.0
1.2
- 14 -
CXA3017R
Item
Symbol
Conditions Input SIG5 (VL = 150mV) to (A) and SIG1 (-6dB, 100kHz, no burst) to (D) and (E). Assume the output amplitude at TP45 (100kHz) and TP40 (100kHz) when serial bus register HUE = 128 as VR0 and VB0, respectively, when HUE = 255 as VR1 and VB1, respectively, and when HUE = 0 as VR2 and VB2, respectively. GEXRMX = 20 log (VR1/VR0) GEXRMN = 20 log (VR2/VR0) GEXBMX = 20 log (VB1/VB0) GEXBMN = 20 log (VB2/VB0) SW53 = SW54 = A Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D). Assume the output amplitude at TP40 (100kHz) as VEXB and the output amplitude at TP43 (100kHz) as VEXBG. VEXGBN = VEXBG/VEXB SW53 = SW54 = A Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (E). Assume the output amplitude at TP45 (100kHz) as VEXR and the output amplitude at TP43 (100kHz) as VEXRG. VEXGRN = VEXRG/VEXR SW53 = SW54 = A Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D). Assume the output amplitude at TP40 (100kHz) as VEXB and the output amplitude at TP43 (100kHz) as VEXBG. VEXGBP = VEXBG/VEXB SW53 = SW54 = A Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (E). Assume the output amplitude at TP45 (100kHz) as VEXR and the output amplitude at TP43 (100kHz) as VEXRG. VEXGRP = VEXRG/VEXR SW53 = SW54 = A
Min.
Typ.
Max.
Unit
Color difference input balance adjustment R
GEXRMX
-5
-2
dB
GEXRMN
+2
+3
dB
Color difference input balance adjustment B
GEXBMX
+2
+3
dB
GEXBMN
-5
-2
dB
VEXGBN G-Y matrix characteristics (NTSC) VEXGRN
0.23
0.26
0.29
0.46
0.51
0.56
VEXGBP G-Y matrix characteristics (PAL) VEXGRP
0.17
0.20
0.23
0.46
0.51
0.56
RGB signal output block RGB signal and PSIG output DC voltage Input SIG5 (VL = 0mV) to (A). Adjust serial bus registers BRIGHT and PSIG-BRT so that the output (black-black) at TP43 and TP38 is 9Vp-p and measure the DC voltage at TP40, TP43, TP45 and TP38. Input SIG5 (VL = 0mV) to (A). Adjust serial bus registers BRIGHT and PSIG-BRT so that the output (black-black) at TP43 and TP38 is 9Vp-p, measure the DC voltage at TP40, TP43, TP45 and TP38, and obtain the maximum difference between each of these values. Set V48 to 5.2V or 6.5V in the VOUT measurement conditions and confirm that VOUT in the preceding item is satisfied and that |V48 - VOUT| 0.15V. SW48 = ON
VOUT
5.85
6.00
6.15
V
RGB signal and PSIG output DC voltage difference
VOUT
0
100
mV
SIG center variable VORNG range
5.2
6.5
V
- 15 -
CXA3017R
Item
Symbol
Conditions Input SIG3 to (A). Vary BLKLIM and measure the maximum value VLIMMX and minimum value VLIMMN of the voltage range (black-black) over which the black limiter operates for the TP38, TP40, TP43 and TP45 outputs. Assume the value when BLKLIM = 0 as VLIMMX, and when BLKLIM = 255 as VLIMMN. Input SIG3 (VL = 0mV) to (A) and measure the output (black-black) at TP38 when serial bus register PSIG-BRT = 255. Input SIG3 (VL = 0mV) to (A) and measure the output (black-black) at TP38 when serial bus register PSIG-BRT = 0. Input SIG3 to (A) and measure the amount of change in the black level output at TP40, TP43 and TP45 when serial bus register USER-BRT is changed from 128 to 255. Input SIG3 to (A) and measure the amount of change in the white level output at TP40, TP43 and TP45 when serial bus register USER-BRT is changed from 128 to 0. Input SIG3 to (A) and measure the black level output at TP40, TP43 and TP45 when serial bus register BRIGHT is changed from 128 to 255. Input SIG3 to (A) and measure the white level output at TP40, TP43 and TP45 when serial bus register BRIGHT is changed from 128 to 0. Input SIG5 (VL = 0mV) to (A) and measure the difference between the outputs (black-black) at TP40 and TP45 and the output (black-black) at TP43 when serial bus registers R-BRT = B-BRT = 0 and when R-BRT = B-BRT = 255. Input SIG4 to (A) and obtain the level difference between the maximum and minimum non-inverted output amplitudes (white-black) at TP40, TP43 and TP45. Input SIG4 to (A) and measure the difference between the non-inverted outputs (white-black) at TP40 and TP45 and the non-inverted output (white-black) at TP43 when serial bus registers R-CNT = B-CNT = 0 and when R-CNT = B-CNT = 255. Input SIG4 to (A) and obtain the difference between the non-inverted output amplitudes (white-black) and the inverted output amplitudes at TP40, TP43 and TP45. Input SIG4 to (A) and obtain the level difference between the maximum and minimum black levels of both the inverted and non-inverted outputs at TP40, TP43 and TP45.
Min. 9.0
Typ.
Max.
Unit
VLIMMX RGB and PSIG output black limiter operation voltage VLIMMN
Vp-p
7.0
Vp-p
PSIGMX Amount of change in PSIG output PSIGMN
9.0
Vp-p
1.5
Vp-p
UBRTMX Amount of change in user brightness UBRTMN
2.5
3.0
V
-3.0
-2.5
V
BRTMX Amount of change in brightness BRTMN
2.0
2.5
V
-2.5
-2.0
V
Amount of change in sub-brightness
SBBRT
1.3
1.7
V
Difference in gain between RGB output signals
GRGB
-0.6
0
0.6
dB
Amount of change in sub-contrast
SBCNT
1.5
2
dB
Difference in RGB output inverted/ non-inverted gain Difference in black level potential between RGB output signals
GINV
-0.3
0
0.3
dB
VBL
300
mV
- 16 -
CXA3017R
Item
Symbol G1
Conditions Input SIG8 to (A). Adjust the non-inverted output amplitude (black-white) at TP43 to 3.5Vp-p with serial bus register CONT and the black level at TP43 to 1.5V with serial bus register RBT. Measure VG1, VG2 and VG3. G 1 = 20 log (VG1/0.0375) G 2 = 20 log (VG2/0.0375) G 3 = 20 log (VG3/0.0375) (See Fig. 5 for definitions of VG1, VG2 and VG3.) Input SIG8 to (A) and adjust serial bus register BRIGHT so that the output at TP43 is 9Vp-p (blackblack). Read the point where the gain of the non-inverted output at TP43 changes when serial bus register 1 = 0 and 255 from the input signal IRE level. V 1MN when 1 = 0, and V 1MX when 1 = 255. Input SIG8 to (A) and adjust serial bus register BRIGHT so that the output at TP43 is 9Vp-p (blackblack). Read the point where the gain of the non-inverted output at TP43 changes when serial bus register 2 = 0 and 255 from the input signal IRE level. V 2MN when 2 = 0, and V 2MX when 2 = 255. Input SIG4 to (A) and adjust serial bus register PSIGBRT so that the output at TP38 is 9Vp-p (black-black). Measure the time it takes to change to an amplitude of 9Vp-p. tPSIGH: rise time, tPSIGL: fall time Load: 20000pF Input SIG3 to (A) and measure the potential difference between the white limiter level of the TP43 output and SIGCENTER. VWLIMX when WHITELIM = 0 VWLIMN when WHITELIM = 3 Input SIG5 (VL = 0mV) to (A) and adjust BLKLIM so that the output at TP43 is 9Vp-p (black-black). Measure the DC voltage at TP40, TP43 and TP45 and obtain the difference versus the RGB output voltage VOUT. Input SIG5 (VL = 350mV) to (A). Measure the DC voltage at TP40, TP43 and TP45 and obtain the difference versus the RGB output voltage VOUT. Input SIG8 to (A). Assume the black limiter level of the output at TP40, TP43 and TP45 when serial bus register BRIGHT = 0 as VDRB and the white limiter level when BRIGHT = 255 as VDRW. VDROFF = VDRW - VDRB
Min. 23.0
Typ. 26.0
Max. 29.0
Unit dB
gain
G2
12.0
15.0
18.0
dB
G3
18.0
22.0
26.0
dB
V 1MN 1 adjustment variable range V 1MX
0
IRE
100
IRE
V 2MN 2 adjustment variable range V 2MX
100
IRE
0
IRE
tPSIGH
PSIG transition time
1.5
3.0
s
tPSIGL
1.5
3.0
s
RGB output white limiter operation voltage
VWLIMX
1.0
1.1
1.2
V
VWLIMN
0.45
0.55
0.65
V
Black limiter DC voltage difference
VBLIM
0
100
mV
White limiter DC voltage difference
VWLIM
0
100
mV
RGB output range when FRP polarity VDROFF inversion is stopped
3.0
Vp-p
- 17 -
CXA3017R
Item Filter characteristics
Symbol
Conditions
Min.
Typ.
Max.
Unit
Amount of BPF attenuation
ATBPF
Assume the chroma amplitude at TP55 when SIG5 (VL = 0mV) is input to (A) and SIG1 (0dB at input center frequency (3.58MHz or 4.43MHz)) is input to (B) as 0dB. Obtain the amount by which the output at TP55 is attenuated when the frequencies noted on the right are input. SW57 = A Input SIG2 (0dB, 3.58MHz and 4.43MHz) to (A) and measure the output at TP43 with a spectrum analyzer. Assume the amplitude at TP43 during Y/C input mode as 0dB, and obtain the amount of attenuation during COMP input mode.
NTSC 1.5MHz PAL 2.0MHz
-18 -16 -6 -6
-12 -10 -2 -2
dB dB dB dB
NTSC 5.5MHz PAL 6.8MHz
ATRAPN Amount of TRAP attenuation ATRAPP
NTSC
-40
-30
dB
PAL
-40
-30
dB
R-Y and B-Y LPF characteristics
DEMLPF
Assume the amplitude of the 100kHz component of the output at TP43 when SIG5 (VL = 150mV) is input to (A) and SIG2 (0dB, 3.58MHz + 100kHz) is input to (B) as 0dB. Obtain the frequency which attenuates the beat component of the output by 3dB when the SIG2 frequency is increased with respect to 3.58MHz.
0.9
1.2
1.5
MHz
Sync separation, TG block Input SIG5 (VL = 0mV, VS = 143mV, WS variable) to (A) and confirm that it is synchronized with the HD output at TP21. Gradually narrow the WS of SIG5 from 4.7s and obtain the WS at which synchronization with the HD output at TP21 is lost. Input SIG5 (VL = 0mV, WS = 4.7s, VS variable) to (A) and confirm that it is synchronized with the HD output at TP21. Gradually reduce the VS of SIG5 from 143mV and obtain the VS at which synchronization with the HD output at TP21 is lost. Input SIG5 (VL = 0mV, WS = 4.7s, VS = 143mV) to (A) and measure the delay time with the HD output at TP21. TDSY1 is from the falling edge of the input HSYNC to the rising edge of the HD output, and TDSY2 is from the falling edge of the input HSYNC to the falling edge of the HD output. Input SIG5 (VL = 0mV, WS = 4.7s, VS = 143mV, horizontal frequency variable) to NTSC (A) and confirm that it is synchronized with the HD output at TP21. Obtain the frequency fH at which the input and output are synchronized by changing the horizontal frequency of SIG5 from the PAL non-synchronized condition. HPLLN = fH - 15734, HPLLP = fH - 15625 2.3
Input sync signal width sensitivity
WSSEP
2.0
s
Sync separation input sensitivity
VSSEP
40
60
mV
TDSY1 HD output delay time TDSY2
2.6
2.9
s
4.3
4.6
4.9
s
HPLLN Horizontal pull-in range HPLLP
500
1000
Hz
500
1000
Hz
- 18 -
CXA3017R
Item Output transition time (page 112 pins) Cross-point time difference
Symbol
Conditions Input SIG5 (VL = 0mV) to (A) and measure the transition time for each output. Load = 50pF (See Fig. 3.) SW57 = A Input SIG5 (VL = 0mV) to (A) and measure HCK1/HCK2, VCK1/VCK2 and VCK3/VCK4. Load = 50pF (See Fig. 4.) SW57 = A Input SIG5 (VL = 0mV) to (A) and measure the HCK1/HCK2 duty. Load = 50pF, SW57 = A Measure the output voltage at TP23 when DA OUT = 7. IOH = -1mA Measure the output voltage at TP23 when DA OUT = 0. IOH = 1mA
Min.
Typ.
Max. 30 30
Unit ns ns
tTLH tTHL
T
10
ns
HCK duty
DTYHC
47
50
53
%
VBKLTH DA OUT output voltage VBKLTL External I/O characteristics
2.7 0.3
V
V
VTEXTB External RGB input threshold voltage VTEXTW
Input SIG5 (VL = 0mV) to (A) and SIG6 (VL variable) to (C). Raise the SIG6 amplitude (VL) from 0V and assume the voltage where the outputs at TP40, TP43 and TP45 go to black level as VTEXTB. Then raise the amplitude further and assume the voltage where these outputs go to white level as VTEXTW. SW1 = SW2 = SW3 = B Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 3V) to (C). Measure the rise delay time TD1EXT and the fall delay time TD2EXT of the outputs at TP40, TP43 and TP45. (See Fig. 2.) SW1 = SW2 = SW3 = B Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 1.7V) to (C). Measure the difference from the black level of the outputs at TP40, TP43 and TP45. SW1 = SW2 = SW3 = B Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 2.7V) to (C). Measure the difference from the black level of the outputs at TP40, TP43 and TP45. SW1 = SW2 = SW3 = B Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 2.7V) to (C). Measure the minimum pulse width at which each of the outputs at TP40, TP43 and TP45 reach the white limiter. SW1 = SW2 = SW3 = B
0.8
1.0
1.2
V
1.8
2.0
2.2
V
Propagation delay time between external RGB input and output Output blanking level during external RGB input
TD1EXT
50
90
130
ns
TD2EXT
50
100
140
ns
EXTBK
0
V
Output white level during external RGB input
EXTWT
3.0
V
Minimum pulse width during external RGB input
TEXMIN
180
ns
- 19 -
CXA3017R
Item Serial transfer block
Symbol
Conditions
Min.
Typ.
Max.
Unit
ts0 Data setup time ts1 th0 Data hold time th1 tw1L Minimum pulse width tw1H tw2
LOAD setup time, activated by the rising edge of SCLK. (See Fig. 6.) DATA setup time, activated by the rising edge of SCLK. (See Fig. 6.) LOAD hold time, activated by the rising edge of SCLK. (See Fig. 6.) DATA hold time, activated by the rising edge of SCLK. (See Fig. 6.) SCLK pulse width. (See Fig. 6.) SCLK pulse width. (See Fig. 6.) LOAD pulse width. (See Fig. 6.)
150 150 150 150 156 156 1
ns ns ns ns ns ns s
- 20 -
Description of Electrical Characteristics Measurement Methods Serial Bus Register Initial Settings
Serial bus Mode settings System Panel S/H FRP HUE COL BRT CNT -- 1 0 0 0 0 0 0 0 0 0 0 128 128 128 128 128 0 128 128 128 128 128 0 0 0 0 0 0 0 0 0 0 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 128 128 128 0 128 128 128 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 ON 128 128 128 128 ON 128 128 128 128 ON 128 128 128 128 128 128 ON 128 128 128 128 128 128 ON 128 128 128 128 128 128 ON 128 128 128 128 128 128 ON 128 128 128 128 128 128 ON 128 128 128 128 128 128 ON 128 128 128 128 128 128 ON 128 128 128 128 128 128 128 128 -- -- -- ON 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 BRBRT BRT 1 2 DAC settings USER WHITE DA BLK BPSIG RPIC -BRT VCO LIM OUT BRT CNT CNT LIM ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ 3 3 3 3 3 3 3 3 3 3 3 3 3 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- (--: don't care, ADJ: adjustment, SET: setting)
Item
Symbol
Input
Setting 2
Horizontal AFC adjustment
COMP NTSC
ICC11 Y/C NTSC
COMP NTSC
Current consumption VCC1
ICC12
ICC13
Y/color NTSC difference
Current ICC2 consumption VCC2, 3
COMP NTSC 501
Current characteristics
IDD1 Current consumption VDD1, 2 IDD2 -- -- -- -- -- -- --
COMP NTSC 009
Digital block I/O characteristics
Y signal block
- 21 -
ALL ON 128 128 128 255 ALL ON 128 128 128 128 ALL ON 128 128 128
COMP NTSC 005
Low level input voltage
VIL
COMP NTSC
High level input voltage
VIH
COMP NTSC
High level output voltage
VOH1
COMP NTSC
Low level output voltage
VOL1
COMP NTSC
Video maximum gain
GV
COMP NTSC
Contrast characteristics TYP
GCNTTP
COMP NTSC
Contrast characteristics MIN
GCNTMN
COMP NTSC
CXA3017R
VCO must be reset when the panel mode is changed.
Serial bus Mode settings System Panel S/H FRP HUE COL BRT CNT NTSC 009 0 0 0 0 0 0 0 0 0 0 0 0 0 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 128 128 128 128 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 128 0 128 128 128 0 128 128 128 0 128 128 0 0 0 0 0 0 0 0 0 0 0 ALL ON 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 128 180 128 128 128 180 128 ADJ 128 128 ADJ 128 128 ADJ 255 128 ADJ 0 128 ADJ 255 128 ADJ 0 128 ADJ 255 128 ADJ 0 128 ADJ 255 128 ADJ 0 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ BRBRT BRT 1 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 DAC settings USER WHITE DA PSIG RBBLK PIC -BRT VCO LIM BRT CNT CNT LIM OUT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- (--: don't care, ADJ: adjustment, SET: setting)
Item
Symbol
Input Y/C
FCYYC
Y signal frequency response SPAL 005 NTSC 009 NTSC 009 NTSC 005 NTSC 005
FCYCMN COMP NTSC 005
FCYCMP COMP Y/C Y/C Y/C Y/C
Picture quality GSHP1X adjustment variable amount 1 GSHP1N
Picture quality GSHP2X adjustment variable amount 2 GSHP2N
COMP NTSC 005
Picture quality GSHP3X adjustment variable GSHP3N amount 3
COMP NTSC 005
Y signal block
Chroma signal block
- 22 -
-- -- -- -- -- -- -- -- -- -- -- -- -- Y/C SPAL -- SPAL SPAL SPAL
COMP NTSC 009
Picture quality GSHP4X adjustment variable GSHP4N amount 4
COMP NTSC 009
Carrier leak (Y block) CRLEKY COMP
TDYYC
TDYCMN COMP NTSC
Y signal I/O delay time
TDYCMP COMP
TDYDEF
Y/color difference
COMP NTSC
ACC amplitude characteristics 1
ACC1
COMP
COMP NTSC
ACC amplitude characteristics 2
ACC2
COMP
COMP NTSC
APC pull-in range
FAPC
CXA3017R
COMP
VCO must be reset when the panel mode is changed.
Serial bus Mode settings DAC settings BRBRT BRT 1 0 0 0 0 0 0 0 0 0 0 0 0 128 128 128 128 128 128 0 128 128 128 128 128 128 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 128 128 128 0 128 128 128 0 128 128 128 0 0 0 0 0 0 0 0 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 2 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 USER WHITE DA BLK PSIG RBPIC -BRT VCO LIM OUT BRT CNT CNT LIM -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
CXA3017R
Item System Panel S/H FRP HUE COL BRT CNT -- -- ALL ON 128 ALL ON 255 128 150 128 ALL ON ALL ON 128 128 150 128 ALL ON 128 128 150 128 ALL ON 128 128 150 128 ALL ON 128 128 150 128 ALL ON 128 128 150 128 ALL ON 128 128 150 128 ALL ON 128 128 150 128 ALL ON 128 128 150 128 ALL ON 128 128 150 128 ALL ON 128 128 150 128 ALL ON 128 255 128 128 ALL ON 128 0 128 150 128 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 128 128 ALL ON 128 255 128 128
Symbol
Input
Color adjustment GCOLMX characteristics MAX
COMP NTSC
Color adjustment characteristics MIN
GCOLMN
COMP NTSC
HUE adjustment HUEMX characteristics MAX
COMP NTSC
HUE adjustment characteristics MIN
HUEMN
COMP NTSC
Killer operation input level SPAL
ACKN
COMP NTSC
ACKP
COMP
Demodulation output amplitude ratio (NTSC)
VRBN
COMP NTSC
Chroma signal block
- 23 -
SPAL SPAL SPAL SPAL -- -- -- ALL ON 128 128 128 128
VGBN
COMP NTSC
RBN
COMP NTSC
Demodulation output phase difference (NTSC)
GBN
COMP NTSC
Demodulation output amplitude ratio (PAL)
VRBP
COMP
VGBP
COMP
Demodulation output phase difference (PAL)
RBP
COMP
GBP
COMP
Color difference input color adjustment
GEXCMX
Y/color difference
GEXCMN
Y/color difference
Color difference balance
VEXCBL
Y/color difference
VCO must be reset when the panel mode is changed.
(--: don't care, ADJ: adjustment, SET: setting)
Serial bus Mode settings System Panel S/H FRP HUE COL BRT CNT -- 0 128 128 128 128 128 128 128 0 0 128 128 128 80 80 128 128 255 128 255 128 128 128 128 255 128 128 128 128 255 128 ALL ON 128 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 128 128 128 128 128 128 255 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 0 0 0 128 0 0 0 0 0 0 0 128 0 128 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 255 128 128 0 0 128 128 128 128 128 0 0 0 0 0 128 128 128 128 128 -- -- -- -- ALL ON 0 0 ALL ON ALL ON ALL ON ALL ON ALL ON ALL ON ALL ON ALL ON ALL ON 128 128 ADJ 128 128 128 128 ADJ 128 128 128 128 ADJ 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 -- -- -- -- -- -- -- -- -- -- 128 128 128 128 128 -- ALL ON 0 0 128 128 128 128 128 -- ALL ON 0 128 255 128 128 128 128 -- ALL ON 0 0 128 128 128 128 128 -- ALL ON 0 128 0 128 128 255 128 128 128 128 ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ BRBRT BRT 1 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 DAC settings BLK USER WHITE DA PSIG RBPIC VCO -BRT LIM OUT BRT CNT CNT LIM -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- (--: don't care, ADJ: adjustment, SET: setting)
Item
Symbol
Input
Color difference input balance adjustment R
GEXRMX
Y/color difference
GEXRMN
Y/color difference
Color difference input balance adjustment B
GEXBMX
Y/color difference
GEXBMN
Y/color difference
Chroma signal block
G-Y matrix characteristics (NTSC)
VEXGBN
Y/color NTSC difference
VEXGRN
Y/color NTSC difference
RGB signal output block
- 24 -
-- -- -- -- -- -- -- -- -- -- -- -- -- --
G-Y matrix characteristics (PAL)
VEXGBP
Y/color SPAL difference
VEXGRP
Y/color SPAL difference
RGB/PSIG output DC voltage
VOUT
RGB/PSIG output VOUT DC voltage difference
SIG center variable range
VORNG
RGB output/PSIG black limiter operation voltage
VLIMMX
VLIMMN
Amount of change in PSIG output
PSIGMX
PSIGMN
CXA3017R
VCO must be reset when the panel mode is changed.
Serial bus Mode settings System Panel S/H FRP HUE COL BRT CNT -- 0 0 0 0 0 0 0 0 128 128 128 128 128 128 0 0 0 128 128 0 128 128 128 0 128 128 128 128 0 0 128 0 0 0 0 0 0 128 128 0 128 -- -- -- -- -- -- -- 128 ALL ON 128 128 128 128 128 -- 128 ALL ON 128 128 128 128 128 -- ALL ON 128 128 160 128 SET SET -- 255 128 128 ALL ON 128 128 0 -- 128 ALL ON 128 128 255 255 128 -- 128 ALL ON 128 128 128 255 128 -- 128 ALL ON 128 128 128 255 128 128 255 ADJ ADJ BRBRT BRT 1 2 3 3 3 3 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 3 3 3 DAC settings USER WHITE DA BLK PSIG RBPIC -BRT VCO LIM BRT CNT CNT LIM OUT -- -- -- -- -- -- --
Item
Symbol
Input -- -- -- -- -- -- --
Amount of change in user brightness
UBRTMX
UBRTMN
Amount of change in brightness
BRTMX
128 128 ADJ
BRTMN
Amount of change in sub brightness
SBBRT
Difference in gain GRGB between RGB signals
Amount of change in sub-contrast -- -- 0 -- 128 ALL ON 128 128 128 128 128 0 128
SBCNT
128 SET SET
RGB signal output block
- 25 -
-- -- -- -- -- -- -- -- -- -- -- -- -- -- ALL ON 128 128 ALL ON 128 128 ALL ON 128 128 -- ALL ON 128 128 -- -- -- ALL ON 128 128 ADJ ADJ 128 ALL ON 128 128 ADJ ADJ 128 ALL ON 128 128 ADJ ADJ 128 80 80 80 80 60 60 60 60 128 128 128 128 -- -- -- -- -- -- -- -- -- ALL ON 128 128 128 128 128 128 0 0 128 0 128 255 128 128 0 0 0 0 0 ALL ON 128 128 128 128 128
Difference in RGB inverted/non-inverted GINV gain
128
128
0
128 128 ADJ
3
--
Difference in black level potential VBL between RGB signals
128 128 140 230 128 128 140 230 128 128 140 230 128 128 128 128 255 128
128 128 128 128 128 128 128 128 128 128 128 SET 128
128 128 128 128 128 128 128 128 128
0 0 0 0 0 0 0 0 0
128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ
3 3 3 3 3 3 3 3 3
-- -- -- -- -- -- -- -- -- (--: don't care, ADJ: adjustment, SET: setting)
G1
gain
G2
G3
1 adjustment variable range
V 1MN
V 1MX
2 adjustment variable range
V 2MN
V 2MX
PSIG transition time tPSIG
CXA3017R
VCO must be reset when the panel mode is changed.
Serial bus Mode settings System Panel S/H FRP HUE COL BRT CNT BRBRT BRT 1 2 DAC settings WHITE DA USER BBLK PSIG RPIC VCO LIM -BRT BRT CNT CNT LIM OUT
Item
Symbol
Input
RGB output white limiter operation voltage -- -- 0 255 128 128 0 128 0 128 -- 128 128 ALL ON 128 128 128 128 -- -- 0 0 0 128 128 128 0 128 128 0 -- -- 128 128 ALL ON 128 128 255 128 -- -- 128 128 128 ALL ON 128 128 0
VWLIM
ADJ SET
--
Black limiter DC voltage difference
VBLIM
128 ADJ 128 128 ADJ 128 128 ADJ
0 0
-- --
RGB signal output block
White limiter DC voltage difference -- -- 0 0 128 -- 128 128 ALL OFF 128 128 SET 128 128 128
VWLIM
RGB output range when FRP polarity VDROFF inversion is stopped SET 0 0 0 0 0 128 128 128 128 128 128 ON 128 128 128 128 1 1 ON 128 128 128 128 128 128 128 128 128 128 128 128 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NTSC SPAL NTSC -- -- NTSC 009 NTSC 009 NTSC SPAL -- -- -- -- -- ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 -- ALL ON 128 128 128 128 128 -- 128 ALL ON 128 128 150 128 128 -- 128 128 ALL ON 128 128 128 128 -- 128 128 ALL ON 128 128 128 128 -- 128 128 ALL ON 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128
0
128
0
ADJ
3
--
Amount of BPF attenuation
ATBPF
COMP
128 128 128 128 128 128 128 128 128 128 128 128
0 0 0 0 0 0 0 0 0 0 0 0
128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ
3 3 3 3 3 3 3 3 3 3 3 3
-- -- -- -- -- -- -- -- -- -- -- -- (--: don't care, ADJ: adjustment, SET: setting)
Filter characteristics
Sync, TG block
- 26 -
Y/C -- -- -- -- -- --
Amount of TRAP attenuation
ATRAPN
SET
ATRAPP
SET
R-Y and B-Y LPF characteristics
DEMLPF
Input sync signal width sensitivity
WSSEP
Sync separation input sensitivity
VSSEP
HD output delay time
TDSY1
TDSY2
Horizontal pull-in range
HPLLN
HPLLP
Output transition time
tTLH
COMP NTSC
CXA3017R
tTHL
COMP NTSC
VCO must be reset when the panel mode is changed.
Serial bus Mode settings System Panel S/H FRP HUE COL BRT CNT -- 1 0 0 0 -- -- 0 0 0 0 0 0 0 0 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 0 128 128 128 128 -- -- -- -- 0 0 0 0 0 0 0 -- -- -- -- -- -- 128 128 128 0 128 128 0 -- -- 0 0 0 0 0 128 0 1 -- -- -- 128 128 128 128 128 128 128 128 128 128 128 128 128 128 -- -- -- -- -- -- -- -- ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 128 128 ALL ON 128 128 100 128 ALL ON 128 128 128 128 -- -- -- -- -- ON 128 128 128 128 128 128 128 128 -- -- -- -- -- -- -- -- -- -- ON 128 128 128 128 128 128 ADJ 128 128 ADJ -- -- -- -- 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ 128 128 ADJ BRBRT BRT 1 2 3 3 -- -- 3 3 3 3 3 3 3 DAC settings USER WHITE DA BLK PSIG RBPIC VCO -BRT LIM OUT BRT CNT CNT LIM -- -- 7 0 -- -- -- -- -- -- -- (--: don't care, ADJ: adjustment, SET: setting)
Item
Symbol
Input
Cross-point time difference
T
COMP NTSC
HCK duty -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
DTYHC
COMP NTSC
Sync, TG block
DA OUT output voltage
VBKLTH
VBKLTL
External RGB input threshold voltage
VTEXTB
VTEXTW
Propagation delay TD1EXT time between external RGB input and output TD2EXT
External RGB input blanking level
External I/O characteristics
- 27 -
EXTBK
External RGB input output white level
EXTWT
External RGB input TEXMIN minimum pulse width
VCO must be reset when the panel mode is changed.
CXA3017R
CXA3017R
Electrical Characteristic Measurement Method Diagrams
3V SIG6 0V TP40, 43, 45 non-inverted output TD1EXT 100% 50% TD2EXT
Fig. 2. Conditions for measuring the delay between external RGB input and output
T 90% 50% 10% tTLH tTHL T
Fig. 3. Output transition time measurement conditions
Fig. 4. Cross-point time difference measurement conditions
White VG3
Non-inverted output
VG2
3.5V
Black 1.5V
VG1
Input
Fig. 5. characteristics measurement conditions
- 28 -
CXA3017R
DATA
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
ts1
th1
SCLK
50%
tw1H
tw1L
LOAD
50%
ts0
th0
tw2
Fig. 6. Serial transfer block measurement conditions
- 29 -
CXA3017R
Input Waveforms SG No. Waveform
Sine wave video signal: With/without burst Amplitude and frequency variable
SIG1
150mV 143mV
150mV
Value noted on left: 0 dB
Chroma signal: Burst, chroma frequency (3.579545MHz, 4.433619MHz) Chroma phase and burst frequency variable
SIG2
150mV 143mV Value noted on left: 0 dB
Ramp waveform
SIG3
143mV 1H
357mV
5-step staircase waveform
150mV
SIG4
143mV 1H
VL
SIG5
VS fH WS
VL amplitude variable VS variable: 143mV unless otherwise specified WS variable: 4.7s unless otherwise specified fH variable: 15.734kHz (NTSC) or 15.625kHz (PAL) unless otherwise specified
- 30 -
CXA3017R
SG No.
30s 5s
Waveform
VL amplitude variable
SIG6
VL
Horizontal sync signal
75mV Frequency variable
SIG7
143mV
175mV
10-step staircase waveform
SIG8
143mV 1H
357mV
SIN2 2T pulse waveform
SIG9
143mV 1H
357mV
- 31 -
CXA3017R
Electrical Characteristics Measurement Circuit
+12V SW48 V48 +3V ICC2 A 47
TP45 0.01
TP43
TP40
TP38
+15.5V
400p
400p
400p
20000p
100k
100k TP35 TP34
+3V IDD4 A 47 0.01
0.1 ICC1 A 47 49 VCC1 0.22 10k 1 16p 51 VXO IN 0.033 0.1 (D) 0.1 (E) A 52 APC A B 54 R-Y IN 55 C OUT 3.9k 1 56 V REG (B) A B SW57 SW58 V58 58 RESET 1 59 Y IN TP60 0.01 (A) 0.33 62 VSEP TC 15k 2 63 F0 ADJ 64 GND1 61 SYNC IN 60 TEST2 57 C IN SW53 53 B-Y IN 0.01 0.01 48 47 46 45 44
0.1 43 42 41
0.1 40 39 38 37 36
0.1 35 34 33
SIG.CENTER
FB R
FB PSIG
R OUT
GND2
VCC3
RGT1
PSIG
FB G
FB B
G OUT
B OUT
GND3
DWN
VCC2
VDD2
DA OUT 32 VD 31 EN2 30 EN1 29 XEN1 28 VCK1 27 VCK2 26 VCK3 25 VCK4 24 VST 23 XVST 22 HD 21 PCG 20 XPCG 19 HCK1 18 HCK2 17
TP32 TP31 TP30 TP29 TP28 TP27 TP26 TP25 TP24 TP23 TP22 TP21 TP20 TP19 TP18 TP17
50 VXO OUT
B SW54 TP55
TEST1
CLR
XHST1
15
EXT G
EXT R
EXT B
LOAD
TRAP
DATA
SCLK
HST2
VDD1
RPD
BLK
HST1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
VSS
+3V IDD3 A 47 0.01
SW1 SW2 SW3 BABABA 3
TP6
TP7 TP8 10k 3.3
TP10 TP11 TP12 TP13 TP14 TP15 TP9 6800p
(C)
1 Used crystal: KINSEKI CX-5F Frequency deviation: within 30ppm, frequency temperature characteristics: within 30ppm, load capacity: 16pF NTSC: 3.579545MHz PAL: 4.433619MHz
2 Resistance value tolerance: 2%, temperature coefficient: 200ppm or less 3 Trap (TDK) NTSC: NLT4532-S3R6B PAL: NLT4532-S4R4
- 32 -
CXA3017R
Description of Operation The CXA3017R incorporates the three functions of an RGB decoder block, an RGB driver block and a timing generator (TG) block onto a single chip using Bi-CMOS technology. 1) RGB decoder block * Input mode switching The input mode (composite input, Y/C input, Y/color difference input) can be switched by the serial bus settings. During composite input: The composite signal is input to Pins 57, 59 and 61. During Y/C input: The Y signal is input to Pins 59 and 61, and the C signal to Pin 57. During Y/color difference input: The Y signal is input to Pins 59 and 61, the B-Y signal to Pin 53, and the R-Y signal to Pin 54. * System switching The input system (NTSC, SPAL, DPAL) can be switched by the serial bus settings. (DPAL uses external delay lines.) * Trap, BPF The center frequency of the built-in trap and BPF can be switched to 3.58MHz during NTSC and 4.43MHz during PAL. During composite input, the Y signal enters the trap circuit and the C signal enters the BPF. These signals do not pass through the trap or BPF during Y/C input and Y/color difference input. * ACC detection, ACC amplifier The amplitude of the burst signal output from the ACC amplifier is detected and the ACC amplifier is controlled to maintain the burst signal amplitude at a constant level. * VXO, APC detection The VXO local oscillation circuit is a crystal oscillation circuit. The phases of the input burst signal and the VXO oscillator output are compared in the APC detection block, and the detective output is used to form a PLL that controls the VXO oscillation frequency, which means that the need for adjustments is eliminated. * External inputs These are digital inputs with two thresholds. When one of the RGB inputs is higher than the lower threshold Vth1 ( 1.0V), all RGB outputs go to black level. When the higher threshold Vth2 ( 2.0V) is exceeded, the output for only the signal in question goes to white level, while the other outputs remain at black level.
- 33 -
CXA3017R
2) RGB driver block * correction In order to support the characteristics of LCD panels, the I/O characteristics are as shown in Fig. 1. The gain transition point A voltage changes as shown in Fig. 2 by adjusting the serial bus register 1, and the transition point B voltage changes as shown in Fig. 3 by adjusting 2.
Output B A
Output A A' B
Output A
B'
B
Input
Input
Input
Fig. 1
Fig. 2
Fig. 3
* Sample-and-hold circuit As LCD panels sample RGB signals simultaneously, RGB signals output from the CXA3017R must be sampled-and-held in sync with the LCD panel drive pulses.
R S/H1 S/H4
HCK1
G
S/H2
S/H4
A
B B S/H3 S/H4 C SH1 SH2 SH3 SH4
RGT = H (normal) SHS1 SH1 B SHS2 A SHS3 C
RGT = L (right/left inversion) SHS1 SH1 SH2 B A SHS2 A C SHS3 C B SH1: R signal SH pulse SH2: G signal SH pulse SH3: B signal SH pulse SH4: RGB signal SH pulse SHS1,2,3: Serial data settings
SH2 Through Through Through SH3 SH4 A C C B B A
SH3 Through Through Through SH4 C B A
The sample-and-hold circuit performs sample and hold by receiving the SH1 to SH4 pulses from the TG block. Since LCD panels perform color coding using an RGB delta arrangement, each horizontal line must be compensated by 1.5 dots. This relationship is reversed during right/left inversion. This compensation timing is also generated by the TG block. The sample-and-hold timing changes according to the phase relationship with the HCK1 pulse, so the timing should be set to SHS1, 2 or 3 in accordance with the actual board. - 34 -
CXA3017R
* RGB output RGB outputs (Pins 40, 43 and 45) are inverted each horizontal line by the FRP pulse (internal pulse) supplied from the TG block as shown in the figure below. Feedback is applied so that the center voltage (Vsig center) of the output signal matches the reference voltage (VCC2 + GND2)/2 (or the voltage input to SIG CENTER (Pin 48)). In addition, the white level output is clipped at the limiter operation point that is set by the serial bus register WHITE LIM, and the black level output is clipped at the limiter operation point that is set by the serial bus register BLKLIM.
Video IN
FRP Black level limiter
RGB OUT
White level limiter Vsig center White level limiter
Black level limiter
3) TG block * PLL and AFC circuits The TG block contains a PLL circuit phase comparator and frequency division counter and a VCO circuit, and comprises a PLL circuit. The PLL error detection signal is generated by the HSYNC block, and the integral value of the phase comparison output of the entire bottom of HSYNC and the internal frequency division counter becomes RPD (Pin 9). The CXA3017R controls the internal VCO with the RPD output to stabilize the oscillation frequency at 690fH (NTSC) or 716fH (PAL) for the LCX005BK/BKB and LCX024AK/AKB, and 1034fH (NTSC) or 1072fH (PAL) for the LCX009AK/AKB, LCX027AK/AKB and DCX501BK. The PLL of this system is adjusted by adjusting the serial bus register VCO so that the RPD output waveform is constant near VSYNC as shown in the figure
Video signal
RPD (Pin 9)
Adjust to a horizontal waveform.
Horizontal AFC adjustment * H position The horizontal display position can be set at 2fH intervals in 32 different ways by the serial bus settings. Note that the delay difference between the RGB signal and the drive pulse differs according to the board, so adjust the serial bus register H position so that the picture center matches the center of the LCD panel. - 35 -
CXA3017R
* Right/left inversion The LCD panel is arranged in a delta arrangement, where identical signal lines are offset by 1.5 dots from adjoining lines. For this reason, a 1.5-bit offset is attached to the horizontal start pulse (HST) between odd lines and even lines. HCK and S/H are also 1.5-bit offset. Therefore, when the panel is driven by left scan (Reverse scan), this offset relationship is inverted for even and odd lines. Moreover, since the dot arrangement is asymmetrical, the HST position is also changed. RGT = H: Right scan mode RGT = L: Left scan mode (H and L are the LCD panel input levels.)
Right scan (Normal scan) Left scan (Reverse scan)
H SCANNER
V SCANNER
Active area
LCD panel
* Wide mode Wide mode can be selected by setting wide mode with the serial bus aspect switching register. In this mode, aspect ratio conversion is performed by pulse elimination processing to enable 16:9 quasi-WIDE display. Vertical pulse elimination scanning of 1/4 for NTSC and 10/28 for PAL is performed and the video signal is compressed in order to achieve a 16:9 aspect ratio during the wide mode period. In addition, high-speed scan is performed in areas outside of the active area to display black in the upper 28 lines and the lower 28 (27) lines. Black display is performed by limiting the video signal input during the V blanking period and writing a black level signal in its place.
Vertical high-speed scan 28 LINES (28 LINES)
Black active area
225 LINES (218 LINES)
Active area
Active area
169 LINES (163 LINES)
Black active area 4:3 display 16:9 display
28 LINES (27 LINES)
Vertical pulse elimination scan
Numbers inside parentheses are for the LCX005BK/BKB and LCX024AK/AKB; other numbers are for the LCX009AK/AKB, LCX027AK/AKB and DCX501BK. - 36 -
CXA3017R
* AC driving of LCD panels during no signal HST, XHST, HCK1, HCK2, VST, XVST, VCK1, VCK2, PCG, XPCG, EN, XEN, HD, VD, and FRP (internal pulse) are made to run freely so that the LCD panel is AC driven even when there is no composite sync from the SYNCIN pin. During this time, the HSYNC separation circuit stops and the PLL counter is made to run freely. In addition, the VSYNC separation circuit is also stopped, so the auxiliary V counter is used to create the reference pulse for generating VD, VST and XVST. The cycle of this V counter is designed to be 525/2H for NTSC and 625/2H for PAL. However, when there is no vertical sync signal for 5 fields, the no signal state is assumed and the free running VD, VST and XVST pulses are generated from the next field. In addition, RPD is kept at high impedance when there is no signal in order to prevent the AFC circuit from causing errors due to phase comparison.
- 37 -
CXA3017R
Description of Serial Control Operation 1) Control method Control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of SCLK. This loading operation starts from the falling edge of LOAD and is completed at the next rising edge. Digital block control data is established by the vertical sync signal, so if data is transferred multiple times for the same item, the data immediately before the vertical sync signal is valid. Analog (electronic attenuator) block control data becomes valid each time the LOAD signal is input.
DATA
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCLK LOAD
Serial transfer timing
2) Serial data map The serial data map is as follows. D15 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D10 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 D9 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 D8 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 - 38 - D7 D6 D5 D4
External VSYNC
D3
D2
D1
D0
S/H phase Aspect 0 0
System
Input switching
Panel 2 TEST1
Supported panels
Y/color VD HD difference polarity polarity clamp
DWN RGT2 RGT1 0
PLL adjustment 2
SYNC TEST2 GEN
P-FRP FRP
FRP FRP4096 TEST5 inversion inversion inversion inversion TEST4 TEST3 stop stop PLL adjustment 1
0
0
0
POWER SAVE
0
SYNC detection

H-POSITION HD-POSITION HUE COLOR BRIGHT CONTRAST R-BRIGHT B-BRIGHT -1 -2 : don't care
CXA3017R
Serial data map (cont.) D15 1 1 1 1 1 1 1 1 1 1 D14 0 0 0 0 0 0 0 0 0 1 D13 0 0 0 0 0 0 0 0 0 1 D12 0 0 0 0 0 0 0 0 1 0 D11 1 1 1 1 1 1 1 1 0 0 D10 0 0 0 0 1 1 1 1 0 0 D9 0 0 1 1 0 0 1 1 0 0 D8 0 1 0 1 0 1 0 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0
PSIG-BRIGHT R-CONTRAST B-CONTRAST BLK LIM PICTURE USER-BRIGHT VCO WHITE LIM DA OUT
TEST6 : don't care
3) Serial data mode settings
(X: don't care)
* Input switching This switches the input signal format. D1 D0 0 X Composite input (default) 1 0 Y/C input 1 1 Y/color difference input * System switching This switches the input video signal system. D3 D2 0 0 NTSC (default) 0 1 TEST 1 0 D-PAL 1 1 S-PAL * External VSYNC Internal VSYNC separation is not performed and an externally input VSYNC is used. D4 0 OFF (internal separation) (default) 1 ON (external input) * Aspect switching This switches the video display aspect. D5 0 4:3 (normal) (default) 1 16:9 (letterbox, pulse elimination display)
- 39 -
CXA3017R
* Sample-and-hold phase This switches the sample-and-hold timing. D7 D6 0 0 SHS1 (default) 0 1 SHS2 1 0 SHS3 1 1 Through (sample-and-hold not performed) * Supported panels This switches the supported panels. D3 D2 D1 D0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DCX501BK DCX501BK DCX501BK DCX501BK DCX501BK Supported panels LCX005BK/BKB single LCX024AK/AKB single LCX009AK/AKB single LCX027AK/AKB single LCX005BK/BKB + (DCX501BK) LCX024AK/AKB + (DCX501BK) (default) LCX009AK/AKB + (DCX501BK) LCX027AK/AKB + (DCX501BK) -- single -- -- + (LCX005BK/BKB) + (LCX024AK/AKB) + (LCX009AK/AKB) + (LCX027AK/AKB) Two-panel simultaneous drive mode The supported panels are the main panel and the sub panel (the panel noted inside the parentheses). The video is not displayed correctly on the sub panel for combinations of the LCX005BK (BKB)/024AK (AKB) and the DCX501BK. Therefore, the sub panel back light should be turned off. Two-panel simultaneous display is possible with combinations of the LCX009AK (AKB)/027AK (AKB) and the DCX501BK (only when RGT1 = RGT2). However, when the right/left inversion directions of the main and sub panels differ (RGT1 RGT2), the picture is not displayed correctly due to the line offset. Therefore, use Panel 2 mode in these cases.
* TEST1 This is the test mode. Set to normal mode. D4 0 Normal mode (default) 1 TEST mode * Panel 2 Set this when the right/left inversion direction of the two panels differs (RGT1 RGT2) during two-panel simultaneous drive using the LCX009AK (AKB)/027AK (AKB)and the DCX501BK. D5 0 OFF (default) 1 ON Notes) 1. The VST connection changes in this mode, so an external inverter is required. 2. Set sample and hold to OFF (through) in this mode. 3. When the right/left inversion direction of the two panels differs (RGT1 RGT2), the video display start position of the sub panel is advanced by 1H. 4. RGT1 and RGT2 can also be set the same in this mode. - 40 -
CXA3017R
* HD polarity This switches the HD output (Pin 21) polarity. D0 0 Positive polarity (default) 1 Negative polarity * VD polarity This switches the VD output (Pin 31) polarity. D1 0 Positive polarity (default) 1 Negative polarity * Y/color difference clamp This switches the position at which the R-Y and B-Y input signals are clamped during Y/color difference input mode. D2 0 Pedestal position (default) 1 SYNC position * TEST2 This is the test mode. Set to normal mode. D3 0 Normal mode (default) 1 TEST mode * SYNC GEN This sets the sync generator function. Outputs other than VD and HD of the TG block are stopped. D4 0 OFF (default) 1 ON * RGT1 (right/left inversion 1) This switches the DCX501BK right/left inverted display timing and the RGT1 output (Pin 34). D5 0 OFF (normal display) (default) 1 ON (right/left inverted display) * RGT2 (right/left inversion 2) This switches the LCX005BK (BKB)/009AK (AKB)/024AK (AKB)/027AK (AKB)right/left inverted display timing. D6 0 OFF (normal display) (default) 1 ON (right/left inverted display) * DWN (up/down inversion) This switches the DCX501BK up/down inverted display timing and the DWN output (Pin 35). D7 0 OFF (normal display) (default) - 41 -
CXA3017R
* TEST3 This is the test mode. Set to normal mode. D0 0 Normal mode (default) 1 TEST mode * TEST4 This is the test mode. Set to normal mode. D1 0 Normal mode (default) 1 TEST mode * FRP4096 inversion This further inverts the polarity of the RGB output that is inverted every 1H for 4096 fields. D2 0 OFF (default) 1 ON * FRP inversion stop This stops R, G and B output polarity inversion. D3 0 OFF (1H inversion) (default) 1 ON (polarity not inverted) * P-FRP inversion stop This stops PSIG output polarity inversion. D4 0 OFF (1H inversion) (default) 1 ON (polarity not inverted) * FRP inversion This switches the FRP output inversion cycle. D5 0 1H inversion (default) 1 1 field inversion * TEST5 This is the test mode. Set to normal mode. D6 0 Normal mode (default) 1 TEST mode * Sync detection This prevents (as much as possible) the vertical sync from being lost during weak magnetic field signal input. Set to ON (0). D0 0 ON (default) 1 OFF - 42 -
CXA3017R
* POWER SAVE This stops HST1/XHST1 in order to reduce the DCX501BK current consumption. Set to OFF (0). D2 0 OFF (default) 1 ON (HST1/XHST1 stopped) * PLL adjustment 1, 2 These set the PLL adjustment. D7 D6 0 0 (default) 0 1 Set D7 = 0, D6 = 1. 1 0 1 1 * H position setting This sets the horizontal display start position. (2fH intervals in 32 different ways) D4 D3 D2 D1 D0 0 0 0 0 0 : : : : : 1 0 0 0 0 (default) : : : : : 1 1 1 1 1 Variable in 2fH (= 1 bit) increments
CLK (internal) 10001 HST 10000 01111 1 step 1 step
* HD phase setting This sets the HD output (Pin 21) phase. (4fH intervals in 32 different ways) D4 D3 D2 D1 D0 0 0 0 0 0 (default) : : : : : 1 1 1 1 1 Variable in 4fH (= 1 bit) increments
HSYNC HD 00000 11111 31 steps
- 43 -
CXA3017R
4) Serial data electronic attenuator (D/A converter) settings D7 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 -- D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- D3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- D2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- D1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
* HUE * COLOR * BRIGHT * CONTRAST * R-BRT * B-BRT * -1 * -2 * PSIG-BRT * R-CONT * B-CONT * BLK LIM * PICTURE * USER-BRIGHT * VCO * WHITE LIM
(default) (default) (default) (default) (default) (default) (default) (default) (default) (default) (default) (default) (default) (default) (default) (default)
5) DA OUT This controls the DC level (0 to 3V, 8 steps) of the DA OUT (Pin 32) DAC output. D7 -- D6 -- D5 -- D4 -- D3 -- D2 0 D1 0 D0 0
DA OUT
(default)
6) TEST6 TEST6 is a test mode which results automatically if data is sent to these addresses, regardless of the data contents. For this reason, do not perform data transfer using these addresses. D15 1 D14 D13 1 1 D12 0 D11 0 D10 0 D9 0 D8 0 D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXX
- 44 -
CXA3017R
DCX501BK Color Coding Diagram The CXA3017R supports LCD panels which perform color coding in a delta arrangement. The shaded areas in the figure are not displayed. DCX501BK Pixel Arrangement
HSW1
HSW2
HSW3
HSW266
HSW267
HSW268
dummy1
R
G
B
R
G
B
R
G
B
R
G
B
R
G
Photo-shielding area B R G
Vline1 R
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
Vline2
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
Vline3
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
225
R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R Active area Vline224 R G B R G B R G B R G B R G B R G Vline225 R B R G B R G B R G B R G B R G B R dummy2 Precharge SW 2 800 803 1
1 1 227
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
- 45 -
CXA3017R
LCX027AK/AKB Pixel Arrangement
dummy1 to 4
HSW1
HSW3
HSW266
HSW268
dummy5 to 8
dummy1
B
R
G
B
R
G
B
R
G
B
R
G
B
R
dummy2
R
G
B
R
G
B
R
G
B
R
G
B
R
G
G B R Photo-shielding area B R G
Vline1 R
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
Vline2
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
Vline3 R
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
2 1 225 228
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
Active area Vline224 R G B R G B R G B R G B R G B R G
Vline225 R
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
dummy3
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
14 827
800
13
- 46 -
CXA3017R
LCX024AK/AKB Pixel Arrangement
HSW1
HSW2
HSW3
HSW176
HSW178
HSW179
dummy2
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
Vline1 B
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
Vline2
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
218 2
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
G
B
R
G
B
R G Active area G B R
B
R
G
B
R
G
B
R
G
B
R
Vline218
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
dummy3 B
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
dummy4
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
3
521 537
13
- 47 -
228
Vline3
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
2
dummy1
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R G B Photo-shielding area
R
CXA3017R
LCX009AK/AKB Pixel Arrangement
dummy1 to 4
HSW1
HSW2
HSW267
HSW268
dummy5 to 8
dummy1 dummy2 R
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
Photo-shielding area B R G
Vline1
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
Vline2
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
Vline3 R
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
2
G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R Vline224 R G B R G B Active area R G B R G B R G B R G Vline225 B R G B R G B R G B R G B R G B R 14 800 827 13
- 48 -
1
dummy3
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
225
228
CXA3017R
LCX005BK/BKB Pixel Arrangement
dummy1
HSW1
HSW2
HSW3
HSW174
HSW175
dummy2 to 5
dummy1 B
G
B
R
G
B
R
G
B
R
G
B
R
G
B
dummy2
R
G
B
R
G
B
R
G
B
R
G
B
R
R G B R Photo-shielding area G B R G
Vline1 Vline2 B
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
218 2
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
Vline217 B
G
B
R
G
B
R G Active area G B R
B
R
G
B
R
G
B
R
G
B
R
Vline218
R
G
B
R
G
B
R
G
B
R
G
B
R
G
dummy3 B
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
dummy4
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
3
521 537
13
- 49 -
222
Vline3
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
2
Horizontal Direction Timing Chart -- NTSC/PAL LCX005 + (DCX501), LCX024 + (DCX501) RGT1 = 0, RGT2 = 0, HP = 10000, HD = 00000 Cycle value NTSC: 690 ck, PAL: 716 ck
(MCK) 4.7s (53fH)
(SYNC) 4.7s (53fH) 2.0s (22fH) 22.5fH 13fH 4.5s (50fH)
(BLK)
HD
HST1
HST2
HCK1
HCK2
SH1 (Internal)
SH2 (Internal)
SH3 (Internal)
SH4 (Internal) 6.0s (67.5fH) 5.0s (56.5fH)
FRP (Internal)
- 50 -
6.5s (73fH) 3.0s (34fH) 3.0s (34fH) 3.0s (34fH) 0.5s (6fH) 5.0s (56fH)
VCK1
VCK2
PCG
EN1
EN1 (PAL)
EN2 (PAL)
CLR
VCK3
VCK4
VST/VD
ODD LINE CXA3017R
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX005/024 drive pulses: HST2, HCK1, HCK2, EN2, CLR, VCK3, VCK4, VST(EN2 is high during NTSC.) DCX501 drive pulses: HST1, HCK1, HCK2, VCK1, VCK2, PCG, EN1 and VST (HST1, PCG, EN1 and VST output inverted pulses XHST1, XPCG, XEN1 and XVST.)
Horizontal Direction Timing Chart -- NTSC/PAL LCX005 + (DCX501), LCX024 + (DCX501)
RGT1 = 0, RGT2 = 0, HP = 10000, HD = 00000 Cycle value NTSC: 690 ck, PAL: 716 ck
(MCK) 4.7s (53fH)
(SYNC) 4.7s (53fH) 2.0s (22fH) 21fH 13fH 4.5s (50fH)
(BLK)
HD
HST1
HST2
HCK1
HCK2
SH1 (Internal)
SH2 (Internal)
SH3 (Internal)
SH4 (Internal) 6.0s (66fH) 5.0s (55fH)
FRP (Internal)
- 51 -
6.5s (73fH) 3.0s (34fH) 3.0s (34fH) 3.0s (34fH) 0.5s (6fH) 5.0s (56fH)
VCK1
VCK2
PCG
EN1
EN1 (PAL)
EN2 (PAL)
CLR
VCK3
VCK4
VST/VD
EVEN LINE CXA3017R
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX005/024 drive pulses: HST2, HCK1, HCK2, EN2, CLR, VCK3, VCK4 and VST (EN2 is high during NTSC.) DCX501 drive pulses: HST1, HCK1, HCK2, VCK1, VCK2, PCG, EN1 and VST (HST1, PCG, EN1 and VST output inverted pulses XHST1, XPCG, XEN1 and XVST.)
Horizontal Direction Timing Chart -- NTSC/PAL LCX005 + (DCX501), LCX024 + (DCX501)
HST1 and HST2 during right/left inversion
(MCK) 4.7s (53fH) 4.7s (53fH) 2.0s (22fH) ODD LINE 22.5fH 13fH 4.5s (50fH)
(SYNC)
(BLK)
HD
RGT1 = 0 or 1, RGT2 = 0
HST1
HST2
HCK1
HCK2 EVEN LINE 21fH 13fH
RGT1 = 0 or 1, RGT2 = 0
HST1
HST2
HCK1
HCK2 ODD LINE 22fH 13fH
- 52 -
EVEN LINE
RGT1 = 0 or 1, RGT2 = 1
HST1
HST2
HCK1
HCK2
RGT1 = 0 or 1, RGT2 = 1
HST1 23.5fH 13fH
HST2
HCK1
HCK2
CXA3017R
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. HST1: DCX501 horizontal display start pulse (inverted pulse XHST1 output) HST2: LCX005/024 horizontal display start pulse
Horizontal Direction Timing Chart -- NTSC/PAL LCX009 + (DCX501), LCX027 + (DCX501) DCX501 + (LCX009), DCX501 + (LCX027), DCX501 + (LCX005), DCX501 + (LCX024)
4.7s (79fH) 4.7s (79fH) 2.0s (34fH) 4.5s (75fH) 20.5fH 12fH
RGT1 = 0, RGT2 = 0, HP = 10000, HD = 00000 Cycle value NTSC: 1034 ck, PAL: 1072 ck
(MCK)
(SYNC)
(BLK)
HD
HST1
HST2
HCK1
HCK2
SH1 (Internal)
SH2 (Internal)
SH3 (Internal)
SH4 (Internal) 6.0s (101.5fH) 5.0s (84.5fH)
FRP (Internal)
- 53 -
6.5s (109fH) 3.0s (50fH) 3.0s (50fH) 3.0s (50fH) 0.5s (8fH) 5.0s (84fH)
VCK1
VCK2
PCG
EN1
EN1 (PAL)
EN2 (PAL)
CLR
VCK3, (4)
VCK4, (3)
VST/VD
ODD LINE CXA3017R
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. In LCX009 + (DCX501) and DCX501 + (LCX009) modes, the VCK3 and VCK4 polarities are inverted. (VCK(3) and VCK(4)) LCX009/027, 005/024 drive pulses: HST2, HCK1, HCK2, EN2, CLR, VCK3, VCK4 and VST (EN2 is high during NTSC.) DCX501 drive pulses: HST1, HCK1, HCK2, VCK1, VCK2, PCG, EN1 and VST (HST1, PCG, EN1 and VST output inverted pulses XHST1, XPCG, XEN1 and XVST.)
Horizontal Direction Timing Chart -- NTSC/PAL LCX009 + (DCX501), LCX027 + (DCX501) DCX501 + (LCX009), DCX501 + (LCX027), DCX501 + (LCX005), DCX501 + (LCX024)
4.7s (79fH)
RGT1 = 0, RGT2 = 0, HP = 10000, HD = 00000 Cycle value NTSC: 1034 ck, PAL: 1072 ck
(MCK)
(SYNC) 4.7s (79fH) 2.0s (34fH) 4.5s (75fH) 19fH
(BLK)
HD
HST1
12fH
HST2
HCK1
HCK2
SH1 (Internal)
SH2 (Internal)
SH3 (Internal)
SH4 (Internal) 6.0s (100fH) 5.0s (83fH)
FRP (Internal)
- 54 -
6.5s (109fH) 3.0s (50fH) 3.0s (50fH) 0.5s (8fH) 3.0s (50fH) 5.0s (84fH)
VCK1
VCK2
PCG
EN1
EN1 (PAL)
EN2 (PAL)
CLR
VCK3, (4)
VCK4, (3)
VST/VD
EVEN LINE
CXA3017R
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. In LCX009 + (DCX501) and DCX501 + (LCX009) modes, the VCK3 and VCK4 polarities are inverted. (VCK(3) and VCK(4)) LCX009/027, 005/024 drive pulses: HST2, HCK1, HCK2, EN2, CLR, VCK3, VCK4 and VST (EN2 is high during NTSC.) DCX501 drive pulses: HST1, HCK1, HCK2, VCK1, VCK2, PCG, EN1 and VST (HST1, PCG, EN1 and VST output inverted pulses XHST1, XPCG, XEN1 and XVST.)
Horizontal Direction Timing Chart -- NTSC/PAL LCX009 + (DCX501), LCX027 + (DCX501)
HST1 and HST2 during right/left inversion, RGT2 = 0
(MCK) 4.7s (79fH) 4.7s (79fH) 2.0s (34fH) ODD LINE 20.5fH 4.5s (75fH) 12fH
(SYNC)
(BLK)
HD
HST1
RGT1 = 0, RGT2 = 0
HST2
HCK1
HCK2 EVEN LINE 19fH 12fH
HST1
RGT1 = 0, RGT2 = 0
HST2
HCK1
HCK2 ODD LINE 23.5fH 20.5fH 12fH 12fH
- 55 -
EVEN LINE
HST1
RGT1 = 1, RGT2 = 0
HST2
HCK1
HCK2 22fH 19fH 12fH 12fH
HST1
RGT1 = 1, RGT2 = 0
HST2
HCK1
HCK2
CXA3017R
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. HST1: DCX501 horizontal display start pulse (inverted pulse XHST1 output) HST2: LCX009/027 horizontal display start pulse
Horizontal Direction Timing Chart -- NTSC/PAL LCX009 + (DCX501), LCX027 + (DCX501)
HST1 and HST2 during right/left inversion, RGT2 = 1
(MCK) 4.7s (79fH) 4.7s (79fH) 2.0s (34fH) 4.5s (75fH) 23fH 20fH 12fH 12fH
(SYNC)
(BLK)
HD
HST1
RGT1 = 0, RGT2 = 1
ODD LINE
HST2
HCK1
HCK2 24.5fH 21.5fH 12fH 12fH
HST1
RGT1 = 0, RGT2 = 1
EVEN LINE
HST2
HCK1
- 56 -
HCK2 20fH 12fH
HST1
RGT1 = 1, RGT2 = 1
ODD LINE
HST2
HCK1
HCK2 21.5fH 12fH
HST1
RGT1 = 1, RGT2 = 1
EVEN LINE
HST2
HCK1
HCK2
CXA3017R
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. HST1: DCX501 horizontal display start pulse (inverted pulse XHST1 output) HST2: LCX009/027 horizontal display start pulse
Horizontal Direction Timing Chart -- NTSC/PAL DCX501 + (LCX009), DCX501 + (LCX027)
HST1 and HST2 during right/left inversion, RGT1 = 0
(MCK) 4.7s (79fH)
(SYNC) 4.7s (79fH) 2.0s (34fH) 4.5s (75fH) 20.5fH 12fH
(BLK)
HD
HST1
RGT1 = 0, RGT2 = 0
ODD LINE
HST2
HCK1
HCK2 19fH 12fH
HST1
RGT1 = 0, RGT2 = 0
EVEN LINE
HST2
HCK1
- 57 -
HCK2 20.5fH 23.5fH 12fH 12fH
HST1
RGT1 = 0, RGT2 = 1
ODD LINE
HST2
HCK1
HCK2 19fH 22fH 12fH 12fH
HST1
RGT1 = 0, RGT2 = 1
EVEN LINE
HST2
HCK1
HCK2
CXA3017R
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. HST1: DCX501 horizontal display start pulse (inverted pulse XHST1 output) HST2: LCX009/027 horizontal display start pulse
Horizontal Direction Timing Chart -- NTSC/PAL DCX501 + (LCX009), DCX501 + (LCX027)
HST1 and HST2 during right/left inversion, RGT1 = 1
(MCK) 4.7s (79fH) 4.7s (79fH) 2.0s (34fH) 20fH 23fH 4.5s (75fH) 12fH 12fH
(SYNC)
(BLK)
HD
HST1
RGT1 = 1, RGT2 = 0
ODD LINE
HST2
HCK1
HCK2 21.5fH 24.5fH 12fH 12fH
HST1
RGT1 = 1, RGT2 = 0
EVEN LINE
HST2
HCK1
- 58 -
HCK2 20fH 12fH
HST1
RGT1 = 1, RGT2 = 1
ODD LINE
HST2
HCK1
HCK2 21.5fH 12fH
HST1
RGT1 = 1, RGT2 = 1
EVEN LINE
HST2
HCK1
HCK2
CXA3017R
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. HST1: DCX501 horizontal display start pulse (inverted pulse XHST1 output) HST2: LCX009/027 horizontal display start pulse
Horizontal Direction Timing Chart -- NTSC/PAL DCX501 + (LCX005), DCX501 + (LCX024)
HST1 and HST2 during right/left inversion
(MCK) 4.7s (79fH)
(SYNC) 4.7s (79fH) 2.0s (34fH) 20.5fH 4.5s (75fH) 12fH
(BLK)
HD
HST1
RGT1 = 0, RGT2 = 0 or 1
ODD LINE
HST2
HCK1
HCK2 19fH 12fH
HST1
RGT1 = 0, RGT2 = 0 or1
EVEN LINE
HST2
HCK1
- 59 -
HCK2 20fH 23fH 12fH 12fH
HST1
RGT1 = 1, RGT2 = 0 or 1
ODD LINE
HST2
HCK1
HCK2 21.5fH 24.5fH 12fH 12fH
HST1
RGT1 = 1, RGT2 = 0 or 1
EVEN LINE
HST2
HCK1
HCK2
CXA3017R
Note) The first (MCK), second (SYNC) and third (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. HST1: DCX501 horizontal display start pulse (inverted pulse XHST1 output) HST2: LCX005/024 horizontal display start pulse
Vertical Direction Timing Chart -- NTSC LCX005 + (DCX501), LCX024 + (DCX501)
: Display start line : Display end line
(SYNC)
(BLK)
VD
VST
HD
HST1
HST2
VCK2, 3
VCK1, 4
FRP (Internal)
FRP (Internal) 1F inversion
- 60 -
ODD FIELD
PCG
EN1
EN2
CLR
BLK
SBLK (Internal)
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX005/024 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.) CXA3017R
Vertical Direction Timing Chart -- NTSC LCX005 + (DCX501), LCX024 + (DCX501)
: Display start line : Display end line
(SYNC)
(BLK)
VD
VST
HD
HST1
HST2
VCK2, 3
VCK1, 4
FRP (Internal)
- 61 -
EVEN FIELD
FRP (Internal) 1F inversion
PCG
EN1
EN2
CLR
BLK
SBLK (Internal)
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX005/024 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.) CXA3017R
Vertical Direction Timing Chart -- PAL LCX005 + (DCX501), LCX024 + (DCX501)
: Display start line : Display end line
(SYNC)
(BLK)
VD
VST
HD
HST1
HST2
VCK2, 3
VCK1, 4
FRP (Internal)
- 62 -
ODD FIELD
FRP (Internal) 1F inversion
PCG
EN1
EN2
CLR
BLK
SBLK (Internal)
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX005/024 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
CXA3017R
Vertical Direction Timing Chart -- PAL LCX005 + (DCX501), LCX024 + (DCX501)
: Display start line : Display end line
(SYNC)
(BLK)
VD
VST
HD
HST1
HST2
VCK2, 3
VCK1, 4
FRP (Internal)
- 63 -
EVEN FIELD
FRP (Internal) 1F inversion
PCG
EN1
EN2
CLR
BLK
SBLK (Internal)
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX005/024 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.) CXA3017R
Vertical Direction Timing Chart -- NTSC LCX009 + (DCX501), LCX027 + (DCX501), DCX501 + (LCX009), DCX501 + (LCX027), DCX501 + (LCX005), DCX501 + (LCX024)
: Display start line : Display end line
(SYNC)
(BLK)
VD
VST
HD
HST1
HST2
VCK1, 4, (3)
VCK2, 3, (4)
FRP (Internal)
- 64 -
ODD FIELD
FRP (Internal) 1F inversion
PCG
EN1
EN2
CLR
BLK
SBLK (Internal)
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. In LCX009 + (DCX501) and DCX501 + (LCX009) modes, the VCK3 and VCK4 polarities are inverted. (VCK(3) and VCK(4)) LCX009/027 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
CXA3017R
Vertical Direction Timing Chart -- NTSC LCX009 + (DCX501), LCX027 + (DCX501), DCX501 + (LCX009), DCX501 + (LCX027), DCX501 + (LCX005), DCX501 + (LCX024)
: Display start line : Display end line
(SYNC)
(BLK)
VD
VST
HD
HST1
HST2
VCK1, 4, (3)
VCK2, 3, (4)
FRP (Internal)
- 65 -
EVEN FIELD
FRP (Internal) 1F inversion
PCG
EN1
EN2
CLR
BLK
SBLK (Internal)
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. In LCX009 + (DCX501) and DCX501 + (LCX009) modes, the VCK3 and VCK4 polarities are inverted. (VCK(3) and VCK(4)) LCX009/027 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
CXA3017R
Vertical Direction Timing Chart -- PAL LCX009 + (DCX501), LCX027 + (DCX501), DCX501 + (LCX009), DCX501 + (LCX027), DCX501 + (LCX005), DCX501 + (LCX024)
: Display start line : Display end line
(SYNC)
(BLK)
VD
VST
HD
HST1
HST2
VCK1, 4, (3)
VCK2, 3, (4)
FRP (Internal)
- 66 -
ODD FIELD
FRP (Internal) 1F inversion
PCG
EN1
EN2
CLR
BLK
SBLK (Internal)
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. In LCX009 + (DCX501) and DCX501 + (LCX009) modes, the VCK3 and VCK4 polarities are inverted. (VCK(3) and VCK(4)) LCX009/027 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
CXA3017R
Vertical Direction Timing Chart -- PAL LCX009 + (DCX501), LCX027 + (DCX501), DCX501 + (LCX009), DCX501 + (LCX027), DCX501 + (LCX005), DCX501 + (LCX024)
: Display start line : Display end line
(SYNC)
(BLK)
VD
VST
HD
HST1
HST2
VCK1, 4, (3)
VCK2, 3, (4)
FRP (Internal)
- 67 -
EVEN FIELD
FRP (Internal) 1F inversion
PCG
EN1
EN2
CLR
BLK
SBLK (Internal)
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. In LCX009 + (DCX501) and DCX501 + (LCX009) modes, the VCK3 and VCK4 polarities are inverted. (VCK(3) and VCK(4)) LCX009/027 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
CXA3017R
Vertical Direction Timing Chart -- NTSC-WIDE LCX005 + (DCX501), LCX024 + (DCX501)
: Display start line : Display end line
(SYNC)
(BLK)
VD
VST
HD
HST1
HST2
VCK2, 3 (A)
VCK1, 4 (A)
FRP (Internal) (A)
VCK2, 3 (B)
- 68 -
ODD FIELD
VCK1, 4 (B)
FRP (Internal) (B)
FRP (Internal) 1F inversion
PCG
EN1
EN2
CLR
BLK
SBLK (Internal)
CXA3017R
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX005 + (DCX501) mode: VCK(A) output LCX024 + (DCX501) mode: VCK(B) output LCX005/024 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
Vertical Direction Timing Chart -- NTSC-WIDE LCX005 + (DCX501), LCX024 + (DCX501)
: Display start line : Display end line
(SYNC)
(BLK)
VD
VST
HD
HST1
HST2
VCK2, 3 (A)
VCK1, 4 (A)
FRP (Internal) (A)
VCK2, 3 (B)
- 69 -
EVEN FIELD
VCK1, 4 (B)
FRP (Internal) (B)
FRP (Internal) 1F inversion
PCG
EN1
EN2
CLR
BLK
SBLK (Internal)
CXA3017R
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX005 + (DCX501) mode: VCK(A) output LCX024 + (DCX501) mode: VCK(B) output LCX005/024 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
Vertical Direction Timing Chart -- PAL-WIDE LCX005 + (DCX501), LCX024 + (DCX501)
: Display start line : Display end line
(SYNC)
(BLK)
VD
VST
HD
HST1
HST2
VCK2, 3 (A)
VCK1, 4 (A)
FRP (Internal) (A)
VCK2, 3 (B)
- 70 -
ODD FIELD
VCK1, 4 (B)
FRP (Internal) (B)
FRP (Internal) 1F inversion
PCG
EN1
EN2
CLR
BLK
SBLK (Internal)
CXA3017R
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX005 + (DCX501) mode: VCK(A) output LCX024 + (DCX501) mode: VCK(B) output LCX005/024 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
Vertical Direction Timing Chart -- PAL-WIDE LCX005 + (DCX501), LCX024 + (DCX501)
: Display start line : Display end line
(SYNC)
(BLK)
VD
VST
HD
HST1
HST2
VCK2, 3 (A)
VCK1, 4 (A)
FRP (Internal) (A)
VCK2, 3 (B)
VCK1, 4 (B)
- 71 -
EVEN FIELD
FRP (Internal) (B)
FRP (Internal) 1F inversion
PCG
EN1
EN2
CLR
BLK
SBLK (Internal)
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX005 + (DCX501) mode: VCK(A) output LCX024 + (DCX501) mode: VCK(B) output LCX005/024 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
CXA3017R
Vertical Direction Timing Chart -- NTSC-WIDE LCX009 + (DCX501), LCX027 + (DCX501), DCX501 + (LCX009), DCX501 + (LCX027), DCX501 + (LCX005)
: Display start line : Display end line
(SYNC)
(BLK)
VD
VST
HD
HST1
HST2
VCK1, 3, (4) (A)
VCK2, 4, (3) (A)
FRP (Internal) (A)
VCK1, 4 (B)
- 72 -
ODD FIELD
VCK2, 3 (B)
FRP (Internal) (B)
FRP (Internal) 1F inversion
PCG
EN1
EN2
CLR
BLK
SBLK (Internal)
CXA3017R
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX009 + (DCX501), DCX501 + (LCX009) and DCX501 + (LCX005) modes: VCK(A) output (In DCX501 + (LCX005) mode the polarity is inverted. (VCK(3)(A) and VCK(4)(A))) LCX027 + (DCX501) and DCX501 + (LCX027) modes: VCK(B) output LCX009/027 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
: Display start line : Display end line
Vertical Direction Timing Chart -- NTSC-WIDE LCX009 + (DCX501), LCX027 + (DCX501), DCX501 + (LCX009), DCX501 + (LCX027), DCX501 + (LCX005)
(SYNC)
(BLK)
VD
VST
HD
HST1
HST2
VCK1, 3, (4) (A)
VCK2, 4, (3) (A)
FRP (Internal) (A)
VCK1, 4 (B)
VCK2, 3 (B)
- 73 -
EVEN FIELD
FRP (Internal) (B)
FRP (Internal) 1F inversion
PCG
EN1
EN2
CLR
BLK
SBLK (Internal)
CXA3017R
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX009 + (DCX501), DCX501 + (LCX009) and DCX501 + (LCX005) modes: VCK(A) output (In DCX501 + (LCX005) mode the polarity is inverted. (VCK(3)(A) and VCK(4)(A))) LCX027 + (DCX501) and DCX501 + (LCX027) modes: VCK(B) output LCX009/027 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
Vertical Direction Timing Chart -- PAL-WIDE LCX009 + (DCX501), LCX027 + (DCX501), DCX501 + (LCX009), DCX501 + (LCX027), DCX501 + (LCX005)
: Display start line : Display end line
(SYNC)
(BLK)
VD
VST
HD
HST1
HST2
VCK1, 3, (4) (A)
VCK2, 4, (3) (A)
FRP (Internal) (A)
VCK1, 4 (B)
- 74 -
ODD FIELD
VCK2, 3 (B)
FRP (Internal) (B)
FRP (Internal) 1F inversion
PCG
EN1
EN2
CLR
BLK
SBLK (Internal)
CXA3017R
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX009 + (DCX501), DCX501 + (LCX009) and DCX501 + (LCX005) modes: VCK(A) output (In DCX501 + (LCX005) mode the polarity is inverted. (VCK(3)(A) and VCK(4)(A))) LCX027 + (DCX501) and DCX501 + (LCX027) modes: VCK(B) output LCX009/027 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
Vertical Direction Timing Chart -- PAL-WIDE LCX009 + (DCX501), LCX027 + (DCX501), DCX501 + (LCX009), DCX501 + (LCX027), DCX501 + (LCX005)
: Display start line : Display end line
(SYNC)
(BLK)
VD
VST
HD
HST1
HST2
VCK1, 3, (4) (A)
VCK2, 4, (3) (A)
FRP (Internal) (A)
VCK1, 4 (B)
- 75 -
EVEN FIELD
VCK2, 3 (B)
FRP (Internal) (B)
FRP (Internal) 1F inversion
PCG
EN1
EN2
CLR
BLK
SBLK (Internal)
CXA3017R
Note) The first (SYNC) and second (BLK) rows of the timing chart are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX009 + (DCX501), DCX501 + (LCX009) and DCX501 + (LCX005) modes: VCK(A) output (In DCX501 + (LCX005) mode the polarity is inverted. (VCK(3)(A) and VCK(4)(A))) LCX027 + (DCX501) and DCX501 + (LCX027) modes: VCK(B) output LCX009/027 drive pulses: HST2, EN2, CLR, VCK3, VCK4, VST and BLK DCX501 drive pulses: VCK1, VCK2, HST1, EN1, PCG and VST (HST1, EN1, PCG and VST output inverted pulses XHST1, XEN1, XPCG and XVST.)
CXA3017R
Application Circuit (NTSC/PAL, COMP input)
To LCD panel +12V 0.01 47 0.01 +3V 0.01 47 49 VCC1 1 16p 51 VXO IN 0.22 10k 52 APC 0.033 53 B-Y IN 54 R-Y IN 55 C OUT 1 56 V REG 57 C IN 0.1 58 RESET 59 Y IN 1 60 TEST2 0.01 61 SYNC IN COMP IN 0.33 62 VSEP TC 15k 2 63 F0 ADJ 64 GND1 48 47 46 45 44 43 42 41 40 39 38 37 36 0.47 0.47 0.47
VDD of connected LCD panel +15.5V
100k 0.47
100k
35
34
33
SIG.CENTER
FB G
G OUT
B OUT
GND3
DWN
VCC2
FB PSIG
R OUT
GND2
VCC3
RGT1
PSIG
50 VXO OUT
VDD2
DA OUT 32 VD 31 EN2 30 EN1 29 XEN1 28 VCK1 27 VCK2 26 VCK3 25 VCK4 24 VST 23 XVST 22 HD 21 PCG 20 XPCG 19 HCK1 18 HCK2 17 To LCD panel 16
FB R
FB B
EXT B
LOAD
TEST1
HST2
CLR
XHST1
15
EXT G
EXT R
TRAP
DATA
SCLK
VDD1
BLK
HST1
RPD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VSS
+3V From serial controller 10k 3 3.3 6800p To LCD panel 47 0.01
1 Used crystal: KINSEKI CX-5F Frequency deviation: within 30ppm, frequency temperature characteristics: within 30ppm, load capacity: 16pF NTSC: 3.579545MHz PAL: 4.433619MHz
2 Resistance value variation: 2%, temperature coefficient: 200ppm or less 3 Trap (TDK) NTSC: NLT4532-S3R6B PAL: NLT4532-S4R4
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 76 -
CXA3017R
Application Circuit (NTSC/PAL, Y/C input)
To LCD panel +12V 0.01 47 0.01 +3V 0.01 47 49 VCC1 1 16p 51 VXO IN 0.22 10k 52 APC 0.033 53 B-Y IN 54 R-Y IN 55 C OUT 1 56 V REG 57 C IN C IN 0.1 58 RESET 59 Y IN 1 60 TEST2 0.01 61 SYNC IN Y IN 62 VSEP TC 0.33 63 F0 ADJ 64 GND1 48 47 46 45 44 43 42 41 40 39 38 37 0.47 0.47 0.47
VDD of connected LCD panel +15.5V
100k 0.47
100k
36
35
34
33
SIG.CENTER
VCC2
G OUT
B OUT
GND3
FB PSIG
R OUT
GND2
VCC3
RGT1
PSIG
FB G
DWN
50 VXO OUT
VDD2
DA OUT 32 VD 31 EN2 30 EN1 29 XEN1 28 VCK1 27 VCK2 26 VCK3 25 VCK4 24 VST 23 XVST 22 HD 21 PCG 20 XPCG 19 HCK1 18 HCK2 17 To LCD panel 16
FB R
FB B
EXT R
EXT B
LOAD
TEST1
TRAP
DATA
HST2
CLR
XHST1
15
EXT G
SCLK
VDD1
RPD
BLK
HST1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VSS
+3V From serial controller 10k 3.3 6800p To LCD panel 47 0.01
1 Used crystal: KINSEKI CX-5F Frequency deviation: within 30ppm, frequency temperature characteristics: within 30ppm, load capacity: 16pF NTSC: 3.579545MHz PAL: 4.433619MHz
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 77 -
CXA3017R
Application Circuit (NTSC/PAL, Y/color difference input)
To LCD panel +12V 0.01 47 0.01 0.47 0.47 0.47
VDD of connected LCD panel +15.5V
100k 0.47
100k
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
R OUT
GND2
SIG.CENTER
RGT1
PSIG
FB G
FB B
G OUT
B OUT
GND3
DWN
VCC2
+3V 0.01 47 49 VCC1
FB PSIG
VCC3
50 VXO OUT 51 VXO IN 52 APC 0.1 B-Y IN 0.1 R-Y IN 54 R-Y IN 55 C OUT 1 56 V REG 57 C IN 0.1 58 RESET 59 Y IN 1 60 TEST2 0.01 61 SYNC IN COMP/Y IN 62 VSEP TC 0.33 63 F0 ADJ 64 GND1 53 B-Y IN
VDD2
DA OUT 32 VD 31 EN2 30 EN1 29 XEN1 28 VCK1 27 VCK2 26 VCK3 25 VCK4 24 VST 23 XVST 22 HD 21 PCG 20 XPCG 19 HCK1 18 HCK2 17 To LCD panel 16
FB R
CLR
XHST1
15
EXT G
EXT R
EXT B
LOAD
TRAP
DATA
TEST1
SCLK
HST2
VDD1
RPD
BLK
HST1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VSS
+3V From serial controller 10k 3.3 6800p To LCD panel 47 0.01
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 78 -
CXA3017R
Example of Representative Characteristics
HUE adjustment characteristics
45 30 10.00
COLOR adjustment characteristics
HUE adjustment angle [deg]
0.00 15 0 -15 -30 -30.00 -45 -60 -40.00
Gain [dB]
0 96 128 160 DAC value
-10.00
-20.00
32
64
192
224 256
0
32
64
96 128 160 DAC value
192
224 256
BRIGHT adjustment characteristics
8 7 14 13 10.00 5.00
CONTRAST adjustment characteristics
Non-inverted output black level [V]
Inverted output black level [V]
6 5 4 3 2 1 0 -1 -2 0 32 64 Non-inverted black Inverted black 96 128 160 DAC value 192
12 11 10 9 8 7 6 5
0.00
Output gain [dB]
-5.00 -10.00 -15.00 -20.00 -25.00
4 224 256
0
32
64
96 128 160 DAC value
192
224 256
SUB-BRIGHT adjustment characteristics
2 11
Black limiter control characteristics
Voltage change with respect to G output [V]
1.5 10 1 0.5 0 -0.5 -1 7 -1.5 -2 0 32 64 96 128 160 DAC value 192 224 256 6 0 32 64 96 128 160 DAC value 192 224 256
Limiter voltage [Vp-p]
9
8
- 79 -
CXA3017R
Color difference balance adjustment
5.00 B-Y output [dB] R-Y output [dB] 10
PSIG adjustment characteristics
3.00
8
Gain [dB]
1.00
Output amplitude [Vp-p]
0 96 128 160 192 DAC value
6
-1.00
4
-3.00
2
-5.00
32
64
224
256
0
0
32
64
96 128 160 192 DAC value
224
256
SUB-CONTRAST adjustment characteristics (1 = 2 = 0)
4.00 8 7
USER-BRIGHT adjustment characteristics
14 13
Non-inverted output black level [V]
3.00 2.00 1.00 0.00 -1.00 -2.00 -3.00 -4.00 0 32 64 96 128 160 192 DAC value 224 256
5 4 3 2 1 0 -1 -2 0 32 64 Non-inverted black Inverted black 96 128 160 192 DAC value 224
11 10 9 8 7 6 5
4 256
DA OUT output adjustment characteristics
3
2.5
Output voltage [V]
2
1.5
1
0.5
0
0
1
2
3 4 DAC value
5
6
7
- 80 -
Inverted output black level [V]
6
12
Gain [dB]
CXA3017R
Sharpness characteristics (1 = 2 = 0)
10.00 (COMP, PAL, 009AK/AKB) 5.00 0.00 -5.00 -10.00 -15.00 -20.00 -25.00 -30.00 0 2 4 6 8 Frequency [MHz] 10 12 -5.00 -10.00 -15.00 DAC = 0 DAC = 128 DAC = 255 15.00 10.00 20.00
Sharpness characteristics (1 = 2 = 0)
(Y/C, 009AK/AKB) DAC = 0 DAC = 128 DAC = 255
Gain [dB]
Gain [dB]
5.00 0.00
0
2
4 6 8 Frequency [MHz]
10
12
Sharpness characteristics (1 = 2 = 0)
15.00 (Y/C, 005BK/BKB) 10.00 DAC = 0 DAC = 128 DAC = 255 15.00 10.00 5.00 0.00
Sharpness characteristics (1 = 2 = 0)
(COMP, PAL, 005BK/BKB) DAC = 0 DAC = 128 DAC = 255
5.00
Gain [dB]
Gain [dB]
-5.00 -10.00 -15.00 -20.00
0.00
-5.00
-10.00 -25.00 -15.00 0 2 4 6 8 Frequency [MHz] 10 12 -30.00 0 2 4 6 8 Frequency [MHz] 10 12
Sharpness characteristics (1 = 2 = 0)
15.00 10.00 5.00 0.00 (COMP, NTSC, 005BK/BKB) 5.00 DAC = 0 DAC = 128 DAC = 255 0.00 -5.00 -10.00 -15.00 -20.00 -25.00 0 2 4 6 8 Frequency [MHz] 10 12 -30.00 0 10.00
Sharpness characteristics (1 = 2 = 0)
(COMP, NTSC, 009AK/AKB) DAC = 0 DAC = 128 DAC = 255
Gain [dB]
-5.00 -10.00 -15.00 -20.00 -25.00 -30.00
Gain [dB]
2
4 6 8 Frequency [MHz]
10
12
- 81 -
CXA3017R
Notes on Operation The CXA3017R contains digital circuits, so the set board pattern must be designed in consideration of undesired radiation, interference to analog circuits, etc. Care should also be taken for the following items when designing the pattern. * Make the IC power supply and GND patterns as plain as possible. In particular, GND and Vss should not be separated and should be connected to the same GND pattern as close to the pins as possible. * Connect the by-pass capacitors between the power supplies and GND as close to the pins as possible. * The trap connected to Pin 4 should be located as close to the pin as possible. Also, do not pass other signal lines close to this pin or the connected trap. * The wiring for the crystal and capacitor connected to Pins 50 and 51 should be as short as possible in order to prevent floating capacitance. Do not pass other signal lines close to these pins and wiring in order to prevent interference such as color unevenness. In addition, the APC pull-in characteristics vary significantly according to the characteristics of the used crystal and the wiring pattern, so be sure to thoroughly investigate these items before using the set. * The resistor connected to Pin 63 should be located as close to the pin as possible. Also, do not pass other signal lines close to this pin. The composite/Y signal and the external R-Y and B-Y signals are clamped at the inputs using the capacitors connected to the input pins, so these signals should be input at sufficiently low impedance. The C signal is received by the internal capacitor, so this signal should be input at low impedance after applying an appropriate external DC bias. The smoothing capacitor of the DC level control feedback circuit in the output block should have a leak current with a small absolute value and variance. A thorough study of the external buffer for PSIG output should be made before deciding on a circuit to ascertain that it sufficiently brings out the characteristics of the LCD panel. If this IC is used in connection with a circuit other than an LCD, it may cause that circuit to malfunction depending on the order in which power is supplied to the circuits. Thoroughly study the consequences of using this IC with other circuits before deciding on its use. Since this IC utilizes a C-MOS structure, it may latch up due to excessive noise or power surge greater than the maximum rating of the I/O pins, or due to interface with the power supply of another circuit, or due to the order in which power is supplied to circuits. Be sure to take measures against the possibility of latch up. Do not apply a voltage higher than VDD or lower than Vss to I/O pins. Do not use this IC under operating conditions other than those given. Absolute maximum rating values should not be exceeded even momentarily. Exceeding ratings may damage the device, leading to eventual breakdown. This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should be taken to prevent electrostatic discharge. - 82 -
CXA3017R
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 0.2 10.0 0.2 48 49 33 32 0.15 0.05 0.1
A 64 17
1 1.25 0.5
+ 0.08 0.18 - 0.03
16
1.7 MAX 0.1 M
0.1 0.1
0 to 10
DETAIL A
0.5 0.2
(0.5)
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42 ALLOY 0.3g LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
SONY CODE EIAJ CODE JEDEC CODE
LQFP-64P-L061 LQFP064-P-1010-AY
- 83 -

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Price & Availability of CXA3017R

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