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| Standard ICs Picture cell driver for STN (LCD driver) BU9716BK / BU9716BKV The BU9716BK and BU9716BKV are man-machine interface ICs designed for applications such as multi-media portable terminals. Specifically, these products are used as driver ICs for operating mode display LCD panels in portable terminals, household appliances, and other similar products. The number of display cells includes 32 segments and 3 commons, enabling drive of up to 96 cells. *Applications terminals, POS terminals, ECR Multi-media portable terminals, short wave radios, telephones, cameras, VCRs, movie projectors, car audio systems, and others *Features segment outputs and 3 common outputs 1) Up to 32 can be displayed, for a total of 96 segments. 2) 1 / 3 duty display. 3) Either 1 / 2 or 1 / 3 can be selected for power supply for LCD display. *Absolute maximum ratings (Ta = 25C, VSS = 0V) Parameter Power supply voltage Power dissipation Input voltage Operating temperature Storage temperature BU9716BK BU9716BKV Symbol VDD Pd VIN Topr Tstg Limits - 0.3 ~ + 7.0 5001 4002 - 0.3 ~ VDD + 0.3 - 40 ~ + 85 - 55 ~ + 125 Unit V mW V C C 1 Reduced by 5mW for each increase in Ta of 1C over 25C . 2 Reduced by 4mW for each increase in Ta of 1C over 25C . *Recommended operating conditions (Ta = 25C, VSS = 0V) Parameter Power supply voltage Input voltage Symbol VDD VDD1 VDD2 Min. 4.5 0 0 Typ. -- 2 / 3VDD 1 / 3VDD Max. 5.5 VDD VDD Unit V V V 1 Standard ICs BU9716BK / BU9716BKV *Block diagram VDD1 VDD2 LCD Power RES CS DI CK CTRL Logic DATA Latch OSC OSC Common Driver Segment Driver S1 S2 S3 S4 S30 S31 S24 S23 COM1 COM2 COM1 *Pin assignments COM1 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 33 COM2 COM3 RES VDD VDD1 VDD2 VSS OSC CS CK DI 44 1 11 12 34 23 22 S22 S21 S20 S19 S18 COM2 COM3 RES VDD VDD1 VDD2 VSS OSC CS CK DI N.C. 48 37 COM3 36 25 24 N.C. S22 S21 S20 S19 S18 BU9716BK S17 S16 S15 S14 S13 S12 BU9716BKV N.C. S32 S31 S30 S29 S28 S27 S26 S25 S32 S17 S16 S15 S14 S13 13 S12 1 12 S5 S5 2 N.C. S10 S11 S10 S11 S1 S2 S3 S4 S6 S7 S8 S9 S1 S2 S3 S4 S6 S7 S8 S9 Standard ICs BU9716BK / BU9716BKV *Pin descriptions (BU9716BK) Pin No. Pin name I / O 1 - 32 33 34 35 36 41 42 43 44 38 39 S1 - S32 COM1 COM2 COM3 RES OSC CS CK DI VDD1 VDD2 O Function Output pin for segment data. Outputs consistent LCD drive voltage to the data corresponding to COM1 to COM3. Common driver output. The frame frequency is fC = (fOSC / 384) Hz Processing when not used OPEN O OPEN I -- I I I -- -- Reset input. At RES = L, internal data (including control data) is reset. Oscillator pin (for common and segment alternating waveforms) Chip select input. At CS = H, data can be transferred. Synchronous clock input for serial data transfer Serial data input Internal reference voltage for LCD drive. In 1 / 2 bias mode, this is connected to VDD2. Internal reference voltage for LCD drive. In 1 / 2 bias mode, this is connected to VDD1. VDD VSS VSS VSS VSS OPEN OPEN *Electrical characteristics (unless otherwise noted, Ta = 25C, VDD = 4.5V to 5.5V, VSS = 0V) Parameter Input high level voltage Input low level voltage Input high level current Input low level current Output high level voltage Symbol VIH VIL IIH IIL VSOH VCOH VSOL VCOL VCM1 VSM1 Intermediate output voltage VCM2 VSM2 VCM3 Power supply current IQ IDD Min. 0.8VDD 0 0 0 -- -- -- -- -- -- -- -- -- -- -- Typ. -- -- -- -- VDD - 1.0 VDD - 1.0 1.0 1.0 1 / 2VDD 1.0 2 / 3VDD 1.0 2 / 3VDD 1.0 1 / 3VDD 1.0 1 / 3VDD 1.0 30 100 Max. VDD 0.2VDD 6.0 6.0 -- -- -- -- -- -- -- -- -- 70 300 Unit V V A A V V V V V V V V V A A Conditions CS, CK, DI, RES CS, CK, DI, RES CS, CK, DI, RES, VI = VDD CS, CK, DI, RES, VI = VSS S1 ~ S32, IO = - 20A COM1 ~ COM3, IO = - 100A S1 ~ S32, IO = - 20A COM1 ~ COM3, IO = - 100A COM1 ~ COM3, 1 / 2Bias S1 ~ S32, 1 / 3Bias COM1 ~ COM3, 1 / 3Bias S1 ~ S32, 1 / 3Bias COM1 ~ COM3, 1 / 3Bias Low-power mode fOSC = 38kHz Output low level voltage 3 Standard ICs BU9716BK / BU9716BKV *Electrical characteristics otherwise noted, Ta = 25C, VDD = 4.5V to 5.5V, VSS = 0V) AC characteristics (unless Parameter Recommended external resistance Recommended external capacitance Guaranteed oscillation range Data setup time Data hold time CS setup time CS hold time CK "H" pulse width CK "L" pulse width Rise time Fall time Symbol R C fOSC tDS tDH tCS tCH tCKH tCKL tr tf Pin OSC OSC OSC CK, DI CK, DI CS, CK CS, CK CK CK CS, CK, DI CS, CK, DI Min. -- -- 19 100 100 100 100 100 100 -- -- Typ. 47 1000 38 -- -- -- -- -- -- -- -- Max. -- -- 76 -- -- -- -- -- -- 300 300 Unit k pF kHz ns ns ns ns ns ns ns ns AC timing waveform (1) When CK is stopped at "L" 0.8VDD CS tCS tCKH tCKL tCH 0.2VDD 0.8VDD CK tDS 0.5VDD tDH 0.5VDD 0.8VDD 0.2VDD tr tf DI (2) When CK is stopped at "H" 0.8VDD CS tCS tCKH tCKL tCH 0.2VDD CK 0.2VDD tDS 0.5VDD tDH 0.5VDD 0.8VDD 0.2VDD tr tf DI 4 Standard ICs BU9716BK / BU9716BKV IDD, IQ VDD SW4 CS, CK DI, RES S1 ~ S32 1 SW3 VDD1 2 0.047F VDD2 OSC VSS 1000pF, 47k COM1 ~ COM3 1 2 SW2 SW1 1 2 3 VCM1, VCM2, VCM3 VSM1, VSM2 IO V VSOH, VSOL VCOH, VCOL V V1 A *Measurement circuit P. G. A IIH, LH V2 1 2 0.047F GND GND P. G.: Control signal generator for programmable signal generator, etc. Fig.1 Measurement conditions Parameter Input high level voltage Input low level voltage Input high level current Input low level current Output high level voltage Symbol VIH VIL IIH IIL VSOH VCOH VSOL VCOL VCM1 VSM1 Intermediate output voltage VCM2 VSM2 VCM3 Current dissipation AC characteristics IQ IDD 2 2 1 SW1 2 SW2 -- SW3 -- SW4 1 Conditions Set as P.G. input voltage; mode switching test V2 = VDD V2 = VSS Pattern 1, IO = - 20A Pattern 1, IO = - 100A Pattern 2, IO = 20A Pattern 2, IO = 100A Pattern 3 Pattern 4 1 1 Pattern 4 Pattern 5 Pattern 5 -- -- 1 1 Pattern 6 Test after power on Used as P.G. input condition 2 -- 1 2 1 2 2 1 2 1 2 -- -- -- 2 3 1 1 Output low level voltage 3 2 2 1 Measurement pattern CS DI CK CS DI CK CS DI CK Pattern 1 Fig.2 CS DI CK CS DI CK Pattern 2 Fig.3 CS DI CK Pattern 3 Fig.4 Pattern 4 Fig.5 Pattern 5 Fig.6 Pattern 6 Fig.7 5 Standard ICs operation *Circuitcharts Timing (1) When CK is stopped at "L" CS CK DI D1 D2 D3 D96 0 0 0 0 0 BU9716BK / BU9716BKV BM LC OE Display data Control code Fig.8 When CS is HIGH, data can be transferred. Data is sent to the shift register at the rising edge of CK. After all of the DI data has been transferred, CS should be (2) When CK is stopped at "H" CS CK DI D1 D2 D3 D96 0 0 set to LOW. The voltage corresponding to the display data transferred at the falling edge of CS is output. 0 0 0 BM LC OE Display data Control code Fig.9 Control code table OE 0 1 Output enable control Normal operation All display data is 0; no display (internal oscillation circuit is operating) BM 0 1 Bias mode control 1 / 3 bias 1 / 2 bias LC 0 1 Low power mode control Normal operation Low power mode = The internal oscillation circuit stops oscillating, and segment and common output = 0 6 Standard ICs Correspondence between display data input and segments Segment S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 COM3 D1 D4 D7 D10 D13 D16 D19 D22 D25 D28 D31 D34 D37 D40 D43 D46 COM2 D2 D5 D8 D11 D14 D17 D20 D23 D26 D29 D32 D35 D38 D41 D44 D47 COM1 D3 D6 D9 D12 D15 D18 D21 D24 D27 D30 D33 D36 D39 D42 D45 D48 Segment S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 BU9716BK / BU9716BKV COM3 D49 D52 D55 D58 D61 D64 D67 D70 D73 D76 D79 D82 D85 D88 D91 D94 COM2 D50 D53 D56 D59 D62 D65 D68 D71 D74 D77 D80 D83 D86 D89 D92 D95 COM1 D51 D54 D57 D60 D63 D66 D69 D72 D75 D78 D81 D84 D87 D90 D93 D96 7 Standard ICs BU9716BK / BU9716BKV *Timing chart COM 1 fO = fOSC / 384 fO = fOSC / 384 VDD VDD1, VDD2 VSS VDD COM 2 VDD1, VDD2 VSS VDD VDD1 VDD2 VSS VDD VDD1 VDD2 VSS VDD COM 3 VDD1, VDD2 VSS VDD VDD1, VDD2 VSS VDD VDD1 VDD2 VSS VDD VDD1 VDD2 VSS LCD driver output when all LCD segments for COM1, 2, and 3 are out LCD driver output when only the LCD segment for COM1 is lit up VDD VDD1, VDD2 VSS VDD VDD1 VDD2 VSS LCD driver output when only the LCD segment for COM2 is lit up VDD VDD1, VDD2 VSS VDD VDD1, VDD2 VSS VDD VDD1, VDD2 VSS VDD VDD1 VDD2 VSS VDD VDD1 VDD2 VSS VDD VDD1 VDD2 VSS LCD driver output when the LCD segments for COM1 and 2 are lit up LCD driver output when only the LCD segment for COM3 is lit up LCD driver output when the LCD segments for COM1 and 3 are lit up VDD VDD1, VDD2 VSS VDD VDD1, VDD2 VSS VDD VDD1 VDD2 VSS VDD VDD1 VDD2 VSS LCD driver output when the LCD segments for COM2 and 3 are lit up LCD driver output when all the LCD segments for COM1, 2 and 3 are lit up VDD VDD1, VDD2 VSS VDD VDD1 VDD2 VSS 1 / 2 bias 1 / 3 duty waveform 1 / 3 bias 1 / 3 duty waveform Fig.10 8 Standard ICs BU9716BK / BU9716BKV *Application example 1 47k 1000pF GND OSC VDD VDD RES VSS COM1 COM2 COM3 S1 VDD1 VDD2 Controller S2 BU9716BK / BKV 96 S3 S4 LCD S5 Segment C 0.047F CS CK DI S6 S32 1 / 2 bias mode Fig.11 47k 1000pF GND OSC VDD VDD RES VSS COM1 COM2 COM3 S1 VDD1 C Controller 0.047 F VDD2 S2 BU9716BK / BKV S3 S4 96 Segment LCD S5 C 0.047F CS CK DI S32 S6 1 / 3 bias mode Fig.12 9 Standard ICs BU9716BK / BU9716BKV *Application example 2 47k 1000pF GND OSC VDD VDD RES COM1 COM2 COM3 S1 VDD1 VDD2 Controller R S2 S3 96 Segment LCD S5 C 0.047F CS CK DI S32 S6 1 R VSS BU9716BK / BKV S4 1 / 2 bias mode Fig.13 47k 1000pF GND OSC VDD VDD RES COM1 COM2 COM3 S1 S2 VDD2 Controller R C 0.047F CS CK DI S32 S3 96 Segment LCD S5 S6 2 R VSS VDD1 R BU9716BK / BKV S4 1 / 3 bias mode Fig. 14 The resistance values and capacitance for1 and 2 should be set to match the LCD panel, and should be checked using test operation. 10 Standard ICs Make sure of the following when resetting when the power is on. BU9716BK / BU9716BKV * When using the external reset terminal, make RST = "L" at 1 ms or more with VDD at 1.8V or more. * When not using the external reset terminal, VDD has to satisfy the following conditions. Instruction receipt possible VDD 1.8V tWAIT 1ms VDD < 0.3V 0 < tON < 10ms *External dimensions (Units: mm) BU9716BK BU9716BKV 14.0 0.3 10.0 0.2 33 23 14.0 0.3 10.0 0.2 34 22 9.0 0.3 7.0 0.2 37 48 9.0 0.3 7.0 0.2 36 25 24 13 1 1.425 0.1 0.10 12 0.5 0.125 0.1 0.10 44 1 11 12 2.15 0.1 1.2 0.15 0.1 0.05 0.8 0.35 0.1 0.5 0.2 0.1 0.15 QFP44 VQFP48 11 |
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