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APPLICATION NOTE A V A I LABLE
AN76 * AN78 * AN81 * AN87
64K/32K/16K
X24F064/032/016
8K/4K/2K x 8 Bit
SerialFlashTM Memory with Block LockTM Protection
FEATURES DESCRIPTION The X24F064/032/016 is a CMOS SerialFlash Memory Family, internally organized 8K/4K/2K x 8. The family features a serial interface and software protocol allowing operation on a simple two wire bus. Device select inputs (S0, S1, S2) allow up to eight devices to share a common two wire bus. A Program Protect Register accessed at the highest address location, provides three new programming protection features: Software Programming Protection, Block Lock Protection, and Hardware Programming Protection. The Software Programming Protection feature prevents any nonvolatile writes to the device until the WEL bit in the program protect register is set. The Block LockTM Protection feature allows the user to individually protect four blocks of the array by programming two bits in the programming protect register. The Programmable Hardware Program Protect feature allows the user to install each device with PP tied to VCC, program the entire memory array in place, and then enable the hardware programming protection by programming a PPEN bit in the program protect register. After this, selected blocks of the array, including the program protect register itself, are permanently protected from being programmed.
* *
* * * * * * * * *
1.8V to 3.6V or 5V "Univolt" Read and Program Power Supply Versions Low Power CMOS --Active Read Current Less Than 1mA --Active Program Current Less Than 3mA --Standby Current Less Than 1A Internally Organized 8K/4K/2K x 8 New Programmable Block Lock Protection --Software Write Protection --Programmable hardware Write Protect Block Lock (0, 1/4, 1/2, or all of the Flash Memory array) 2 Wire Serial Interface Bidirectional Data Transfer Protocol 32 Byte Sector Programming Self Timed Program Cycle --Typical Programming Time of 5ms Per Sector High Reliability --Endurance: 100,000 cycles per byte --Data Retention: 100 Years Available Packages --8-Lead PDIP --8-Lead SOIC (JEDEC) --14-Lead TSSOP (X24F032/016) --20-Lead TSSOP (X24F064)
FUNCTIONAL DIAGRAM
DATA REGISTER SDA SECTOR DECODE LOGIC SCL X DECODE LOGIC 32 8
S0/S0 S1/S1 S2/S2
COMMAND DECODE AND CONTROL LOGIC
SECTORED MEMORY ARRAY
PROGRAM PROTECT REGISTER
PP
SerialFlashTM Memory and Block LockTM Protection are trademarks of Xicor, Inc. (c)Xicor, 1995, 1996 Patents Pending 6686-3.8 8/29/96 T3/C0/D0 SH
PROGRAMMING CONTROL LOGIC
HIGH VOLTAGE CONTROL
6686 ILL F01.5
1
Characteristics subject to change without notice
X24F064/032/016
Xicor SerialFlash Memories are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the pullup resistor selection graph at the end of this data sheet. Device Select (S0, S0, S1, S1, S2, S2) The device select inputs are used to set the device select bits of the 8-bit slave address. This allows multiple devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven with CMOS levels (driven to VCC or VSS). Program Protect (PP) The program protect input controls the hardware program protect feature. When held LOW, hardware program protection is disabled and the X24F064/ 032/016 can be programmed normally. When this input is held HIGH, and the PPEN bit in the program protect register is set HIGH, program protection is enabled, and nonvolatile writes are disabled to the selected blocks as well as the program protect register itself. PIN NAMES Symbol
S0, S0, S1, S1, S2, S2 SDA SCL PP VSS VCC NC
20-LEAD TSSOP NC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 NC VCC PP NC NC NC SCL SDA NC NC S0 S1 S2 VSS 1 2 3 4
PIN CONFIGURATION
14-LEAD TSSOP S0 S1 NC VCC PP SCL SDA NC NC S2 VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC PP NC NC NC SCL SDA
X24F016
8-LEAD DIP & SOIC 8 7 6 5
14-LEAD TSSOP S0 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC PP NC NC NC SCL SDA
X24F032
8-LEAD DIP & SOIC S0 S1 S2 VSS 1 2 3 4 8 7 6 5 VCC PP SCL SDA
S1 NC NC NC S2 VSS
X24F064
8-LEAD DIP & SOIC NC S1 S2 VSS 1 2 3 4 8 7 6 5 VCC PP SCL SDA
NC S1 NC NC NC S2 VSS NC NC
6686 ILL F02.4
Description
Device Select Inputs Serial Data Serial Clock Program Protect Ground Supply Voltage No Connect
6686 FRM T01.1
2
X24F064/032/016
DEVICE OPERATION The X24F064/032/016 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24F064/032/016 will be considered a slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24F064/032/016 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA DATA STABLE DATA CHANGE
6686 ILL F04
Notes: (5) Typical values are for TA = 25C and nominal supply voltage (2.7V) (6) tPR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device requires to perform the internal program operation.
Figure 2. Definition of Start and Stop
SCL
SDA START BIT STOP BIT
6686 ILL F05
3
X24F064/032/016
Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3. The X24F064/032/016 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24F064/032/016 will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the X24F064/032/016 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24F064/032/016 will continue to transmit data. If an acknowledge is not detected, the device will terminate further data transmissions. The master must then issue a stop condition to return the X24F064/032/016 to the standby power mode and place the device into a known state.
Figure 3. Acknowledge Response From Receiver
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
6686 ILL F06
4
X24F064/032/016
DEVICE ADDRESSING Following a start condition the master must output the address of the slave it is accessing (see Figure 4). The next two bits are the device select bits. A system could have up to eight X24F032/016's on the bus or up to four 24F064's on the bus. The device addresses are defined by the state of the S0, S1, and S2 inputs. Note some of the slave addresses must be the inverse of the corresponding input pin. Figure 4. Slave Address
X24F064 DEVICE SELECT S2 S1 A12 HIGH ORDER SECTOR ADDRESS A11 A10
Also included in the slave address is an extension of the array's address which is concatenated with the eight bits of address in the sector address field, providing direct access to the entire SerialFlash Memory array. The last bit of the slave address defines the operation to be performed. When set HIGH a read operation is selected, when set LOW a program operation is selected. Following the start condition, the X24F064/032/016 monitors the SDA bus comparing the slave address being transmitted with its slave address device type identifier. Upon a correct comparison of the device select inputs, the X24F064/032/016 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24F064/032/016 will execute a read or program operation. PROGRAMMING OPERATIONS
A9
A8
R/W
X24F032 DEVICE SELECT A11 HIGH ORDER SECTOR ADDRESS S0 A10
S2
S1
A9
A8
R/W
DEVICE TYPE IDENTIFIER
X24F016 DEVICE SELECT HIGH ORDER SECTOR ADDRESS
1
S2
S1
S0
A10
A9
A8
R/W
6686 ILL F07.4
The X24F064/032/016 offers a 32-byte sector programming operation. For a program operation, the X24F064/032/016 requires a second address field. This field contains the address of the first byte in the sector. Upon receipt of the address, comprised of eight bits, the X24F064/032/016 responds with an acknowledge and awaits the next eight bits of data, again responding with an acknowledge. The master then transmits 31 more bytes. After the receipt of each byte, the X24F064/032/016 will respond with an acknowledge.
Figure 5. Sector Programming
S T A R T S A C K A C K A C K A C K A C K
6686 ILL F10.3
BUS ACTIVITY: MASTER SDA LINE BUS ACTIVITY: X24F016/032/064
SLAVE ADDRESS
SECTOR ADDRESS
DATA n
DATA n+1
DATA n+31
S T O P P
5
X24F064/032/016
Flow 1. ACK Polling Sequence After the receipt of each byte, the five low order address bits are internally incremented by one. The high order bits of the sector address remain constant. If the master should transmit more or less than 32 bytes prior to generating the stop condition, the contents of the sector cannot be guaranteed. All inputs are disabled until completion of the internal program cycle. Refer to Figure 5 for the address, acknowledge and data transfer sequence. Acknowledge Polling
ISSUE SLAVE ADDRESS AND R/W = 0
PROGRAM OPERATION COMPLETED ENTER ACK POLLING
ISSUE START
ISSUE STOP
ACK RETURNED? YES NEXT OPERATION A WRITE? YES ISSUE SECTOR ADDRESS
NO
The Max Write Cycle Time can be significantly reduced using Acknowledge Polling. To initiate Acknowledge Polling, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle, then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to Flow 1. READ OPERATIONS Read operations are initiated in the same manner as program operations with the exception that the R/W bit of the slave address is set HIGH. There are three basic read operations: current address read, random read and sequential read.
NO
ISSUE STOP
PROCEED
PROCEED
It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition.
6686 ILL F09.1
6
X24F064/032/016
Current Address Read Internally, the X24F064/032/016 contains an address counter that maintains the address of the last byte read, incremented by one byte. Therefore, if the last read was from address n, the next read operation accesses data from address n + 1. Upon receipt of the slave address with the R/W set HIGH, the X24F064/032/016 issues an acknowledge and transmits the eight-bit word. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 6 for the sequence of address, acknowledge and data transfer. Random Read Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set HIGH, the master must first perform a "dummy" write operation. The master issues the start condition, and the slave address with the R/W bit set LOW, followed by the byte address it is to read. After the byte address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set HIGH. This will be followed by an acknowledge from the X24F064/032/016 and then by the eight-bit byte. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 7 for the address, acknowledge and data transfer sequence.
Figure 6. Current Address Read
S T A R T S A C K DATA
6686 ILL F11.1
BUS ACTIVITY: MASTER SDA LINE BUS ACTIVITY: X24F016/032/064
SLAVE ADDRESS
S T O P P
Figure 7. Random Read
BUS ACTIVITY: MASTER SDA LINE BUS ACTIVITY: X24F016/032/064
S T A R T S
SLAVE ADDRESS
BYTE ADDRESS n
S T A R T S
SLAVE ADDRESS
S T O P P A C K DATA n
6686 ILL F12.3
A C K
A C K
7
X24F064/032/016
Sequential Read Sequential reads can be initiated as either a current address read or random access read. The first byte is transmitted as with the other modes, however, the master now responds with an acknowledge, indicating it requires additional data. The X24F064/032/016 continues to output data for each acknowledge received. The read operation is terminated by the master; by not responding with an acknowledge and then issuing a stop condition. Figure 8. Sequential Read The data output is sequential, with the data from address n followed by the data from n + 1. The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space, the counter "rolls over" to 0 and the X24F064/032/016 continues to output data for each acknowledge received. Refer to Figure 8 for the address, acknowledge and data transfer sequence.
BUS ACTIVITY: MASTER SDA LINE BUS ACTIVITY: X24F016/032/064
SLAVE ADDRESS
A C K
A C K
A C K
S T O P P
A C K
DATA n
DATA n+1
DATA n+2
DATA n+x
6686 ILL F13.1
Figure 9. Typical System Configuration
VCC PULL-UP RESISTORS SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER
6686 ILL F14
8
X24F064/032/016
PROGRAM PROTECT REGISTER The Program Protect Register (PPR) is accessed at the highest address of each device: X24F064 = 1FFF X24F032 = 0FFF X24F016 = 07FF Figure 10. Program Protect Register other address than the highest address location is performed, the contents of the byte in the array at the highest address location is read out instead of the Program Protect Register. WEL and RWEL are volatile latches that power-up in the LOW (disabled) state. A write to any address other than the highest address location, where the Program Protect Register is located, will be ignored (no ACK) until the WEL bit is set HIGH. The WEL bit is set by writing 0000001x to the highest address location. Once set, WEL remains HIGH until either reset (by writing 00000000 to the highest address location) or until the part powers-up again. The RWEL bit controls writes to the Block Lock bits. RWEL is set by first setting WEL = 1 and then writing 0000011x to the highest address location. RWEL must be set in order to change the Block Lock bits (BL0 and BL1) or the PPEN bit. RWEL is reset when the Block Lock or PPEN bits are changed, or when the part powers-up again. Programming the BL or PPEN Bits A three step sequence is required to change the nonvolatile Block Lock or Program Protect Enable: 1) Set WEL = 1 (write 00000010 to the highest address location, volatile write cycle) (Start) 2) Set RWEL = 1 (write 00000110 to the highest address location, volatile write cycle) (Start) 3) Set BL1, BL0, and/or PPEN bits (Write w00yz010 to the highest address location) w = PPEN, y = BL1, Z = BL0, (Stop) Step 3 is a nonvolatile program cycle, requiring 10ms to complete. RWEL is reset (0) by this program cycle, requiring another program cycle to set RWEL again before the Block Lock bits can be changed. RWEL must be 0 in step 3; if w00yz110 is written to the highest address location, RWEL is set but PPEN, BL1 and BL0 are not changed (the device remains at step 2).
7 PPEN
6 0
5 0
4 BL1
3 BL0
2 RWEL
1 WEL
0 0
6686 ILL F15
PPR.1 = WEL - Write Enable Latch (Volatile) 0 = Write enable latch reset, programming disabled 1 = Write enable latch set, programming enabled If WEL = 0 then "no ACK" after first byte of input data. PPR.2 = RWEL - Register Write Enable Latch (Volatile) 0 = Register write enable latch reset, programming disabled 1 = Register write enable latch set, programming enabled PPR.3, PPR.4 = BL0, BL1 - Block Lock Bits (Nonvolatile) (See Block Lock Bits section for definition) PPR.7 = PPEN - Programming Protect Enable Bit (Nonvolatile) (See Programmable Hardware Program Protect section for definition) Writing to the Program Protect Register The Program Protect Register is written by performing a write of one byte directly to the highest address location. During normal Sector Programming, the byte in the array at the highest address will be written instead of the Program Protect Register (assuming programming is not disabled by the Block Lock register). The state of the Program Protect Register can be read by performing a random read at the highest address location at any time. If a sequential read starting at any
9
X24F064/032/016
Block Lock Bits The Block Lock Bits BL0 and BL1 determine which blocks of the memory are write-protected: Table 1. Block Lock Bits BL1
0 0 1 1
BL0
0 1 0 1 None
Array Locked
Upper 1/4 Upper 1/2 Full Array (WPR not included)
6686 FRM T02
Programmable Hardware Program Protect The Program Protect (PP) pin and the Program Protect Enable (PPEN) bit in the Program Protect Register control the programmable hardware program protect feature. Hardware program protection is enabled when the PP pin and the PPEN bit are both HIGH, and disabled when either the PP pin is LOW or the PPEN bit is LOW. When the chip is hardware programprotected, nonvolatile programming is disabled, including the Program Protect Register, the BL bits and the PPEN bit itself, as well as to Block Locked sections in the memory array. Only the sections of the memory array that are not Block Locked can be written. Note that since the PPEN bit is program-protected, it cannot be changed back to a LOW state, and program protection is disabled as long as the PP pin is held HIGH. Table 2 defines the program protection status for each state of PPEN and PP.
Table 2. Program Protect Status Table Memory Array (Not Block Locked)
Programmable Programmable Programmable
PP
0 X 1
PPEN
X 0 1
Memory Array (Block Locked)
Locked Locked Locked
BL Bits
Programmable Programmable Locked
PPEN Bit
Programmable Programmable Locked
6686 FRM T03
10
X24F064/032/016
ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias X24F064/032/016 ...................... -65C to +135C Storage Temperature........................ -65C to +150C Voltage on any Pin with Respect to VSS.................................... -1V to +7V D.C. Output Current..............................................5mA Lead Temperature (Soldering, 10 Seconds)...... 300C *COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temperature
Commercial Extended Industrial
Min.
0C -20C -40C
Max.
+70C +85C +85C
6686 FRM T04.2
Supply Voltage X24F064/032/016 X24F064/032/016-5
Limits
1.8V to 3.6V 4.5V to 5.5V
6686 FRM T05.2
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol
ICC1 ICC2 ISB1(1)
Parameter
VCC Supply Current (Read) VCC Supply Current (Write) VCC Standby Current
Min.
Max.
1 3 1
Units
mA mA A
Test Conditions
SCL = VCC X 0.1/VCC X 0.9 Levels @ 100KHz, SDA = Open, All Other Inputs = VSS or VCC - 0.3V SCL = SDA = VCC, All Other Inputs = VSS or VCC - 0.3V, VCC = 3.6V
ISB2(1)
VCC Standby Current
10
A
SCL = SDA = VCC, All Other Inputs = VSS or VCC - 0.3V, VCC = 5V 10%
ILI ILO VlL(2) VIH(2) VOL
Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage -1 VCC x 0.7
10 10 VCC x 0.3 VCC + 0.5 0.4
A A V V V
VIN = VSS to VCC VOUT = VSS to VCC
IOL = 3mA
6686 FRM T06.4
CAPACITANCE TA = +25C, f = 1MHz, VCC = 2.7V Symbol
CI/O(3) CIN(3)
Parameter
Input/Output Capacitance (SDA) Input Capacitance (S1, S2, SCL)
Max.
8 6
Units
pF pF
Test Conditions
VI/O = 0V VIN = 0V
6686 FRM T07
Notes: (1) Must perform a stop command prior to measurement. (2) VIL min. and VIH max. are for reference only and are not 100% tested. (3) This parameter is periodically sampled and not 100% tested.
11
X24F064/032/016
A.C. CONDITIONS OF TEST
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels VCC x 0.1 to VCC x 0.9 10ns VCC X 0.5
6686 FRM T08
EQUIVALENT A.C. LOAD CIRCUIT
2.7V 1533 OUTPUT 100pF OUTPUT 100pF 5V 1533
6686 ILL F16.1
A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read & Write Cycle Limits Symbol
fSCL TI tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH
Parameter
SCL Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL LOW to SDA Data Out Valid Time the Bus Must Be Free Before a New Transmission Can Start Start Condition Hold Time Clock LOW Period Clock HIGH Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time
Min.
0
Max.
100 100
Units
KHz ns s s s s s s s ns s ns s ns
6686 FRM T09.1
0.3 4.7 4 4.7 4 4.7 0 250
3.5
1 300 4.7 300
POWER-UP TIMING(4) Symbol
tPUR tPUW
Parameter
Power-up to Read Operation Power-up to Write Operation
Max.
1 5
Units
ms ms
6686 FRM T10
Notes: (4) tPUR and tPUW are the delays required from the time V CC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested.
12
X24F064/032/016
Bus Timing
tF SCL tSU:STA SDA IN tAA SDA OUT
6686 ILL F17
tHIGH
tLOW
tR
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tDH
tBUF
Program Cycle Limits Symbol
tPR(6)
Parameter
Program Cycle Time
Min.
Typ.(5)
5
Max.
10
Units
ms
6686 FRM T11.1
The program cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the program cycle, the Bus Timing
SCL
X24F064/032/016 bus interface circuits are disabled, SDA is allowed to remain HIGH, and the device does not respond to its slave address.
SDA
8th BIT WORD n
ACK tWR STOP CONDITION START CONDITION
6686 ILL F18
Notes: (5) Typical values are for TA = 25C and nominal supply voltage (2.7V). (6) tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal program operation.
Guidelines for Calculating Typical Values of Bus Pull-Up Resistors
120 RESISTANCE (K) 100 80 60 40 20 0 0 20 40 60 80 100 120
6686 ILL F19.1
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
RMIN =
VCC MAX =1.2K IOL MIN tR CBUS
RMAX =
MAX. RESISTANCE
MIN. RESISTANCE
BUS CAPACITANCE (pF)
13
X24F064/032/016
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10) PIN 1 INDEX PIN 1 0.300 (7.62) REF. 0.060 (1.52) 0.020 (0.51)
HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL SEATING PLANE 0.150 (3.81) 0.125 (3.18)
0.145 (3.68) 0.128 (3.25)
0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41)
0.110 (2.79) 0.090 (2.29)
0.015 (0.38) MAX.
0.325 (8.25) 0.300 (7.62)
TYP. 0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F01
14
X24F064/032/016
PACKAGING INFORMATION 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00) PIN 1 INDEX
0.228 (5.80) 0.244 (6.20)
PIN 1
0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.19) 0.010 (0.25)
0.010 (0.25) X 45 0.020 (0.50)
0.050" TYPICAL
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" TYPICAL
FOOTPRINT
0.030" TYPICAL 8 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F22.1
15
X24F064/032/016
PACKAGING INFORMATION 14-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F32
16
X24F064/032/016
PACKAGING INFORMATION
20-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.252 (6.4) .300 (6.6)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F45
17
X24F064/032/016
ORDERING INFORMATION
X24FXXX Device X24F064 X24F032 X24F016
X
X
-X VCC Range Blank = 1.8V to 3.6V 5 = 4.5V to 5.5V Temperature Range Blank = Commercial = 0C to +70C E = Extended = -20C to +85C I = Industrial = -40C to +85C Package X24F064 P = 8-Lead Plastic DIP S = 8-Lead SOIC (JEDEC) V = 20-Lead TSSOP X24F032 X24F016 P = 8-Lead Plastic DIP S = 8-Lead SOIC (JEDEC) V = 14-Lead TSSOP
Part Mark Convention
X24FXXX
X X
P = 8-Lead Plastic DIP Blank = 8-Lead SOIC (JEDEC) V = 14/20-Lead TSSOP Blank = 1.8V to 3.6V, 0C to +70C E = 1.8V to 3.6V, -20C to +85C 5 = 4.5V to 5.5V, 0C to +70C I5 = 4.5V to 5.5V, -40C to +85C
X24F064 X24F032 X24F016
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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