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HM658512A Series
4 M PSRAM (512-kword x 8-bit) 2 k Refresh
ADE-203-218C(Z) Rev. 3.0 Nov. 1997 Description
The Hitachi HM658512A is a CMOS pseudo static RAM organized 512-kword x 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.8 m Hi-CMOS process technology. It offers low power data retention by self refresh mode. It also offers easy non multiplexed address interface and easy refresh functions. HM658512A is suitable for handy systems which work with battery back-up systems. The device is packaged in a small 525-mil SOP (460-mil body SOP) or a 8 x 20 mm TSOP with thickness of 1.2 mm, or a 600-mil plastic DIP. High density custom cards made of Tape Carrier Packages are also available.
Features
* Single 5 V (10%) * High speed Access time CE access time: 70/80/100 ns (max) Cycle time Random read/write cycle time: 115/130/160 ns (min) * Low power Active: 250 mW (typ) Standby: 200 W (typ) * Directly TTL compatible All inputs and outputs * Simple address configuration Non multiplexed address * Refresh cycle 2048 refresh cycles: 32 ms
HM658512A Series
* Easy refresh functions Address refresh Automatic refresh Self refresh
Ordering Information
Type No. HM658512ALP-7 HM658512ALP-8 HM658512ALP-10 HM658512ALP-7V HM658512ALP-8V HM658512ALP-10V HM658512ALFP-7 HM658512ALFP-8 HM658512ALFP-10 HM658512ALFP-7V HM658512ALFP-8V HM658512ALFP-10V HM658512ALTT-7 HM658512ALTT-8 HM658512ALTT-10 HM658512ALTT-7V HM658512ALTT-8V HM658512ALTT-10V HM658512ALRR-7 HM658512ALRR-8 HM658512ALRR-10 HM658512ALRR-7V HM658512ALRR-8V HM658512ALRR-10V Access time 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 400-mil 32-pin plastic TSOP (TTP-32DR) 400-mil 32-pin plastic TSOP (TTP-32D) 525-mil 32-pin plastic SOP (FP-32D) Package 600-mil 32-pin plastic DIP (DP-32)
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HM658512A Series
Pin Arrangement
HM658512ALP/ALFP Series A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) HM658512ALTT Series A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 V CC A15 A17 WE A13 A8 A9 A11 OE/RFSH A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
VCC A15 A17 WE A13 A8 A9 A11 OE/RFSH A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
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HM658512A Series
Pin Arrangement (cont.)
HM658512ALRR Series VCC A15 A17 WE A13 A8 A9 A11 OE/RFSH A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
Pin Description
Pin name A0 to A18 I/O0 to I/O7 CE OE/RFSH WE VCC VSS Function Address Input/Output Chip enable Output enable/Refresh Write enable Power supply Ground
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HM658512A Series
Block Diagram
A0 Address Latch Control Row Decoder Memory Matrix (2048 x 256) x 8
A10 Column I/O Column Decoder Address Latch Control
I/O 0 I/O 7
Input Data Control
A11
A18
Refresh Control CE OE/RFSH WE Timing Pulse Gen. Read Write Control
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HM658512A Series
Pin Functions
CE: Chip Enable (Input) CE is a basic clock. RAM is active when CE is low, and is on standby when CE is high. A0 to A18: Address Inputs (Input) A0 to A10 are row addresses and A11 to A18 are column addresses. The entire addresses A0 to A18 are fetched into RAM by the falling edge of CE. OE/RFSH: Output Enable/Refresh (Input) This pin has two functions. Basically it works as OE when CE is low, and as RFSH when CE is high (in standby mode). After a read or write cycle finishes, refresh does not start if CE goes high while OE/RFSH is held low. In order to start a refresh in standby mode, OE/RFSH must go high to reset the refresh circuits of the RAM. After the refresh circuits are reset, the refresh starts when OE/RFSH goes low. I/O0 to I/O7: Input/Output (Inputs and Outputs) These pins are data I/O pins. WE: Write Enable (Input) RAM is in write mode when WE is low, and is in read mode when WE is high. I/O data is fetched into RAM by the rising edge of WE or CE (earlier timing) and the data is written into memory cells.
Refresh
There are three refresh modes : address refresh, automatic refresh and self refresh. (1) Address refresh: Data is refreshed by accessing all 2048 row addresses every 32 ms. A read is one method of accessing those addresses. Each row address (2048 addresses of A0 to A10)must be read at least once every 32 ms. In address refresh mode, OE/RFSH can remain high. In this case, the I/O pins remain at high impedance, but the refresh is done within RAM. (2) Automatic refresh: Instead of address refresh, automatic refresh can be used. RAM goes to automatic refresh mode if OE/RFSH falls while CE is high and it remains low for at least tFAP. One automatic refresh cycle is executed by one low pulse of OE/RFSH. It is not necessary to input the refresh address from outside since it is generated internally by an on-chip address counter. 2048 automatic refresh cycles must be done every 32 ms. (3) Self refresh: Self refresh mode is suitable for data retention by battery. In standby mode, a self refresh starts automatically when OE/RFSH stays low for more than 8 s. Refresh addresses are automatically specified by the on-chip address counter, and the refresh period is determined by the on-chip timer. Automatic refresh and self refresh are distinguished from each other by the width of the OE/RFSH low pulse in standby mode. If the OE/RFSH low pulse is wider than 8 s, RAM becomes into self refresh mode; if the OE/RFSH low pulse is less than 8 s, it is recognized as an automatic refresh instruction.
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HM658512A Series
At the end of self refresh, refresh reset time (tRFS) is required to reset the internal self refresh operation of the RAM. During tRFS, CE and OE/RFSH must be kept high. If auto refresh follows self refresh, low transition of OE/RFSH at the beginning of automatic refresh must not occur during tRFS period.
Notes on Using the HM658512A
Since pseudo static RAM consists of dynamic circuits like DRAM, its clock pins are more noise-sensitive than conventional SRAM's. (1) If a short CE pulse of a width less than tCE min is applied to RAM, an incomplete read occurs and stored data may be destroyed. Make sure that CE low pulses of less than tCE min are inhibited. Note that a 10 ns CE low pulse may sometimes occur owing to the gate delay on the board if the CE signal is generated by the decoding of higher address signals on the board. Avoid these short pulses. (2) OE/RFSH works as refresh control in standby mode. A short OE/RFSH low pulse may cause an incomplete refresh that will destroy data. Make sure that OE/RFSH low pulse of less than tFAP min are also inhibited. (3) tOHC and tOCD are the timing specs which distinguish the OE function of OE/RFSH from the RFSH function. The t OHC and tOCD specs must be strictly maintained. (4) Start the HM658512A operating by executing at least eight initial cycles (dummy cycles) at least 100 s after the power voltage reaches 4.5 V-5.5 V after power-on.
Function Table
CE L L L H H OE/RFSH L X H L H WE H L H X X I/O pin Dout High-Z High-Z High-Z High-Z Mode Read Write -- Refresh Standby
Note: X means H or L.
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HM658512A Series
Absolute Maximum Ratings
Parameter Terminal voltage with respect to V SS Power dissipation Operating temperature Storage temperature Storage temperature under bias Note: 1. With respect to V SS Symbol VT PT Topr Tstg Tbias Value -1.0 to +7.0 1.0 0 to +70 -55 to +125 -10 to +85 Unit V W C C C Note 1
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VCC VSS Input voltage VIH VIL Note: 1. VIL min = -3.0 V for pulse width 30 ns Min 4.5 0 2.4 -1.0 Typ 5.0 0 -- -- Max 5.5 0 6.0 0.8 Unit V V V V 1 Notes
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HM658512A Series
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10 %, VSS = 0 V)
Parameter Symbol Min Typ -- -- -- -- 1 20 Max Unit Test conditions 75 2 200 100 Operating power supply current I CC2 in self refresh mode I CC3 -- -- 1 70 40 Input leakage current Output leakage current Output voltage I LI I LO VOL VOH Notes: 1. Only for L-version. 2. Only for V-version. -10 -- -10 -- -- 2.4 -- -- 2 200 100 10 10 0.4 -- mA mA A A mA A A A A V V I I/O = 0 mA t cyc = min CE = VIH , Vin 0 V OE/RFSH = VIH CE VCC - 0.2 V, Vin 0 V, 1 OE/RFSH VCC - 0.2 V CE VCC - 0.2 V, Vin 0 V, 2 OE/RFSH VCC - 0.2 V CE = VIH , Vin 0 V, OE/RFSH = VIL CE VCC - 0.2 V, Vin 0 V, 1 OE/RFSH 0.2 V CE VCC - 0.2 V, Vin 0 V, 2 OE/RFSH 0.2 V VCC = 5.5 V, Vin = VSS to V CC OE/RFSH = VIH VI/O = VSS to V CC I OL = 2.1 mA I OH = -1 mA Notes Operating power supply current I CC1 Standby power supply current I SB1 I SB2
Capacitance (Ta = 25C, f = 1 MHz)
Parameter Input capacitance Input /output capacitance Symbol Cin CI/O Typ -- -- Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V
Note : This parameter is sampled and not 100% tested.
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HM658512A Series
AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, unless otherwise noted.)
Test Conditions * * * * * Input pulse levels: 0.4 V, 2.4 V Input rise and fall time: 5 ns Timing measurement level: 0.8 V, 2.2 V Reference levels: VOH = 2.0 V, VOL = 0.8 V Output load: 1 TTL Gate and C L (100 pF) (Including scope and jig)
HM658512A -7 Parameter Random read or write cycle time Chip enable access time Read-modify- write cycle time Output enable access time Chip disable to output in high-Z Chip enable to output in low-Z Output disable to output in high-Z Output enable to output in low-Z Chip enable pulse width Chip enable precharge time Address setup time Address hold time Read command setup time Read command hold time Write command pulse width Chip enable to end of write Symbol Min t RC t CEA t RWC t OEA t CHZ t CLZ t OHZ t OLZ t CE tP t AS t AH t RCS t RCH t WP t CW 115 -- 160 -- 0 20 -- 0 70 n 35 0 20 0 0 25 70 0 0 Max -- 70 -- 25 25 -- 25 -- 10 -- -- -- -- -- -- -- -- -- -8 Min 130 -- 180 -- 0 20 -- 0 80 n 40 0 20 0 0 25 80 0 0 Max -- 80 -- 30 25 -- 25 -- 10 -- -- -- -- -- -- -- -- -- -10 Min 160 -- 220 -- 0 20 -- 0 Max -- 100 -- 40 25 -- 25 -- Unit ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns 1, 2 2 1, 2 2 Notes
100 n 10 50 0 25 0 0 30 100 0 0 -- -- -- -- -- -- -- -- --
Chip enable to output enable delay t OCD time Output enable hold time t OHC
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HM658512A Series
AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, unless otherwise noted.) (cont.)
HM658512A -7 Parameter Data in to end of write Data in hold time for write Output active from end of write Write to output in high-Z Transition time (rise and fall) Refresh command delay time Refresh precharge time Refresh command pulse width for automatic refresh Automatic refresh cycle time Refresh command pulse width for self refresh Symbol Min t DW t DH t OW t WHZ tT t RFD t FP t FAP t FC t FAS 20 0 5 -- 3 35 35 70 n 115 8 600 -- Max -- -- -- 20 50 -- -- 8 -- -- -- 32 -8 Min 20 0 5 -- 3 40 40 80 n 130 8 600 -- Max -- -- -- 20 50 -- -- 8 -- -- -- 32 -10 Min 25 0 5 -- 3 50 40 80 n 160 8 600 -- Max -- -- -- 25 50 -- -- 8 -- -- -- 32 Unit ns ns ns ns ns ns ns s ns s ns ms 9 2048 cycle 2 1, 2 6 Notes
Refresh reset time from self refresh t RFS Refresh period t REF
Notes: 1. tCHZ, tOHZ , t WHZ are defined as the time at which the output achieves the open circuit condition. 2. tCHZ, tCLZ, tOHZ , t OLZ , t WHZ and tOW are sampled under the condition of tT = 5 ns and not 100% tested. 3. A write occurs during the overlap of low CE and low WE. Write end is defined at the earlier of WE going high or CE going high. 4. If the CE low transition occurs simultaneously with or from the WE low transition, the output buffers remain in high impedance state. 5. In write cycle, OE or WE must disable output buffers prior to applying data to the device and at the end of write cycle data inputs must be floated prior to OE or WE turning on output buffers. During this period, I/O pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 6. Transition time t T is measured between V IH (min) and VIL (max). VIH (min) and VIL (max) are reference levels for measuring timing of input signals. 7. After power-up, pause for more than 100 s and execute at least 8 initialization cycles. 8. 2048 cycles of burst refresh or the first cycle of distributed automatic refresh must be executed within 15 s after self refresh, in order to meet the refresh specification of 32 ms and 2048 cycles. 9. At the end of self refresh, refresh reset time (t RFS) is required to reset the internal self refresh operation of the RAM. During t RFS, CE and OE/RFSH must be kept high. If automatic refresh follows self refresh, low transition of OE/RFSH at the beginning of automatic refresh must not occur during t RFS period.
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HM658512A Series
Timing Waveform
Read Cycle
t RC t CE tP t AS Address A0 to A18 t AH
CE
Valid
WE t RCS OE/RFSH
t OHC t CEA t RCH t OEA t CHZ t OHZ t OLZ
Dout
Valid data out
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HM658512A Series
Write Cycle (1) (OE high)
t RC t CE CE t AS Address A0 to A18 t AH tP
Valid t CW
WE
t WP t OCD
OE/RFSH t DW t DH
Din t WHZ t CLZ Dout t OHZ
Valid Data in t OLZ t OW
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HM658512A Series
Write Cycle (2) (OE low)
t RC t CE tP t AS Address A0 to A18 t AH
CE
Valid t CW t DH t WP t OHC
WE
OE/RFSH t DW Din t WHZ t CLZ Dout Valid data in t DH
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HM658512A Series
Read-Modify-Write Cycle
t RWC t CE CE t AS Address A0 to A18 t AH tP
Valid t RCS t CEA t OHC t CW t WP t OCD t RCH
WE
OE/RFSH t OEA Din t OLZ t CLZ Dout t OHZ Valid data out t OW t DW t DH
Valid data in t CHZ
Automatic Refresh Cycle
CE
t RFD t FP t FAP
t FC t FP
t FC t FAP
OE/RFSH
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HM658512A Series
Self Refresh Cycle
CE
t RFD t FP t FAS
t RFS
OE/RFSH
Low VCC Data Retention Characteristics (Ta = 0 to +70C)
This characteristics is guaranteed only for V-version.
Parameter VCC for data retention Self refresh current Symbol VDR I CCDR Min 3.0 -- Typ -- -- Max 5.5 50 Unit V A VCC = 3.0 V, CE V CC - 0.2 V OE/RFSH 0.2 Vin 0 V VCC = 5.5 V, CE V CC - 0.2 V OE/RFSH 0.2 Vin 0 V Test conditions
--
--
100
A
Refresh setup time Operation recovery time
t FS t FR
0 5
-- --
-- --
ns ms
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HM658512A Series
Low V CC Data Retention Timing Waveform
Data Retention mode VCC 4.5V
VDR CE Vcc-0.2V
2.4V CE 0.8V t RFD t FP OE/RFSH 2.4V 0.8V OE/RFSH 0.2V t FS t FAS t FR t RFS
Notes:
1. 2. 3. 4.
Rise time and fall time of power supply voltage must be smaller than 0.05 V/ms. Keep CE VCC - 0.2 V during data retention mode. Regarding t RFD, tFP, tFAS and t RFS, refer to AC characteristics. Input voltage should be lower than V CC +1.5 V in data retention mode.
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HM658512A Series
Package Dimensions
HM658512ALP Series (DP-32)
Unit: mm
32
41.90 42.50 Max
17 13.4 13.7 Max
1 2.30 Max
5.08 Max
1.20
16 15.24
0.51 Min 2.54 Min
2.54 0.25
0.48 0.10
0.25 - 0.05 0 - 15
+ 0.11
Hitachi Code JEDEC EIAJ Weight (reference value)
DP-32 -- Conforms 5.1 g
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HM658512A Series
HM658512ALFP Series (FP-32D)
Unit: mm 20.45 20.95 Max 32 17
1 1.00 Max
16 3.00 Max 0.22 0.05 0.20 0.04
11.30
14.14 0.30 1.42
0.12 0.15 + 0.10 -
0 - 8 0.80 0.20
1.27 0.40 0.08 0.38 0.06
0.10 0.15 M
Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
FP-32D Conforms -- 1.3 g
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HM658512A Series
HM658512ALTT Series (TTP-32D)
Unit: mm 20.95 21.35 Max 32 17
1 0.42 0.08 0.40 0.06 1.15 Max
1.27 0.21
M
16
10.16
0.80 11.76 0.20 0 - 5 0.50 0.10
0.10
0.17 0.05 0.125 0.04
0.13 0.05
1.20 Max
Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TTP-32D Conforms -- 0.51 g
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HM658512A Series
HM658512ALRR Series (TTP-32DR)
Unit: mm 20.95 21.35 Max 1 16
32 0.42 0.08 0.40 0.06 1.15 Max
1.27 0.21
M
17
10.16
0.80 11.76 0.20 0 - 5 0.50 0.10
0.10
0.17 0.05 0.125 0.04
0.13 0.05
1.20 Max
Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TTP-32DR Conforms -- 0.51 g
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HM658512A Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA. 94005-1897 USA Tel: 800-285-1601 Fax:303-297-0447
Hitachi Europe GmbH Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30-00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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