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| CXB1595AN Fibre Channel Repeater Description The CXB1595AN is a clock and data recovery IC for fibre channel 1.0625Gbaud with a built-in PLL. This IC incorporates a port bypass circuit and is suitable for disk array and FC-AL HUB, etc. Features * Conforms to ANSI X3T11 Fibre Channel standard * Single 3.3V power supply * Low power consumption: 380mW (Typ.) * Low jitter * PLL lock detection circuit * Port bypass circuit * Small plastic package (30-pin SSOP) Applications * Fibre channel arbitrated loop 1.0625Gbaud HUB * Disk array Pin Configuration 30 pin SSOP (Plastic) Structure Bipolar silicon monolithic IC REFCLK LKDT VEET DIAG_OUT DIAG_OUTN VCCE LOOP_IN LOOP_INN VEEG 1 2 3 4 5 6 7 8 9 30 CDR_SELN 29 DIAG_SELN 28 LOOP_SELN 27 DIAG_IN 26 DIAG_INN 25 VCCG 24 LOOP_OUT 23 LOOP_OUTN 22 VCCE 21 PORT_OUT 20 PORT_OUTN 19 VEEE 18 PORT_SEL0N 17 PORT_SEL1N 16 VCCP PORT_IN 10 PORT_INN 11 LKREFN 12 VEEP 13 LPF1 14 LPF2 15 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E99632-PS CXB1595AN Block Diagram CDR_SELN REFCLK (TTL/I) LKDT (TTL/O) 53.125MHz (TTL/I) DIAG_SELN S 0 Y (TTL/I) LOOP_SELN (TTL/I) DIAG_IN DIAG_INN (ECL/I) 1 DIAG_OUT DIAG_OUTN (ECL/O) 1.0625Gboud S 0 LOOP_OUT LOOP_IN LOOP_INN (ECL/I) Frequency Detector Unlock Detector Recovered clock 1.0625Gboud Y LOOP_OUTN (ECL/O) 1 Low 11 00 Y 01 10 S1 S0 PORT_OUT PORT_OUTN (ECL/O) 1 PORT_IN PORT_INN (ECL/I) 1.0625Gboud Y Clock and Data Recovery Retimed data 0 S LKREFN (TTL/I) PORT_SEL0N (TTL/I) PORT_SEL1N LPF1 LPF2 (TTL/I) -2- CXB1595AN Pin Description Pin No. Symbol Type VCCG Equivalent circuit Description 1 REFCLK Input TTL TTL_IN Reference clock. This pin is used for the PLL to take the frequency. Input 53.125MHz to this pin. VEET VCCE VEEG 2 LKDT Output TTL TTL_OUT PLL lock detection signal output. Outputs high level when PLL is locked to the serial data. Outputs low level when LKREFN is in the low level or the serial data isn't locked to the serial input data. VEET 3 VEET Ground VCCE Ground for TTL I/O: 0V. 4 5 DIAG_OUT DIAG_OUTN Output ECL ECL_OUT Differential serial data output. ECL_OUTN VEEE 6 VCCE Power supply VCCE VCCG Power supply for ECL l/O: 3.3V 5%. ECL_IN 7 8 LOOP_IN LOOP_INN Input ECL VCCE - 1.3V Differential serial data input. ECL_INN VEEE VEEG -3- CXB1595AN Pin No. 9 Symbol VEEG Type Ground Equivalent circuit Description Ground for internal logic Gate: 0V. VCCE VCCG ECL_IN 10 11 PORT_IN PORT_INN Input ECL VCCE - 1.3V Differential serial data input. ECL_INN VEEE VEEG VCCG 12 LKREFN Input TTL TTL_IN Lock to reference. An active low input. LKREFN causes the PLL lock to the REFCLK. VEET VEEG 13 VEEP Ground VCCP Ground for PLL: 0V. 14 15 LPF1 LPF2 External circuit node LPF1 LPF2 Connect to external loop filter. VEEP 16 VCCP Power supply VCCG Power supply for PLL: 3.3V 5%. 17 18 PORT_SEL1N PORT_SEL0N Input TTL TTL_IN Selection for PORT_OUT. VEET VEEG -4- CXB1595AN Pin No. 19 Symbol VEEE Type Ground Equivalent circuit Description Ground for ECL I/O: 0V. VCCE 20 21 PORT_OUTN PORT_OUT Output ECL ECL_OUT Differential serial data output. ECL_OUTN VEEE 22 VCCE Power supply VCCE Power supply for ECL I/O: 3.3V 5%. 23 24 LOOP_OUTN LOOP_OUT Output ECL ECL_OUT Differential serial data output. ECL_OUTN VEEE 25 VCCG Power supply VCCE VCCG Power supply for internal logic gate: 3.3V 5%. ECL_IN 26 27 DIAG_INN DIAG_IN Input ECL VCCE - 1.3V Differential serial data input. ECL_INN VEEE VEEG VCCG 28 LOOP_SELN Selection for LOOP_OUT. See table 9. 29 DIAG_SELN Input TTL TTL_IN Selection for DIAG_OUT. See table 9. Selection for CDR input. See table 9. 30 CDR_SELN VEET VEEG -5- CXB1595AN Electrical Characteristics Table 1. Absolute Maximum Ratings Item Power supply voltage TTL DC input voltage ECL DC input voltage ECL input voltage between differential signal TTL output current (High) TTL output current (Low) ECL output current Storage temperature Symbol VCC VI_T VI_E II_E IOH_T IOL_T IO_E Tstg Min. -0.3 -0.5 VCC - 2 -4 -20 0 -30 -65 Typ. (VEEE, VEET, VEEG, VEEP = GND) Max. 4 5.5 VCC 4 0 20 0 150 Unit V V V V mA mA mA C Comments Table 2. Recommended Operating Conditions Item Power supply voltage Ambient temperature Symbol VCC Ta Min. 3.135 0 Typ. 3.3 Max. 3.465 70 Unit V C Comments -6- CXB1595AN Table 3. DC Characteristics Item Input high voltage (TTL) Input low voltage (TTL) Input high current (TTL) Input low current (TTL) Output high voltage (TTL) Output low voltage (TTL) Differential input voltage swing Differential output voltage peak-to-peak Supply current Power dissipation Symbol VIH_T VIL_T IIH_T IIL_T VOH_T VOL_T VIS_E VOS_E ICC PD VIN = VCC VIN = 0 IOH = -0.4mA IOL = 2mA (Over recommended operating conditions) Conditions Min. 2.8 0 Typ. Max. 5.5 0.8 20 -400 2.2 0 200 1200 VCC 0.5 1000 2000 154 534 Unit V V A A V V mV mV mA mW AC coupling input 50 to Vcc - 2V Outputs open Outputs open Table 4. AC Characteristics Item Input TTL rise time of REFCLK Input TTL fall time of REFCLK Output TTL rise time Output TTL fall time Output ECL rise time Output ECL fall time Serial data rate REFCKL frequency tolerance REFCKL duty cycle tolerance Total Jitter tolerance peak-to-peak, 10E-12BER Deterministic jitter output peak-to-peak Random jitter output, rms Jitter transfer peaking Jitter transfer 3dB bandwidth Bit sync time Frequency acquisition time Lock detect range Symbol Tir_RC Tif_RC Tor_T Tof_T Tor_E Tof_E SDR (Over recommended operating conditions) Conditions 0.8 to 2.0V 2.0 to 0.8V 0.8 to 2.0V, CL = 10pF 2.0 to 0.8V, CL = 10pF 20 to 80%, CL = 2pF 20 to 80%, CL = 2pF 1.0UI = 941ps -100 1062.5 100 10 1 K28.5 serial data, 637kHz HPF 1 00110011 serial data, 637kHz HPF 1 00110011 input 1 640 2500 800 -2 2 0.7 0.07 Min. Typ. Max. 4.8 4.8 3.5 3.5 400 400 Unit ns ns ns ns ps ps MBd PPM % UI UI RC_TOL 53.125MHz REFCLK RC_DC TJT DJgen RJgen JXFR_PK 0.0125 UIrms 0.2 dB kHz bit s % JXFR_3dB 00110011 input 1 Tbs FC Idle pattern 1, 2 Tfa LDR 1 Frequency difference between recovered Clock and REFCLK 1 The values of LPF R/2 is 200 and LPF C is 0.022F. 2 CXB1595AN starts Bit synchronization in 10s after LKREFN changed to high. -7- CXB1595AN Table 5. Function of LOOP_OUT LOOP_SELN H L LOOP_OUT Recovered Data LOOP_IN Table 6. Function of DIAG_OUT DIAG_SELN H L DIAG_OUT Recovered Data DIAG_IN Table 7. Function of PORT_OUT PORT_SEL0N H L H L PORT_SEL1N H H L L PORT_OUT Low Recovered Data DIAG_IN LOOP_IN Table 8. Function of Recovered data PORT_SEL0N H L H L H L H L PORT_SEL1N H H L L H H L L CDR_SELN H H H H L L L L Recovered Data Low -- DIAG_IN LOOP_IN PORT_IN PORT_IN PORT_IN PORT_IN -8- CXB1595AN Table 9. Selection of Signal PORT_SEL0N PORT_SEL1N LOOP_SELN DIAG_SELN CDR_SELN PORT_OUT LOOP_OUT DIAG_OUT 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low PORT_IN DIAG_IN LOOP_IN Low PORT_IN DIAG_IN LOOP_IN Low PORT_IN DIAG_IN LOOP_IN Low PORT_IN DIAG_IN LOOP_IN Low Low DIAG_IN LOOP_IN LOOP_IN LOOP_IN LOOP_IN LOOP_IN Low Low DIAG_IN LOOP_IN LOOP_IN LOOP_IN LOOP_IN LOOP_IN PORT_IN PORT_IN PORT_IN PORT_IN LOOP_IN LOOP_IN LOOP_IN LOOP_IN PORT_IN PORT_IN PORT_IN PORT_IN LOOP_IN LOOP_IN LOOP_IN LOOP_IN Low Low DIAG_IN LOOP_IN Low Low DIAG_IN LOOP_IN DIAG_IN DIAG_IN DIAG_IN DIAG_IN DIAG_IN DIAG_IN DIAG_IN DIAG_IN PORT_IN PORT_IN PORT_IN PORT_IN PORT_IN PORT_IN PORT_IN PORT_IN DIAG_IN DIAG_IN DIAG_IN DIAG_IN DIAG_IN DIAG_IN DIAG_IN DIAG_IN Boldface type is recovered data. -9- CXB1595AN Application Circuit 1. Power and loop filter 3.3V 22F GND 1 2 3 4 5 6 7 8 9 REFCLK LKDT VEET DIAG_OUT DIAG_OUTN VCCE LOOP_IN LOOP_INN VEEG CDR_SELN 30 DIAG_SELN 29 LOOP_SELN 28 DIAG_IN 27 DIAG_INN 26 VCCG 25 LOOP_OUT 24 LOOP_OUTN 23 VCCE 22 PORT_OUT 21 PORT_OUTN 20 VEEE 19 PORT_SEL0N 18 PORT_SEL1N 17 VCCP 16 10 PORT_IN 11 PORT_INN 12 LKREFN 200 0.022F 15 LPF2 200 13 VEEP 14 LPF1 VCC VCC 0.1F VEE VEE Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 0.1F 2. Serial input and output VCC = 3.3V VEE = GND ZO = 75 0.01F 150 150 CXB1595AN output 150 0.01F CXB1595AN input Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 10 - CXB1595AN Description of Operation 1. Clock and data recovery The PLL in the clock and data recovery block must be frequency locked to the external REFCLK before locking to the data. The LKREFN pin is used to lock the frequency. When the LKREFN pin is low, the PLL frequency is locked to the external REFCLK and when high, it is locked to the input serial data. Up to 800s is required to lock the frequency. 2. Frequency detector The frequency detector constantly monitors the offset between the clock obtained by 1/20 frequency-dividing the recovered clock and the external REFCLK. It outputs high when this offset is less than 1.6%, and low when this offset is 1.6% or more. Note on Operation The following values are recommended for the external resistors and capacitor used as the loop filter. 200 14 0.022F 15 200 - 11 - CXB1595AN Example of Jitter Transfer Measurement Jitter Transfer 5 0 Jitter ratio [dB] -5 -10 -15 Input data = 00110011... Loop filter resistor = 200 Loop filter capacitor = 0.022F -20 100 1000 104 Frequency [Hz] 105 106 107 - 12 - CXB1595AN Example of Representative Characteristics PORT-OUT Output Eye Pattern (1.0625Gbps Retimed data) X: 200ps/div Y: 200mV/div Example of Random Jitter Measurement X: 100ps/div Y: 200mV/div Input data = 010101... Random Jitter = 9.1ps (rms) - 13 - CXB1595AN Package Outline Unit: mm 30PIN SSOP (PLASTIC) + 0.2 1.25 - 0.1 9.7 0.1 0.10 30 16 5.6 0.1 A 1 b 0.13 M 15 0.65 + 0.05 0.15 - 0.02 + 0.1 b=0.22 - 0.05 (0.22) 0.1 0.1 7.6 0.2 b=0.22 0.03 DETAIL B : PALLADIUM EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.1g 0.5 0.2 DETAIL B : SOLDER NOTE: Dimension "" does not include mold protrusion. 0 to 10 PACKAGE STRUCTURE DETAIL A PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-30P-L01 SSOP030-P-0056 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS - 14 - + 0.03 0.15 - 0.01 (0.15) |
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