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PEDL66577-01
Semiconductor 1 MSM66577 Family
16-Bit Microcontroller
This version: Apr. 2000
Preliminary
GENERAL DESCRIPTION
The MSM66577 family of highly functional CMOS 16-bit single chip microcontrollers utilizes the nX-8/500S, Oki's proprietary CPU core. Four channels of serial ports, consisting of two channels of synchronous serial ports with 32-byte FIFO registers and two channels of UART/synchronous serial ports, enable easy interfacing with external peripheral LSI devices such as an encoder/decoder or servocontroller. A switching function permits selection of separate address and data lines or multiplexed lines for the external bus interface to correspond to various peripheral LSI devices. With features such as a clock gear function, dual clock function, STOP/HALT mode, programmable pull-up ports in which individual bits can be programmed, and a small, thin package, the MSM66577 family of microprocessors is optimally suited for the system control of small-sized low power devices. The flash ROM version (MSM66Q577LY) programmable with a single 3V power supply (3.0 to 3.6V) and flash ROM version (MSM66Q577) programmable with a single 5V power supply (4.5 to 5.5V) are also included in the family. These versions are easily adaptable to sudden specification changes and to new product versions.
APPLICATIONS
Digital Audio Control Systems PC peripheral Control Systems Office Electronics Control Systems
ORDERING INFORMATION
Order Code or Product Name MSM66577L-xxTB *1 MSM66577-xxTB *1 MSM66Q577LY-NTB *2 100-pin plastic TQFP (TQFP 100-P-1414-0.50-K) Package Remark Low voltage mask ROM version (2.4 to 3.6 V) 5 V mask ROM version (4.5 to 5.5 V) MSM66577L flash ROM version (3.0 to 3.6V)
MSM66Q577-NTB *2 MSM66577 flash ROM version (4.5 to 5.5 V) *1 : The "xx" of "-xx" stands for the code number. *2 : The "N" of "-N" stands for the flash ROM and the OTP ROM, blank version. When OKI programs and ship the flash ROM and OTP, the part number is changed from "-N" to "-XX" (code number ) , for example, MSM66Q577-999TB.
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FEATURES
Name Operating temperature Power supply voltage/ maximum frequency Minimum instruction execution time Internal ROM size (max. external) Internal RAM size (max. external) I/O ports MSM66577L -30C to +70C VDD = 2.4 to 3.6 V/f = 14 MHz 143 ns at 14 MHz 128 KB (1 MB) 4 KB (1 MB) 74 I/O pins (with programmable pull-up resistors) 8 input-only pins 16-bit free running timer x 1ch Compare output/capture input x 2ch 16-bit timer (auto reload/timer out) x 1ch 8-bit auto reload timer x 2ch (can also be used as 16-bit timer x 1ch) Timers 8-bit auto reload timer x 1ch 8-bit auto reload timer x 3ch (also functions as serial communication baud rate generator) 8-bit auto reload timer x 1ch (also functions as watchdog timer) Watch timer (Real-timer counter) x 1ch 8-bit PWM x 4ch (can also be used as 16-bit PWM x 2ch) Serial port A/D converter D/A converter External interrupt Interrupt priority Synchronous, with 32-byte FIFO x 2ch UART/Synchronous x 2ch 10-bit A/D converter x 8ch 8-bit D/A converter x 2ch Non-maskable x 1ch Maskable x 8ch 3 levels External bus interface (Separate address and data busses / multiplexed address and data busses) Others Bus release function Dual clocks function Clock gear function Flash ROM version MSM66Q577LY (VDD=3.0 to 3.6V) MSM66Q577 VDD = 4.5 to 5.5 V/f = 30 MHz 67 ns at 30 MHz 61 s at 32.768 kHz MSM66577
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SPECIAL FEATURES
1. High-performance CPU The family includes the high-performance CPU, powerful bit manipulation instruction set, full symmetrical addressing mode, and ROM WINDOW function, and also provides the best optimized C compiler support. 2. A variety of power saving modes Attaching a 32.768-kHz crystal produces a real-time clock signal from the internal clock timer. Use of a single clock in place of dual clocks is possible. The clock gear function allows a 1/2 x or 1/4 x main clock to be selected for the CPU operating clock. Switching the CPU clock to 32.768-kHz signal, 1/2 x main clock, or 1/4 x main clock, then produces operation in a low power consumption mode. The family provides a wide range of standby control functions. In addition to the usual STOP mode that stops the oscillator, there are the quick restart STOP mode that shuts down the CPU and peripherals but leaves the oscillator running, and the HALT mode that shuts down the CPU but leaves the peripherals running. 3. Variety of multifunctional serial ports The family includes two channels of built-in synchronous serial ports with 32-byte FIFO implementing an auto transfer function. The family allows multi-byte 1-frame information which consists of address, command, and data to be easily and efficiently transmitted to or received from a serial interface type peripheral LSI device. The family also allows multi-byte character information to be easily and efficiently transmitted to or received from an LCD module. In addition, the family has two channels of combined UART/synchronous serial ports, and provides four channels of serial interfaces.
UART/synchronous SIO UART/synchronous SIO Synchronous SIO with 32-byte FIFO Synchronous SIO with 32-byte FIFO
4. MSM66Q577LY and MSM66Q577 with flash memory programmable with single power supply In addition to the regular mask ROM version, the family includes these versions with 128KB of flash memory that can be programmed using a single power supply. For the MSM66Q577LY, an internal booster circuit derives the necessary program voltage from the device's low (3.0 to 3.6V) power supply, and the program voltage for the MSM66Q577 is provided with a single 5 V power supply (4.5 to 5.5 V). 5. High-precision A/D and D/A converters The family includes a high-precision 10-bit analog-to-digital converter with eight channels and 8-bit digital-toanalog converter with two channels.
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6. Multifunction PWM The family supports both 8- and 16-bit PWM operation. Choosing between the time-base counter output or overflow from an 8-bit auto-reload timer as the PWM counter clock source provides a wide number of possibilities over a broad frequency range. The 16-bit PWM configuration supports a high-speed synchronization mode that generates a high-precision output signal with less ripple suitable for digital-to-analog control applications. 7. Programmable pull-up resistors Building the pull-up resistors into the chip contributes to overall design compactness. Making them programmable on a per-bit basis allows complete flexibility in circuit board layout and system design. These programmable pull-up resistors are available for all I/O pins not already assigned specific functions (such as the oscillator connection pins). 8. Wide support for external interrupts There are a total of nine interrupt channels for use in communicating with external devices: eight for maskable interrupts and one for non-maskable interrupts.
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BLOCK DIAGRAM
TM0OUT TM0EVT TM1OUT TM1EVT TM2OUT TM2EVT CLKOUT XTOUT RXD1 TXD1 RXC1 TXC1 TM4OUT RXD6 TXD6 RXC6 TXC6 16 bit Timer0 CPU Core 8 bit Timer1 8 bit Timer2 System Control Peripheral SIO1 (UART/SYNC)
ALU Control ACC
ALU Control Registers SSP LRB PSW PC
CSR
XT0 XT1 OSC0 OSC1 HOLD HLDACK RES
8 bit Time4/BRG SIO6 (UART/SYNC)
Memory Control Pointing Registers Local Registers
DSR TSR
8 bit Timer3/BRG SIOI4 SIOO4 SIOCK4 SIO4
(32 byte FIFO SYNC)
Instruction Decoder EA SELMBUS PSEN RD WR WAIT D0 to D7 (AD0 to AD7*) A0 to A19 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P14 P15
8 bit Timer5/BRG SIOI5 SIOO5 SIOCK5 SIO5
(32 byte FIFO SYNC)
RAM 4K
ROM 128K Bus Port Control
8 bit Timer6/WDT PWMOUT0 PWMOUT2 PWMOUT1 PWMOUT3 8 bit Timer9 CPCM0 CPCM1 CAP/CMP 16 bit FRC VREF AGND AI0 to AI7 AO0 AO1 NMI EXINT0 to EXINT7 10 bit A/D Converter
8 bit D/A Converter
8 bit PWM0 8 bit PWM1
TBC
RTC
Interrupt *: Address output/data I/O when selecting multiplexed bus type.
Port Control
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PIN CONFIGURATION (TOP VIEW)
95
90
85
SIOCK4/P10-3 SIOO4/P10-4 SIOI4/P10-5 RXD1/P8-0 TXD1/P8-1 RXC1/P8-2 TXC1/P8-3 TM4OUT/P8-4 PWM2OUT/P8-6 PWM3OUT/P8-7 PWM0OUT/P7-6 PWM1OUT/P7-7 VDD GND HLDACK/P9-7 EXINT4/P9-0 EXINT5/P9-1 EXINT6/P9-2 EXINT7/P9-3 EXINT0/P6-0 EXINT1/P6-1 EXINT2/P6-2 EXINT3/P6-3 TM1EVT/P6-4 TM1OUT/P6-5
100
80
TXC6/P15-3 RXC6/P15-2 TXD6/P15-1 RXD6/P15-0 SIOCK5/P14-0 SIOO5/P14-1 SIOI5/14-2 GND AO0/P14-6 AO1/P14-7 AGND AI7/P12-7 AI6/P12-6 AI5/P12-5 AI4/P12-4 AI3/P12-3 AI2/P12-2 AI1/P12-1 AI0/P12-0 VREF VDD A19/P2-3 A18/P2-2 A17/P2-1 A16/P2-0
1
75
5 70
10 65
15 60
20 55
25
30 35 40 45 50
P1-7/A15 P1-6/A14 P1-5/A13 P1-4/A12 P1-3/A11 P1-2/A10 P1-1/A9 P1-0/A8 P4-7/A7 P4-6/A6 P4-5/A5 P4-4/A4 P4-3/A3 P4-2/A2 P4-1/A1 P4-0/A0 GND P0-7/D7(AD7*) P0-6/D6(AD6*) P0-5/D5(AD5*) P0-4/D4(AD4*) P0-3/D3(AD3*) P0-2/D2(AD2*) P0-1/D1(AD1*) P0-0/D0(AD0*)
*: Address output/data I/O when selecting multiplexed bus type.
P6-6/TM2EVT P6-7/TM2OUT P5-4/CPCM0 P5-5/CPCM1 P5-6/TM0OUT P5-7/TM0EVT RES NMI EA VDD XT0 XT1 GND OSC0 OSC1 VDD P11-0/WAIT P11-1/HOLD P11-2/CLKOUT P11-3/XTOUT SELMBUS P3-0/ALE P3-1/PSEN P3-2/RD P3-3/WR
100-pin Plastic TQFP
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PIN DESCRIPTIONS
In the Type column, "I" indicates an input pin, "O" indicates an output pin, and "I/O" indicates an I/O pin.
Description Function Port Symbol Type P0_0/D0 (AD0) to P0_7/D7 (AD7) P1_0/A8 to P1_7/A15 P2_0/A16 to P2_3/A19 P3_0/ALE I/O Primary function
8-bit I/O port 10 mA sink capability Pull-up resistors can be specified for each individual bit 8-bit I/O port Pull-up resistors can be specified for each individual bit
Type
Secondary function
External memory access Data I/O port
(Address output/data I/O port when selecting a multiplexed bus)
I/O
I/O
External memory access
O
Address output port
I/O
4-bit I/O port Pull-up resistors can be specified for each individual bit 4-bit I/O port 10 mA sink capability Pull-up resistors can be specified for each individual bit
O
External memory access Address output port External memory access Address latch enable signal output pin External program memory access Read strobe output pin External memory access Read strobe output pin External memory access Write strobe output pin External memory access Address output port (When selecting a separate bus type) Capture 0 input / Compare 0 output pin Capture 1 input / Compare 1 output pin Timer 0 timer output pin Timer 0 external event input pin External interrupt 0 input pin External interrupt 1 input pin External interrupt 2 input pin External interrupt 3 input pin Timer1 external event input pin Timer 1 timer output pin Timer 2 external event pin Timer 2 timer output pin
O
P3_1/PSEN I/O P3_2/RD P3_3/WR P4_0/A0 to P4_7/A7 P5_4/CPCM0 P5_5/CPCM1
P5_6/TM0OUT P5_7/TM0EVT
O
O O
8-bit I/O port Pull-up resistors can be specified for each individual bit 4-bit I/O port Pull-up resistors can be specified for each individual bit
I/O
O
I/O I/O O I
I/O
P6_0/EXINT0 P6_1/EXINT1 P6_2/EXINT2 P6_3/EXINT3 P6_4/TM1EVT P6_5/TM1OUT P6_6/TM2EVT P6_7/TM2OUT I/O
8-bit I/O port Pull-up resistors can be specified for each individual bit
I I I I I O I O
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Description Function Port Symbol Type
P7_6/PWM0OUT P7_7/PWM1OUT
Primary function
2-bit I/O port Pull-up resistors can be specified for each individual bit 7-bit I/O port Pull-up resistors can be specified for each individual bit
Type O O I O I/O I/O O O O
Secondary function
PWM0 output pin PWM1 output pin SIO1 receive data input pin SIO1 transmit data output pin SIO1 receive clock I/O pin SIO1 transmit clock I/O pin Timer 4 timer output pin PWM2 output pin PWM3 output pin External Interrupt 4 input pin External Interrupt 5 input pin External Interrupt 6 input pin External Interrupt 7 input pin HOLD mode output pin
SIO4 transmit-receive clock I/O pin
I/O
P8_0/RXD1 P8_1/TXD1 P8_2/RXC1 P8_3/TXC1 P8_4/TM4OUT
P8_6/PWM2OUT P8_7/PWM3OUT
I/O
P9_0/EXINT4 P9_1/EXINT5 P9_2/EXINT6 P9_3/EXINT7 P9_7/HLDACK P10_3/SIOCK4 P10_4/SIOO4 P10_5/SIOI4 P11_0/WAIT P11_1/HOLD P11_2/CLKOUT P11_3/XTOUT P12_0/AI0 to P12_7/AI7 P14_0/SIOCK5 P14_1/SIOO5 P14_2/SIOI5 P14_6/AO0 P14_7/AO1 P15_0/RXD6 P15_1/TXD6 P15_2/RXC6 P15_3/TXC6 I/O I/O I I/O I/O I/O
5-bit I/O port Pull-up resistors can be specified for each individual bit
I I I I O
3-bit I/O port Pull-up resistors can be specified for each individual bit 4-bit I/O port 10 mA sink capability Pull-up resistors can be specified for each individual bit
I/O I O I I O O
SIO4 receive data input pin SIO4 transmit data output pin External data memory access wait input pin HOLD mode request input pin Main clock pulse output pin Sub clock pulse output pin A/D converter analog input port
8-bit input port
I
5-bit I/O port Pull-up resistors can be specified for each individual bit SIO5 transmit-receive clock I/O pin SIO5 transmit data output pin SIO5 receive data input pin D/A converter analog output port D/A converter analog output port SIO6 receive data input pin SIO6 transmit data output pin SIO6 receive clock I/O pin SIO6 transmit clock I/O pin
I/O O I O O
4-bit I/O port Pull-up resistors can be specified for each individual bit
I O I/O I/O
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Function Power supply
Symbol VDD GND VREF AGND
Type I I I I I O
Description Power supply pin Connect all VDD pins to the power supply.* GND pin Connect all GND pins to GND.* Analog reference voltage pin Analog GND pin Sub clock oscillation input pin Connect to a crystal oscillator of f = 32.768 kHz. Sub clock oscillation output pin Connect to a crystal oscillator of f = 32.768 kHz. The clock output is opposite in phase to XT0. Main clock oscillation input pin Connect to a crystal or ceramic oscillator. Or, input an external clock. Main clock oscillation output pin Connect to a crystal or ceramic oscillator. The clock output is opposite in phase to OSC0. Leave this pin unconnected when an external clock is used. Reset input pin Non-maskable interrupt input pin External program memory access input pin If the EA pin is enabled (low level), the internal program memory is masked and the CPU executes the program code in external program memory through all address space. SELMBUS = H: Address/data separate bus type SELMBUS = L: Multiplexed bus type
Oscillation
XT0 XT1
OSC0
I
OSC1
O
Reset Other
RES NMI EA
I I I
SELMBUS
I
* Each of the family devices has unique pattern routes for the internal power and ground. Connect the power supply voltage to all VDD pins and the ground potential to all GND pins. If a device may have one or more VDD or GND pins to which the power supply voltage or the ground potential is not connected, it can not be guaranteed for normal operation.
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ABSOLUTE MAXIMUM RATINGS
Parameter Digital power supply voltage Input voltage Output voltage Analog reference voltage Analog input voltage Power dissipation Storage Temperature Symbol VDD VI VO VREF VAI PD TSTG Ta = 70C per package -- GND = AGND = 0 V Ta = 25C Condition MSM66577/Q577 MSM66577L/Q577LY -- -- -- -- 100-pin TQFP Rating -0.3 to +7.0 -0.3 to +4.6 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to VREF 650 -50 to +150 Unit V V V V V V mW C
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Condition MSM66577 MSM66Q577 Digital power supply voltage VDD MSM66577L MSM66Q577LY Analog reference voltage Analog input voltage Memory hold voltage VREF VAI VDDH -- -- fOSC = 0 Hz MSM66577 MSM66Q577 Operating frequency fOSC MSM66577L VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VDD = 2.4 to 3.6 V fOSC 30 MHz fOSC 30 MHz fOSC 14 MHz fOSC 14 MHz Range 4.5 to 5.5 4.5 to 5.5 V 2.4 to 3.6 3.0 to 3.6 VDD -0.3 to VDD AGND to VREF 2.0 to 5.5 2 to 30 2 to 30 MHz 2 to 14 2 to 14 32.768 -30 to +70 20 6 1 kHz C -- -- -- V V V Unit
MSM66Q577LY VDD = 3.0 to 3.6V fXT Ambient temperature Ta -- -- MOS load P0, P3, P11 Fan out N TTL load P1, P2, P4, P5, P6, P7, P8, P9, P10, P14, P15
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ALLOWABLE OUTPUT CURRENT VALUES
MSM66577/Q577 (VDD = 4.5 to 5.5 V, Ta = -30 to +70C) MSM66577L (VDD = 2.4 to 3.6 V, Ta = -30 to +70C) MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = -30 to +70C) Parameter "H" output pin (1 pin) "H" output pins (sum total) "L" output pin (1 pin) Pin All output pins Sum total of all output pins P0, P3, P11 Other ports Sum total of P0, P3, P11 Sum total of P1, P2, P4 "L" output pins (sum total) Sum total of P5, P6, P9 Sum total of P7, P8, P10, P14, P15 Sum total of all output pins 140 IOL -- -- 50 Symbol IOH IOH IOL Min. -- -- -- Typ. -- -- -- Max. -2 -40 10 5 80 mA Unit
[Note] Each of the family devices has unique pattern routes for the internal power and ground. Connect the power supply voltage to all VDD pins and the ground potential to all GND pins. If a device may have one or more VDD or GND pins to which the power supply voltage or the ground potential is not connected, it can not be guaranteed for normal operation.
INTERNAL FLASH ROM PROGRAMMING CONDITIONS
Parameter Supply Voltage Ambient Temperature Endurance Blocks size Symbol VDD Ta CEP -- Condition MSM66Q577 MSM66Q577LY During Read During Programming -- -- Rating 4.5 to 5.5 3.0 to 3.6 -30 to +70 +0 to +50 100 128 Unit V C Cycles bytes
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ELELCTRICAL CHARACTERISTICS
DC Characteristics 1 (VDD = 4.5 to 5.5 V)
(VDD = 4.5 to 5.5 V, Ta = -30 to +70C) Parameter "H" input voltage "L" input voltage
*1
Symbol VIH VIL VOH
Condition -- -- IO = -400 A IO = -2.0 mA IO = 3.2 mA IO = 10.0 mA IO = 1.6 mA IO = 5.0 mA
Min. 0.44VDD 0.80VDD -0.3 -0.3 VDD-0.4 VDD-0.6 -- -- -- -- -- -- --
Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50 5 7 -- --
Max. VDD+0.3 VDD+0.3 0.16VDD 0.2VDD -- -- 0.4 0.8 0.4 0.8 1/-1 1/-250 15/-15 10 100 -- -- 4 10
Unit
"H" input voltage *2,*3,*4,*5,*6
*1
"L" input voltage *2,*3,*4,*5,*6 "H" output voltage "L" output voltage "L" output voltage Input leakage current Input current Input current *1, *2, *4 *1, *4
V
VOL *2 *3 *5 *6 *1, *2, *4 Pull-up resistance Input capacitance Output capacitance Analog reference supply current ILO Rpull CI CO IREF IIH/IIL
VI = VDD/0 V
A
Output leakage current
VO = VDD/0 V VI = 0 V f = 1 MHz, Ta = 25C During A/D operation When A/D is stopped
-- 25 -- -- -- --
A k pF mA A
*1: Applicable to P0 *2: Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10, P14, P15 *3: Applicable to P12, SELMBUS, EA, NMI *4: Applicable to P3, P11 *5: Applicable to RES *6: Applicable to OSC0
Supply current (VDD=4.5 to 5.5 V) (VDD=4.5 to 5.5 V, Ta=-30 to +70C)
Condition Min. Typ. Max. Unit f=30 MHz -- 60 90 mA CPU operation mode *1 IDD f=32.768 kHz -- 80 180 A HALT mode *2 IDDH f=30 MHz -- 40 60 mA XT is used -- 5 110 OSC is stopped XT is not used -- 1 100 STOP mode *3 IDDS A OSC is stopped, XT is not used -- 0.2 10 VDD=2 V, Ta=25C [Note] Ports used as inputs are at VDD or 0 V. Other ports are unloaded. *1. CPU and all the peripheral functions (timer, PWM, A/D, etc.) are activated. *2. CPU is stopped, and all the peripheral functions (timer, PWM, A/D, etc.) are activated. *3. CPU and all the peripheral functions are deactivated (The clock timer is being activated when the XT is used). Mode Symbol
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DC Characteristics 2 (VDD = 2.4 to 3.6 V)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = -30 to +70C) MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = -30 to +70C) Parameter "H" input voltage
*1
Symbol VIH
Condition MSM66577L MSM66Q577LY --
Min. 0.44VDD 0.55VDD 0.80VDD -0.3 -0.3 VDD-0.4 VDD-0.8 VDD-0.4 VDD-0.8 -- -- -- -- -- -- -- -- 40 -- -- -- --
Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100 5 7 -- --
Max. VDD+0.3 VDD+0.3 VDD+0.3 0.16VDD 0.2VDD -- -- -- -- 0.5 0.9 0.5 0.9 1/-1 1/-250 15/-15 10 200 -- -- 2 5
Unit
"H" input voltage *2,*3,*4,*5,*6 "L" input voltage
*1
"L" input voltage *2,*3,*4,*5,*6 "H" output voltage "H" output voltage "L" output voltage "L" output voltage Input leakage current Input current Input current Pull-up resistance Input capacitance Output capacitance Analog reference supply current *1, *4
VIL
-- IO = -400 A
VOH *2 *1, *4 VOL *2 *3 *5 *6 ILO Rpull CI CO IREF IIH/IIL
IO = -2.0 mA IO = -200 A IO = -1.0 mA IO = 3.2 mA IO = 5.0 mA IO = 1.6 mA IO = 2.5 mA VI = VDD/0 V VO = VDD/0 V VI = 0 V f = 1 MHz, Ta = 25C During A/D operation When A/D is stopped
V
A A k pF mA A
Output leakage current *1, *2, *4
*1: Applicable to P0 *2: Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10, P14, P15 *3: Applicable to P12 *4: Applicable to P3, P11, SELMBUS, EA, NMI *5: Applicable to RES *6: Applicable to OSC0
Supply current (VDD=2.4 to 3.6 V)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = -30 to +70C) MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = -30 to +70C) Mode Symbol Condition Min. Typ. Max. Unit f=14 MHz -- 15 30 mA CPU operation mode *1 IDD f=32.768 kHz -- 50 150 A HALT mode *2 IDDH f=14 MHz -- 10 20 mA XT is used* -- 3 110 OSC is stopped XT is not used* -- 1 100 STOP mode *3 IDDS A OSC is stopped, XT is not used -- 0.2 10 VDD=2 V, Ta=25C* [Note] Ports used as inputs are at VDD or 0 V. Other ports are unloaded. *1. CPU and all the peripheral functions (timer, PWM, A/D, etc.) are activated. *2. CPU is stopped, and all the peripheral functions (timer, PWM, A/D, etc.) are activated. *3. CPU and all the peripheral functions are deactivated (The clock timer is being activated when the XT is used).
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AC Characteristics 1 (VDD = 4.5 to 5.5 V) (1) Separate Bus Type External program memory control
(VDD = 4.5 to 5.5 V, Ta = -30 to +70C) Parameter Cycle time Clock pulse width (HIGH level) Clock pulse width (LOW level) PSEN pulse width PSEN pulse delay time Address setup time Address hold time Instruction setup time Instruction hold time Read data access time Symbol tcyc tWH tWL tPW tPD tAS tAH tIS tIH tACC CL = 50 pF Condition fOSC = 30 MHz Min. 33.3 13 13 2 t - 15 -- t - 25 0 25 0 -- Max. -- -- -- -- 45 -- -- -- -- 3 t - 65 ns Unit
Note: t = tcyc/2
tcyc
CPUCLK
tWH PSEN
tWL
tPD
tPW
A0 to A19 tAS D0 to D7 tACC
PC0 to 19 tAH
INST0 to 7 tIS tIH
Bus timing during no wait cycle time
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External data memory control
(VDD = 4.5 to 5.5 V, Ta = -30 to +70C) Parameter Cycle time Clock pulse width (HIGH level) Clock pulse width (LOW level) RD pulse width WR pulse width RD pulse delay time WR pulse delay time Address setup time Address hold time Read data setup time Read data hold time Read data access time Write data setup time Write data hold time Symbol tcyc tWH tWL tRW tWW tRD tWD tAS tAH tRS tRH tACC tWS tWH tcyc CL = 50 pF Condition fOSC = 30 MHz Min. 33.3 13 13 2 t - 15 2 t - 15 -- -- t - 25 t - 3 25 0 -- 2t - 30 t - 3 Max. -- -- -- -- -- 45 45 -- -- -- -- 3t -65 -- -- ns Unit
Note: t = tcyc/2
CPUCLK tWH RD tRD tRW tWL
A0 to A19 tAS D0 to D7 tACC WR
RAP0 to 19 tAH DIN0 to 7 tRS tRH
tWD RAP0 to 19 tAS D0 to D7
tWW
A0 to A19
tAH DOUT0 to 7 tWS tWH
Bus timing during no wait cycle time
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MSM66577 Family
(2) Multiplexed bus type External program memory control
(VDD = 4.5 to 5.5 V, Ta = -30 to +70C) Parameter Cycle time Clock pulse width (HIGH level) Clock pulse width (LOW level) ALE pulse width PSEN pulse width PSEN pulse delay time Low address setup time Low address hold time High address setup time High address hold time Instruction setup time Instruction hold time Symbol tcyc tWH tWL TAW tPW tPAD tALS tALH tAHS tAHH tIS tIH CL = 50 pF Condition fOSC = 30 MHz Min. 33.3 13 13 2 t - 10 2 t - 15 t - 3 2t - 15 t - 3 3t - 25 0 25 0 Max. -- -- -- -- -- -- -- -- -- -- -- t - 3 ns Unit
Note: t = tcyc/2
tcyc
CPUCLK tWH tAW tWL
ALE PSEN
tPAD AD0 to AD7 tALS A8 to A19 tAHS
tPW INST0 to 7
PC0 to 7 tALH
tIS
tIH
PC8 to 19 tAHH
Bus timing during no wait cycle time
16/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
External data memory control
(VDD = 4.5 to 5.5 V, Ta = -30 to +70C) Parameter Cycle time Clock pulse width (HIGH level) Clock pulse width (LOW level) ALE pulse width RD pulse width WR pulse width RD pulse delay time WR pulse delay time Low address setup time Low address hold time High address setup time High address hold time Read data setup time Read data hold time Write data setup time Write data hold time Symbol tcyc tWH tWL tAW tRW tWW tRAD tWAD tALS tALH tAHS tAHH tRS tRH tWS tWH tcyc CL = 50 pF Condition fOSC = 30 MHz Min. 33.3 13 13 2 t - 10 2 t - 15 2 t - 15 t - 3 t - 3 2 t - 15 t - 3 3 t - 25 t - 3 25 0 2t - 30 t - 3 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- t - 3 -- -- ns Unit
Note: t = tcyc/2
CPUCLK tWH ALE RD tRAD AD0 to AD7 tALS A8 to A19 tAHS WR tWAD AD0 to AD7 tALS A8 to A19 tAHS
RAP0 to 7 RAP0 to 7
tWL tAW
tRW
A
DIN0 to 7
tALH
RAP8 to 19
tRS
tRH
tAHH
tWW
DOUT0 to 7
tALH
RAP8 to 19
tWS
tWH
tAHH
Bus timing during no wait cycle time
17/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
(3) Serial port control Serial ports 1 and 6 (SIO1 and 6) Master mode (Clock synchronous serial port)
(VDD = 4.5 to 5.5 V, Ta = -30 to +70C) Parameter Cycle time Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tcyc tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL = 50 pF Condition fOSC = 30 MHz Min. 33.3 4 tcyc 2 t - 5 5 t - 10 13 0 Max. -- -- -- -- -- -- ns Unit
Note: t = tcyc/2
tcyc CPUCLK
TXC/RXC tSCKC SDOUT (TXD) tSTMXH SDIN (RXD) tSRMXS tSRMXH tSTMXS
18/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
Slave mode (Clock synchronous serial port)
(VDD = 4.5 to 5.5 V, Ta = -30 to +70C) Parameter Cycle time Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tcyc tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL = 50 pF Condition fOSC = 30 MHz Min. 33.3 4 tcyc 2 t - 15 4 t - 10 13 3 Max. -- -- -- -- -- -- ns Unit
Note: t = tcyc/2
tcyc CPUCLK
TXC/RXC tSCKC SDOUT (TXD) tSTMXH SDIN (RXD) tSRMXS tSRMXH tSTMXS
19/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
Serial ports 4 and 5 (SIO4 and 5) Master mode (Clock synchronous serial port)
(VDD = 4.5 to 5.5 V, Ta = -30 to +70C) Parameter Cycle time Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tcyc tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL = 50 pF Condition fOSC = 30 MHz Min. 33.3 6 tcyc 6 t - 5 4.5 t - 10 13 0 Max. -- -- -- -- -- -- ns Unit
Note: t = tcyc/2
tcyc CPUCLK
SIOCK tSCKC SDOUT (SIOO) tSTMXH SDIN (SIOI) tSRMXS tSRMXH tSTMXS
20/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
Slave mode (Clock synchronous serial port)
(VDD = 4.5 to 5.5 V, Ta = -30 to +70C) Parameter Cycle time Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tcyc tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL = 50 pF Condition fOSC = 30 MHz Min. 33.3 6 tcyc 3 t - 15 6 t - 10 13 3 Max. -- -- -- -- -- -- ns Unit
Note: t = tcyc/2
tcyc CPUCLK
SIOCK tSCKC SDOUT (SIOO) tSTMXH SDIN (SIOI) tSRMXS tSRMXH tSTMXS
Measurement points for AC timing (except the serial port)
VDD 0V 2.0 V 0.8 V 2.0 V 0.8 V
Measurement points for AC timing (the serial port)
VDD 0V 0.8VDD 0.2VDD 0.8VDD 0.2VDD
21/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
AC Characteristics 2 (VDD = 2.4 to 3.6 V) (1) Separate Bus Type External program memory control
MSM66577L (VDD = 2.4 to 3.6 V, Ta = -30 to +70C) MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = -30 to +70C) Parameter Cycle time Clock pulse width (HIGH level) Clock pulse width (LOW level) PSEN pulse width PSEN pulse delay time Address setup time Address hold time Instruction setup time Instruction hold time Read data access time Symbol tcyc tWH tWL tPW tPD tAS tAH tIS tIH tACC CL = 50 pF Condition fOSC = 14 MHz Min. 71.4 28 28 2 t - 40 -- t - 45 0 75 0 -- Max. -- -- -- -- 95 -- -- -- -- 3 t - 120 ns Unit
Note: t = tcyc/2
tcyc
CPUCLK
tWH PSEN
tWL
tPD
tPW
A0 to A19 tAS D0 to D7 tACC
PC0 to 19 tAH
INST0 to 7 tIS tIH
Bus timing during no wait cycle time
22/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
External data memory control
MSM66577L (VDD = 2.4 to 3.6 V, Ta = -30 to +70C) MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = -30 to +70C) Parameter Cycle time Clock pulse width (HIGH level) Clock pulse width (LOW level) RD pulse width WR pulse width RD pulse delay time WR pulse delay time Address setup time Address hold time Read data setup time Read data hold time Read data access time Write data setup time Write data hold time Symbol tcyc tWH tWL tRW tWW tRD tWD tAS tAH tRS tRH tACC tWS tWH tcyc CL = 50 pF Condition fOSC = 14 MHz Min. 71.4 28 28 2 t - 40 2 t - 40 -- -- t - 45 t - 6 75 0 -- 2t - 55 t - 6 Max. -- -- -- -- -- 95 95 -- -- -- -- 3t -120 -- -- ns Unit
Note: t = tcyc/2
CPUCLK tWH RD tWL
tRD A0 to A19 tAS D0 to D7 tACC WR tWD A0 to A19 tAS D0 to D7 RAP0 to 19 RAP0 to 19
tRW
tAH DIN0 to 7 tRS tRH
tWW
tAH DOUT0 to 7 tWS tWH
Bus timing during no wait cycle time
23/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
(2) Multiplexed bus type External program memory control
MSM66577L (VDD = 2.4 to 3.6 V, Ta = -30 to +70C) MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = -30 to +70C) Parameter Cycle time Clock pulse width (HIGH level) Clock pulse width (LOW level) ALE pulse width PSEN pulse width PSEN pulse delay time Low address setup time Low address hold time High address setup time High address hold time Instruction setup time Instruction hold time Symbol tcyc tWH tWL tAW tPW tPAD tALS tALH tAHS tAHH tIS tIH CL = 50 pF Condition fOSC = 14 MHz Min. 71.4 28 28 2 t - 15 2 t - 40 t - 6 2t - 25 t - 6 3t - 45 0 75 0 Max. -- -- -- -- -- -- -- -- -- -- -- t - 6 ns Unit
Note: t = tcyc/2
tcyc
CPUCLK tWH tAW tWL
ALE PSEN
tPAD AD0 to AD7 tALS A8 to A19 tAHS PC0 to 7 tALH PC8 to 19
tPW INST0 to 7 tIS tIH
tAHH
Bus timing during no wait cycle time
24/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
External data memory control
MSM66577L (VDD = 2.4 to 3.6 V, Ta = -30 to +70C) MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = -30 to +70C) Parameter Cycle time Clock pulse width (HIGH level) Clock pulse width (LOW level) ALE pulse width RD pulse width WR pulse width RD pulse delay time WR pulse delay time Low address setup time Low address hold time High address setup time High address hold time Read data setup time Read data hold time Write data setup time Write data hold time Symbol tcyc tWH tWL tAW tRW tWW tRAD tWAD tALS tALH tAHS tAHH tRS tRH tWS tWH tcyc CL = 50 pF Condition fOSC = 14 MHz Min. 71.4 28 28 2 t - 15 2 t - 40 2 t - 40 t - 6 t - 6 2 t - 25 t - 6 3 t - 45 t - 6 75 0 2t - 55 t - 6 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- t - 6 -- -- ns Unit
Note: t = tcyc/2
CPUCLK tWH ALE RD tRAD AD0 to AD7 tALS A8 to A19 tAHS WR tWAD AD0 to AD7 tALS A8 to A19 tAHS
RAP0 to 7 RAP0 to 7
tWL tAW
tRW
A
DIN0 to 7
tALH
RAP8 to 19
tRS
tRH
tAHH
tWW
DOUT0 to 7
tALH
RAP8 to 19
tWS
tWH
tAHH
Bus timing during no wait cycle time
25/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
(3) Serial port control Serial ports 1 and 6 (SIO1 and 6) Master mode (Clock synchronous serial port)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = -30 to +70C) MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = -30 to +70C) Parameter Cycle time Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tcyc tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL = 50 pF Condition fOSC = 14 MHz Min. 71.4 4 tcyc 2 t - 10 5 t - 20 21 0 Max. -- -- -- -- -- -- ns Unit
Note: t = tcyc/2
tcyc CPUCLK
TXC/RXC tSCKC SDOUT (TXD) tSTMXH SDIN (RXD) tSRMXS tSRMXH tSTMXS
26/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
Slave mode (Clock synchronous serial port)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = -30 to +70C) MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = -30 to +70C) Parameter Cycle time Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tcyc tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL = 50 pF Condition fOSC = 14 MHz Min. 71.4 4 tcyc 2 t - 30 4 t - 20 21 7 Max. -- -- -- -- -- -- ns Unit
Note: t = tcyc/2
tcyc CPUCLK
TXC/RXC tSCKC SDOUT (TXD) tSTMXH SDIN (RXD) tSRMXS tSRMXH tSTMXS
27/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
Serial ports 4 and 5 (SIO4 and 5) Master mode (Clock synchronous serial port)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = -30 to +70C) MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = -30 to +70C) Parameter Cycle time Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tcyc tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL = 50 pF Condition fOSC = 14 MHz Min. 71.4 5.6 tcyc 5.6 t - 10 4.2 t - 20 21 0 Max. -- -- -- -- -- -- ns Unit
Note: t = tcyc/2
tcyc CPUCLK
SIOCK tSCKC SDOUT (SIOO) tSTMXH SDIN (SIOI) tSRMXS tSRMXH tSTMXS
28/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
Slave mode (Clock synchronous serial port)
MSM66577L (VDD = 2.4 to 3.6 V, Ta = -30 to +70C) MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = -30 to +70C) Parameter Cycle time Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tcyc tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL = 50 pF Condition fOSC = 14 MHz Min. 71.4 5.6 tcyc 2.8 t - 30 5.6 t - 20 21 7 Max. -- -- -- -- -- -- ns Unit
Note: t = tcyc/2
tcyc CPUCLK
SIOCK tSCKC SDOUT (SIOO) tSTMXH SDIN (SIOI) tSRMXS tSRMXH tSTMXS
Measurement points for AC timing (except the serial port)
VDD 0V 0.44VDD 0.16VDD 0.44VDD 0.16VDD
Measurement points for AC timing (the serial port)
VDD 0V 0.8VDD 0.2VDD 0.8VDD 0.2VDD
29/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
A/D Converter Characteristics 1 (VDD = 4.5 to 5.5 V)
(Ta = -30 to 70C, VDD = VREF = 4.5 to 5.5 V, AGND = GND = 0 V) Parameter Resolution Linearity error Differential linearity error Zero scale error Full-scale error Cross talk Conversion time Symbol n EL ED EZS EFS ECT tCONV Condition Refer to measurement circuit 1 Analog input source impedance RI 5 k tconv = 10.7 s Refer to measurement circuit 2 Set according to ADTM set data Min. -- -- -- -- -- -- 10.7 Typ. 10 -- -- -- -- -- -- Max. -- 3 2 +3 LSB -3 1 -- s/ch Unit Bit
A/D Converter Characteristics 2 (VDD = 2.4 to 3.6 V)
MSM66577L (Ta = -30 to 70C, VDD = VREF = 2.4 to 3.6 V, AGND = GND = 0 V) MSM66Q577LY (Ta = -30 to 70C, VDD = VREF = 3.0 to 3.6 V, AGND = GND = 0 V) Parameter Resolution Linearity error Differential linearity error Zero scale error Full-scale error Cross talk Conversion time Symbol n EL ED EZS EFS ECT tCONV Condition Refer to measurement circuit 1 Analog input source impedance RI 5 k tconv = 10.7 s Refer to measurement circuit 2 Set according to ADTM set data Min. -- -- -- -- -- -- 27.4 Typ. 10 -- -- -- -- -- -- Max. -- 4 3 +4 LSB -4 2 -- s/ch Unit Bit
Reference voltage 0.1 F
- +
VREF 47 F +
VDD + 0.1 F GND
+5 V / +3V
RI AI0 to AI7 AGND CI
47 F 0V
Analog input
RI (impedance of analog input source) 5 k CI 0.1 F
Measurement Circuit 1
30/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
- + Analog input
5 k AI0 AI1 0.1 F to
Cross talk is the difference between the A/D conversion results when the same analog input is applied to AI0 through AI7 and the A/D conversion results of the circuit to the left.
AI7
VREF or AGND
Measurement Circuit 2
Definition of Terminology 1. Resolution Resolution is the value of minimum discernible analog input. With 10 bits, since 210 = 1024, resolution of (VREF - AGND) / 1024 is possible. 2. Linearity error Linearity error is the difference between ideal conversion characteristics and actual conversion characteristics of a 10-bit A/D converter (not including quantization error). Ideal conversion characteristics can be obtained by dividing the voltage between VREF and AGND into 1024 equal steps. 3. Differential linearity error Differential linearity error indicates the smoothness of conversion characteristics. Ideally, the range of analog input voltage that corresponds to 1 converted bit of digital output is 1LSB = (VREF - AGND) / 1024. Differential error is the difference between this ideal bit size and bit size of an arbitrary point in the conversion range. 4. Zero scale error Zero scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the point where the digital output changes from 000H to 001H. 5. Full-scale error Full-scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the point where the digital output changes from 3FEH to 3FFH.
31/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
D/A Converter Characteristics
MSM66577/Q577 (VDD = 4.5 to 5.5 V, Ta = -30 to +70C) MSM66577L (VDD = 2.4 to 3.6 V, Ta = -30 to +70C) MSM66Q577LY (VDD = 3.0 to 3.6 V, Ta = -30 to +70C) Parameter Resolution Linearity error Absolute precision Conversion time Analog output impedance Symbol n EL -- tCONV -- CL = 50 pF -- -- Condition Min. -- -- -- -- -- Typ. -- -- -- 20 20 Max. 8 1 2 50 -- Unit Bit LSB s k
Definition of Terminology 1. Resolution Resolution is the value of minimum discernible analog output. With 8 bits, since 28 = 256, resolution of (VDD - GND) / 256 is possible. 2. Linearity error Linearity error is the difference between ideal conversion characteristics and actual conversion characteristics of an 8-bit D/A converter. Ideal conversion characteristics can be obtained by dividing the voltage between VDD and GND into 256 equal steps. 3. Differential linearity error Differential linearity error indicates the smoothness of conversion characteristics. Ideally, the range of analog input voltage that corresponds to 1 converted bit of digital input is 1LSB = (VDD - GND) / 256. Differential error is the difference between this ideal bit size and bit size of an arbitrary point in the conversion range. 4. Absolute precision Absolute precision is a gross error including a linearity error and the effect of noise.
32/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
PACKAGE DIMENSIONS
(Unit: mm)
TQFP100-P-1414-0.50-K
Mirror finish
5
Notes for Mounting the Surface Mount Type Packages
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.55 TYP. 4/Oct. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
33/34
PEDL66577-01
Semiconductor 1
MSM66577 Family
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2000 Oki Electric Industry Co., Ltd.
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