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E2L0013-17-Y1 Semiconductor
Semiconductor MSM514262
262,144-Word 4-Bit Multiport DRAM
This version: Jan. 1998 MSM514262 Previous version: Dec. 1996
DESCRIPTION
The MSM514262 is an 1-Mbit CMOS multiport DRAM composed of a 262,144-word by 4-bit dynamic RAM and a 512-word by 4-bit SAM. Its RAM and SAM operate independently and asynchronously. The MSM514262 supports three types of operation : random access to RAM port, high speed serial access to SAM port and bidirectional transfer of data between any selected row in the RAM port and the SAM port. In addition to the conventional multiport DRAM operating modes, the MSM514262 features the block write and flash write functions on the RAM port and a split data transfer capability on the SAM port. The SAM port requires no refresh operation because it uses static CMOS flip-flops.
FEATURES
* Single power supply: 5 V 10% * Full TTL compatibility * Multiport organization RAM: 256K word 4 bits SAM: 512 word 4 bits * Fast page mode * Write per bit * Masked flash write * Masked block write * RAS only refresh * CAS before RAS refresh * Hidden refresh * Serial read/write * 512 tap location * Bidirectional data transfer * Split transfer * Masked write transfer * Refresh: 512 cycles/8 ms * Package options: 28-pin 400 mil plastic ZIP (ZIP28-P-400-1.27) 28-pin 400 mil plastic SOJ (SOJ28-P-400-1.27)
(Product : MSM514262-xxZS) (Product : MSM514262-xxJS) xx indicates speed rank.
PRODUCT FAMILY
Family MSM514262-70 MSM514262-80 MSM514262-10 Access Time RAM 70 ns 80 ns 100 ns SAM 25 ns 25 ns 25 ns Cycle Time RAM 140 ns 150 ns 180 ns SAM 30 ns 30 ns 30 ns Power Dissipation Operating 120 mA 110 mA 100 mA Standby 8 mA 8 mA 8 mA
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Semiconductor
PIN CONFIGURATION (TOP VIEW)
DSF W4/IO4 SIO3 VSS SIO1
1 3 5 7 9
2 4 6 8
W3/IO3 SE SIO4 SC
10 SIO2
DT/OE 11 W2/IO2 13 NC 15 A8 17 A5 19 VCC 21 A3 23 A1 25 QSF 27
12 W1/IO1
14 WB/WE 16 RAS 18 A6 20 A4 22 A7 24 A2 26 A0 28 CAS
SC 1 28 VSS SIO1 2 27 SIO4 SIO2 3 26 SIO3 25 SE DT/OE 4 W1/IO1 5 W2/IO2 6 WB/WE 7 NC 8 RAS 9 24 W4/IO4 23 W3/IO3 22 DSF 20 QSF 19 A0 18 A1 17 A2 16 A3 15 A7 21 CAS A8 10 A6 11 A5 12 A4 13 VCC 14 28-Pin Plastic SOJ
MSM514262
28-Pin Plastic ZIP
Pin Name A0 - A8 RAS CAS DT/OE WB/WE DSF W1/IO1 - W4/IO4 SC SE SIO1 - SIO4 QSF VCC VSS NC
Function Address Input Row Address Strobe Column Address Strobe Transfer/Output Enable Mask/Write Enable Special Function Input RAM Inputs/Outputs Serial Clock SAM Port Enable SAM Inputs/Ourputs Special Function Output Power Supply (5 V) Ground (0 V) No Connection
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Semiconductor
BLOCK DIAGRAM
Column Address Buffer
Column Decoder Sense Amp.
Block Write Control I/O Control
Column Mask Register Color Register Mask Register RAM Input Buffer W1/IO1 - W4/IO4 RAM Output Buffer
Row Decoder
Row Address Buffer A0 - A8 Refresh Counter
512 512 4 RAM ARRAY
Flash Write Control SAM Input Buffer SAM Output Buffer
Gate SAM
Gate SAM
SIO1 - SIO4 Timing Generator
RAS CAS DT/OE WB/WE DSF SC SE VCC VSS
Serial Decoder SAM Address Buffer SAM Address Counter
QSF
MSM514262
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Semiconductor
MSM514262
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Input Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD Topr Tstg Condition Ta = 25C Ta = 25C Ta = 25C -- -- Rating -1.0 to 7.0 50 1 0 to 70 -55 to 150 (Note: 16) Unit V mA W C C
Recommended Operating Condition
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min. 4.5 2.4 -1.0 Typ. 5.0 -- --
(Ta = 0C to 70C) (Note: 17) Max. 5.5 6.5 0.8 Unit V V V
Capacitance
Parameter Input Capacitance Input/Output Capacitance Output Capacitance Symbol CI CI/O CO(QSF) Min. -- -- --
(VCC = 5 V 10%, f = 1 MHz, Ta = 25C) Max. 7 9 9 Unit pF pF pF
Note:
This parameter is periodically sampled and is not 100% tested.
DC Characteristics 1
Parameter Output "H" Level Voltage Output "L" Level Voltage Input Leakage Current Symbol VOH VOL ILI Condition IOH = -2 mA IOL = 2 mA 0 VIN VCC All other pins not under test = 0 V Output Leakage Current ILO 0 VOUT 5.5 V Output Disable -10 10 -10 10 mA Min. 2.4 -- Max. -- 0.4 Unit V
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Semiconductor DC Characteristics 2
Item (RAM) Operating Current (RAS, CAS Cycling, tRC = tRC min.) Standby Current (RAS, CAS = VIH) RAS Only Refresh Current (RAS Cycling, CAS = VIH, tRC = tRC min.) Page Mode Current (RAS = VIL, CAS Cycling, tPC = tPC min.) CAS before RAS Refresh Current (RAS Cycling, CAS before RAS, tRC = tRC min.) Data Transfer Current (RAS, CAS Cycling, tRC = tRC min.) Flash Write Current (RAS, CAS Cycling, tRC = tRC min.) Block Write Current (RAS, CAS Cycling, tRC = tRC min.) SAM Standby Active Standby Active Standby Active Standby Active Standby Active Standby Active Standby Active Standby Active Symbol ICC1 ICC1A ICC2 ICC2A ICC3 ICC3A ICC4 ICC4A ICC5 ICC5A ICC6 ICC6A ICC7 ICC7A ICC8 ICC8A
MSM514262
(VCC = 5 V 10%, Ta = 0C to 70C) -70 85 120 8 50 85 120 70 120 85 120 85 120 85 120 85 120 -80 75 110 8 45 75 110 65 110 75 110 75 110 75 110 75 110 -10 65 100 8 40 65 100 60 100 65 100 65 100 65 100 65 100 mA Max. Max. Max. Unit Note 1, 2 1, 2 3 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2
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Semiconductor AC Characteristics (1/3)
Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from Column Address Access Time from CAS Access Time from CAS Precharge Output Buffer Turn-off Delay Transition Time (Rise and Fall) RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode Only) RAS Hold Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Time RAS to Column Address Delay Time Column Address to RAS Lead Time CAS to RAS Precharge Time CAS Precharge Time CAS Precharge Time (Fast Page Mode) Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time referenced to RAS Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Hold Time Write Command Hold Time referenced to RAS Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Symbol tRC tRWC tPC tPRWC tRAC tAA tCAC tCPA tOFF tT tRP tRAS tRASP tRSH tCSH tCAS tRCD tRAD tRAL tCRP tCPN tCP tASR tRAH tASC tCAH tAR tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL
MSM514262
(VCC = 5 V 10%, Ta = 0C to 70C) Note 4, 5, 6 -70 140 195 45 90 -- -- -- -- 0 3 60 70 70 20 70 20 20 15 35 10 10 10 0 10 0 15 55 0 0 0 15 55 15 20 20 -- -- -- -- 70 35 20 40 20 35 -- 10k 100k -- -- 10k 50 35 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -80 150 195 50 90 -- -- -- -- 0 3 60 80 80 25 80 25 20 15 40 10 10 10 0 10 0 15 55 0 0 0 15 55 15 20 20 -- -- -- -- 80 40 25 45 20 35 -- 10k -- -- 10k 55 40 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -10 180 235 55 100 -- -- -- -- 0 3 70 100 25 100 25 20 20 55 10 10 10 0 10 0 15 70 0 0 0 15 70 15 25 25 -- -- -- -- 100 55 25 50 20 35 -- 10k -- -- 10k 75 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. Max. Min. Max. Min. Max. Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 13 13 7, 13 7, 13 7, 14 7, 14 9 6
100k 100 100k
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Semiconductor AC Characteristics (2/3)
Parameter Data Set-up Time Data Hold Time Data Hold Time referenced to RAS Write Command Set-up Time RAS to WE Delay Time Column Address to WE Delay Time CAS to WE Delay Time Data to CAS Delay Time Data to OE Delay Time Access Time from OE Output Buffer Turn-off Delay from OE OE to Data Delay Time OE Command Hold Time RAS Hold Time referenced to OE CAS Set-up Time for CAS before RAS Cycle CAS Hold Time for CAS before RAS Cycle RAS Precharge to CAS Active Time Refresh Period WB Set-up Time WB Hold Time DSF Set-up Time referenced to RAS DSF Hold Time referenced to RAS (1) DSF Hold Time referenced to RAS (2) DSF Set-up Time referenced to CAS DSF Hold Time referenced to CAS Write Per Bit Mask Data Set-up Time Write Per Bit Mask Data Hold Time DT High Set-up Time DT High Hold Time DT Low Set-up Time DT Low Hold Time DT Low Hold Time referenced to RAS (Real Time Read Transfer) DT Low Hold Time referenced to Column Address (Real Time Read Transfer) DT Low Hold Time referenced to CAS (Real Time Read Transfer) SE Set-up Time referenced to RAS SE Hold Time referenced to RAS Symbol tDS tDH tDHR tWCS tRWD tAWD tCWD tDZC tDZO tOEA tOEZ tOED tOEH tROH tCSR tCHR tRPC tREF tWSR tRWH tFSR tRFH tFHR tFSC tCFH tMS tMH tTHS tTHH tTLS tTLH tRTH tATH tCTH tESR tREH
MSM514262
(VCC = 5 V 10%, Ta = 0C to 70C) Note 4, 5, 6 -70 0 15 55 0 100 65 45 0 0 -- 0 10 10 15 10 10 0 -- 0 15 0 15 55 0 15 0 15 0 15 0 15 60 25 20 0 15 -- -- -- -- -- -- -- -- -- 20 10 -- -- -- -- -- -- 8 -- -- -- -- -- -- -- -- -- -- -- -- 10k 10k -- -- -- -- 0 15 55 0 100 65 45 0 0 -- 0 10 10 15 10 10 0 -- 0 15 0 15 55 0 15 0 15 0 15 0 15 65 30 25 0 15 -80 -- -- -- -- -- -- -- -- -- 20 10 -- -- -- -- -- -- 8 -- -- -- -- -- -- -- -- -- -- -- -- 10k 10k -- -- -- -- 0 15 70 0 130 80 55 0 0 -- 0 20 20 15 10 10 0 -- 0 15 0 15 70 0 15 0 15 0 15 0 15 80 30 25 0 15 -10 -- -- -- -- -- -- -- -- -- 25 20 -- -- -- -- -- -- 8 -- -- -- -- -- -- -- -- -- -- -- -- 10k 10k -- -- -- -- Min. Max. Min. Max. Min. Max. Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 9 12 12 12 12 11 11
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Semiconductor AC Characteristics (3/3)
Parameter DT to RAS Precharge Time DT Precharge Time RAS to First SC Delay Time (Read Transfer) Column Address to First SC Delay Time (Read Transfer) CAS to First SC Delay Time (Read Transfer) Last SC to DT Lead Time (Real Time Read Transfer) DT to First SC Delay Time (Read Transfer) Last SC to RAS Set-up Time (Serial Input) RAS to First SC Delay Time (Serial Input) RAS to Serial Input Delay Time Serial Output Buffer Turn-off Delay from RAS (Pseudo Write Transfer) SC Cycle Time SC Pulse Width (SC High Time) SC Precharge Time (SC Low Time) Access Time from SC Serial Output Hold Time from SC Serial Input Set-up Time Serial Input Hold Time Access Time from SE SE Pulse Width SE Precharge Time Serial Output Buffer Turn-off Delay from SE Serial Input to SE Delay Time Serial Input to First SC Delay Time Serial Write Enable Set-up Time Serial Write Enable Hold Time Serial Write Disable Set-up Time Serial Write Disable Hold Time Split Transfer Set-up Time Split Transfer Hold Time SC-QSF Delay Time DT-QSF Delay Time CAS-QSF Delay Time RAS-QSF Delay Time Symbol tTRP tTP tRSD tASD tCSD tTSL tTSD tSRS tSRD tSDD tSDZ tSCC tSC tSCP tSCA tSOH tSDS tSDH tSEA tSE tSEP tSEZ tSZE tSZS tSWS tSWH tSWIS tSWIH tSTS tSTH tSQD tTQD tCQD tRQD
MSM514262
(VCC = 5 V 10%, Ta = 0C to 70C) Note 4, 5, 6 -70 60 20 70 45 20 5 15 25 20 40 10 30 10 10 -- 5 0 15 -- 25 25 0 0 0 5 15 5 15 25 25 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40 -- -- -- 25 -- -- -- 25 -- -- 20 -- -- -- -- -- -- -- -- 25 25 35 75 60 20 80 45 25 5 15 25 20 40 10 30 10 10 -- 5 0 15 -- 25 25 0 0 0 5 15 5 15 30 30 -- -- -- -- -80 -- -- -- -- -- -- -- -- -- -- 40 -- -- -- 25 -- -- -- 25 -- -- 20 -- -- -- -- -- -- -- -- 25 25 35 75 70 30 100 50 25 5 15 30 25 50 10 30 10 10 -- 5 0 15 -- 25 25 0 0 0 5 15 5 15 30 30 -- -- -- -- -10 -- -- -- -- -- -- -- -- -- -- 50 -- -- -- 25 -- -- -- 25 -- -- 20 -- -- -- -- -- -- -- -- 25 25 35 85 Min. Max. Min. Max. Min. Max. Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 8 8 9
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Semiconductor Notes:
MSM514262
1. These parameters depend on output loading. Specified values are obtained with the output open. 2. These parameters are masured at minimum cycle test. 3. ICC2 (Max.) are mesured under the condition of TTL input level. 4. VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 5. An initial pause of 200 ms is required after power-up followed by any 8 RAS cycles (DT/OE "high") and any 8 SC cycles before proper divice operation is achieved. In the case of using an internal refresh counter, a minimum of 8 CAS before RAS initialization cycles in stead of 8 RAS cycles are required. 6. AC measurements assume tT = 5 ns. 7. RAM port outputs are mesured with a load equivalent to 1 TTL load and 100 pF. Output reference levels are VOH/VOL = 2.4 V/0.8 V. 8. SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF. Output reference levels are VOH/VOL = 2.0 V/0.8 V. 9. tOFF (Max.), tOEZ (Max.), tSDZ (Max.) and tSEZ (Max.) difine the time at which the outputs achieve the open circuit condition and are not reference to output voltage levels. 10. Either tRCH or tRRH must be satisfied for a read cycle. 11. These parameters are referenced to CAS leading edge of early write cycles and to WB/WE leading edge in OE controlled write cycles and read modify write cycles. 12. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), the cycle is an early write cycle, and the data out pin will remain open circuit (high impedance) throughout the entire cycle : If tRWD tRWD (Min.), tCWD tCWD (Min.) and tAWD tAWD (Min.) the cycle is a read-write cycle and the data out will contain data read from the selected cell : If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indterminate. 13. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only : If tRCD is greater than the specified tRCD (Max.) limit, then access time is controlled by tCAC. 14. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only : If tRAD is greater than the specified tRAD (Max.) limit, then access time is controlled by tAA. 15. Input levels at the AC parameter measurement are 3.0 V/0 V. 16. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permenent damege to the device. 17. All voltages are referenced to VSS.
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Semiconductor
MSM514262
TIMING WAVEFORM
Read Cycle
tRC tRAS RAS VIH - VIL - tCRP tRCD tAR tCSH tRP
, ,
tRSH tCPN CAS VIH - VIL - tCAS tRAD tRAL tASR tRAH tASC tCAH A0 - A8 VIH - VIL - Row Address Column Address tRCS tRCH tRRH WB/WE VIH - VIL - tTHS tTHH tROH DT/OE VIH - VIL - tFSR tRFH tFHR tFSC tCFH DSF VIH - VIL - tDZO tOEA IN VIH - VIL - tCAC tOFF W1/IO1 W4/IO4 OUT tAA tRAC tOEZ VOH - VOL - Open Valid Data-out "H" or "L"
10/45
Semiconductor Write Cycle (Early Write)
tRC tRAS RAS VIH - VIL - tCRP tRCD tAR tCSH tRP
MSM514262
,, ,
tRSH tCPN CAS VIH - VIL - tCAS tASR tRAD tRAH tRAL tASC tCAH A0 - A8 VIH - VIL - Row Address tWSR Column Address tWCH tRWH tWCS WB/WE VIH - VIL - *1 tWP tWCR tTHS tTHH tCWL tRWL DT/OE VIH - VIL - tFSR tRFH tFHR tFSC tCFH DSF VIH - VIL - tMS tMH tDS tDH IN VIH - VIL - WM1 Data Valid Data-in W1/IO1 W4/IO4 OUT tDHR VOH - VOL - Open "H" or "L"
*1 WB/WE 0 1
W1/IO1 - W4/IO4 WM1 data Don't Care
Cycle
Write per Bit
Normal Write
WM1 data:
0: Write Disable 1: Write Enable
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Semiconductor Write Cycle (OE Controlled Write)
tRC tRAS RAS VIH - VIL - tCRP tRCD tAR tCSH tRP
MSM514262
, ,
tRSH tCPN CAS VIH - VIL - tCAS tASR tRAD tRAH tASC tRAL tCAH A0 - A8 VIH - VIL - Row Address tWSR tRWH Column Address tCWL tWP tRWL WB/WE VIH - VIL - *1 tWCR tTHS tOEH DT/OE VIH - VIL - tFHR tFSR tRFH tFSC tCFH DSF VIH - VIL - tMS tMH tDS tDH IN VIH - VIL - WM1 Data Valid Data-in W1/IO1 W4/IO4 OUT tDHR VOH- VOL - Open "H" or "L"
*1 WB/WE 0 1
W1/IO1 - W4/IO4 WM1 data Don't Care
Cycle
Write per Bit
Normal Write
WM1 data:
0: Write Disable 1: Write Enable
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Semiconductor Read Modify Write Cycle
tRWC tRAS RAS VIH - VIL - tCRP tRCD tAR tCSH
MSM514262
tRP
, , ,
tRSH tCAS tCPN CAS VIH - VIL - tRAD tASR tRAH tASC tCAH A0 - A8 VIH - VIL - Row Address tWSR tRWH Column Address tCWL tWP tRCS tCWD tRWL WB/WE VIH - VIL - *1 tAWD tRWD tTHS tTHH tOEH DT/OE VIH - VIL - tFHR tFSR tRFH tFSC tCFH DSF VIH - VIL - tMS tMH tDZC tDZO tDS tOED tDH IN VIH - VIL - WM1 Data tOEA Valid Data-in W1/IO1 W4/IO4 OUT tRAC tAA tCAC tOEZ VOH- VOL - Open Valid Data-out "H" or "L"
*1 WB/WE 0 1
W1/IO1 - W4/IO4 WM1 data Don't Care
Cycle
Write per Bit
Normal Write
WM1 data:
0: Write Disable 1: Write Enable
13/45
Semiconductor Fast Page Mode Read Cycle
tRASP RAS VIH - VIL - tCRP tAR tPC tRSH
MSM514262
tRP
, ,, ,
tRCD tCP tCP tCAS tCPN CAS VIH - VIL - tASR tRAD tCSH tRAH tASC tCAS tCAS tCAH tASC tCAH tRAL tASC tCAH A0 - A8 VIH - VIL -
Row Address Column Address 1 Column Address 2 Column Address n
tRCH
tRCS
tRCH
tRCH
tRCS
tRCS
tRRH
WB/WE
VIH - VIL -
tTHS
tTHH
DT/OE
VIH - VIL -
tFSC
tFSR
tFSC
tFSC
DSF
VIH - VIL -
tRFH
tCFH
tCFH
tCFH
tFHR
tDZO
IN
VIH - VIL -
tCPA
tCPA
tOEA
W1/IO1 W4/IO4
tCAC
tOFF
tOEA
tOFF
tOEA
OUT
VOH - VOL -
tRAC
tAA
tOEZ
tCAC
tAA
tOEZ
tCAC
tOFF
tAA
tOEZ
Open
Data-out 1
Data-out 2
Data-out n
"H" or "L"
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Semiconductor Fast Page Mode Write Cycle (Early Write)
tRASP RAS VIH - VIL - tCRP tRCD tAR tPC tRSH
MSM514262
tRP
,,, ,
tCAS tCPN CAS VIH - VIL - tASR tRAD tCSH tRAH tASC tCAS tCAS tCAH tASC tCAH tRAL tASC tCAH A0 - A8 VIH - VIL -
Row Address Column Address 1 Column Address 2 Column Address n
tCP
tCP
tWCR
tWSR
tRWH
tWCH
tWCH
tWCS
tWCH
tWCS
tWCS
WB/WE
VIH - VIL -
*1
tWP
tWP
tWP
tCWL
tCWL
tTHS
tTHH
tCWL tRWL
DT/OE
VIH - VIL -
tFHR
DSF
VIH - VIL -
tRFH tFSR
tCFH
tFSC
tFSC
tFSC
tCFH
tCFH
tMH
tMS
tDS
tDH
tDH
tDH
tDS
tDS
IN
VIH - VIL -
WM1 Data
Data-in 1
Data-in 2
Data-in n
W1/IO1 W4/IO4
tDHR
OUT
VOH - VOL -
Open
"H" or "L"
*1 WB/WE 0 1
W1/IO1 - W4/IO4 WM1 data Don't Care
Cycle
Write per Bit
Normal Write
WM1 data:
0: Write Disable 1: Write Enable
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Semiconductor Fast Page Mode Read Modify Write Cycle
tRASP tAR RAS VIH - VIL - tRCD tCSH tPRWC tRSH
MSM514262
tRP
, ,
tCP tCP CAS VIH - VIL - tCAS tCAS tCAS tASC tASR tRAH
Row Address
tCAH
tASC
tASC
tCWL
tCWL
tCAH
tCWL
tCAH
tRWL
A0 - A8
VIH - VIL -
Column Address 1
Column Address 2
Column Address n
tWSR
tRWH
tWP
tWP
tWP
WB/WE
VIH - VIL -
*1
tCWD
tCWD
tCWD
tRWD
tTHS
tTHH
DT/OE
VIH - VIL -
tRFH
tFSR
tFHR tFSC
tFSC
tFSC
DSF
VIH - VIL -
tCFH
tCFH
tCFH
tMH
tDZO
tDS
tDZO
tDS
tMS
tDZC
tOED
tDH
tDZC
tOED
tDZO
tDS
tDH
tDZC
tOED
tDH
IN
VIH - VIL -
WM1 Data
tOEA
Datain 1
tOEA
Datain 2
tOEA
Datain n
W1/IO1 W4/IO4 OUT
tCAC
tOEZ
tCAC
tOEZ
tAA
tAA
tCAC tAA
tOEZ
VOH - VOL -
tRAC
Dataout 1
Dataout 2
Dataout n
"H" or "L"
*1 WB/WE 0 1
W1/IO1 - W4/IO4 WM1 data Don't Care
Cycle
Write per Bit
Normal Write
WM1 data:
0: Write Disable 1: Write Enable
16/45
Semiconductor RAS Only Refresh Cycle
tRC tRAS RAS VIH - VIL - tRP
MSM514262
,,, ,, ,
tCRP tRPC tCRP CAS VIH - VIL - tASR tRAH A0 - A8 VIH - VIL - Row Address WB/WE VIH - VIL - tTHS tTHH DT/OE VIH - VIL - tFSR tRFH DSF VIH - VIL - W1/IO1 W4/IO4 VOH- VOL - Open "H" or "L"
17/45
Semiconductor CAS before RAS Refresh Cycle
MSM514262
,,,
tRP tRP RAS VIH - VIL - tRAS tRPC tCSR tCPN tCHR CAS VIH - VIL - WB/WE VIH - VIL - DT/OE VIH - VIL - DSF VIH - VIL - tOFF W1/IO1 W4/IO4 VOH- VOL - Open Note: A0 - A8 = Don't care ("H" or "L") "H" or "L"
tRC
18/45
Semiconductor Hidden Refresh Cycle
tRC tRAS RAS VIH - VIL - tAR tRP tRAS tRC
MSM514262
tRP
,, , ,
tCRP tRCD tRSH tCHR tCPN CAS VIH - VIL - tASR tRAD tRAH tASC tRAL tCAH A0 - A8 VIH - VIL - Row Address Column Address tWSR tRCS tRRH tRWH WB/WE VIH - VIL - tTHS tTHH tROH DT/OE VIH - VIL - tFSR tRFH tFSC tCFH tFHR DSF VIH - VIL - tOEZ tOFF tAA tOEA tCAC tOFF tOEZ W1/IO1 W4/IO4 VOH- VOL - Valid Data-out "H" or "L"
19/45
Semiconductor Load Color Register Cycle
tRC tRAS RAS VIH - VIL - tCHR tCRP tRCD tRSH tRP
MSM514262
, ,
tCPN CAS VIH - VIL - tCAS tASR tRAH A0 - A8 VIH - VIL - Row Address tWSR tCWL tWP tRWH tRWL WB/WE VIH - VIL - tWCR tTHS tWCH tOEH DT/OE VIH - VIL - tFSR tRFH DSF VIH - VIL - tDHR tDS tDH IN VIH - VIL - Color Data-in W1/IO1 W4/IO4 tDS tDH (Delayed Write) OUT VOH - VOL - Color Data-in (Early Write) "H" or "L"
20/45
Semiconductor Read Color Register Cycle
tRC tRAS RAS VIH - VIL - tCSH tCRP tRCD tRSH tRP
MSM514262
CAS
VIH - VIL -
A0 - A8
VIH - VIL -
DT/OE
VIH - VIL -
WB/WE
VIH - VIL -
DSF
VIH - VIL -
W1/IO1 W4/IO4
VOH- VOL -
, , ,
tCAS tASR tRAH Row Address tTHS tTHH tROH tRRH tWSR tRWH tRCS tRCH tFSR tRFH tOEA tCAC tOFF tOEZ Valid Data-out tRAC "H" or "L"
tCPN
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Semiconductor Flash Write Cycle
tRC tRAS RAS VIH - VIL - tCSH tCRP tRCD tRSH tRP
MSM514262
,, ,
tCPN CAS VIH - VIL - tCAS tASR tRAH A0 - A8 VIH - VIL - Row Address WB/WE VIH - VIL - tWSR tRWH tTLS tTLH DT/OE VIH - VIL - tFSR tRFH DSF VIH - VIL - tMS tMH IN VIH - VIL - WM1 Data W1/IO1 W4/IO4 OUT VOH - VOL - Open "H" or "L"
WM1 Data 0 1 Cycle Flash Write Disable Flash Write Enable
22/45
Semiconductor Block Write Cycle
tRC tRAS RAS VIH - VIL - tCRP tRCD tAR tCSH
MSM514262
tRP
,, ,
tRSH tCPN CAS VIH - VIL - tCAS tRAD tASR tRAH tASC tRAL tCAH A0 - A8 VIH - VIL - Row Address Column Address (A2C~A8C) tWSR tRWH WB/WE VIH - VIL - *1 tTHS tTHH DT/OE VIH - VIL - tFHR tFSR tRFH tFSC tCFH DSF VIH - VIL - tMS tMH tDS tDH IN VIH - VIL - *2 *3 W1/IO1 W4/IO4 tDHR OUT VOH - VOL - Open "H" or "L"
*1 WB/WE 0 1 *2 W1/IO1 - W4/IO4 WM1 data Don't Care Cycle Masked Block Write Block Write (Non Mask) WM1 data: 0: Write Disable 1: Write Enable *3) COLUMN SELECT W1/IO1 - Column 0 (A1C = 0, A0C = 0) W2/IO2 - Column 1 (A1C = 0, A0C = 1) W3/IO3 - Column 2 (A1C = 1, A0C = 0) W4/IO4 - Column 3 (A1C = 1, A0C = 1) Wn/On = 0 : Disable = 1 : Enable
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Semiconductor Fast Page Mode Block Write Cycle
tRASP RAS VIH - VIL - tAR tCSH tPC tPC
MSM514262
tRP
,,, ,,, ,
tRSH tCRP tRCD tCP tCP tCAS tCPN CAS VIH - VIL - tRAD tCAS tCAS tRAH tASR tASC tCAH tASC tCAH tASC tRAL tCAH A0 - A8 VIH - VIL - Row Address A2C A8C A2C A8C A2C A8C tTHS tTHH DT/OE VIH - VIL - tWSR tRWH WB/WE VIH - VIL - *1 tFSR tFHR tRFH t FSC tCFH tCFH tCFH tFSC tFSC DSF VIH - VIL - tDHR tMH tMS tDS tDH tDH tDH tDS tDS W1/IO1 W4/IO4 VOH - VOL - *2 *3 *3 *3 "H" or "L"
*1 WB/WE 0 1 *2 W1/IO1 - W4/IO4 WM1 data Don't Care Cycle Masked Block Write Block Write (Non Mask) WM1 data: 0: Write Disable 1: Write Enable *3) COLUMN SELECT W1/IO1 - Column 0 (A1C = 0, A0C = 0) W2/IO2 - Column 1 (A1C = 0, A0C = 1) W3/IO3 - Column 2 (A1C = 1, A0C = 0) W4/IO4 - Column 3 (A1C = 1, A0C = 1) Wn/On = 0 : Disable = 1 : Enable
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, ,,
Semiconductor MSM514262 Read Transfer Cycle (Previous Transfer is Write Transfer Cycle)
tRC tRAS tRP RAS VIH - VIL - tAR tCSH tCRP tRCD tRSH tCPN CAS VIH - VIL - tCAS tASR tRAD tRAH tASC tRAL tCAH A0 - A8 VIH - VIL - Row Address SAM Start Address A0 - A8 : TAP tWSR tRWH WB/WE VIH - VIL - tTRP tTLS tTLH tTP DT/OE VIH - VIL - tASD tFSR tRFH DSF VIH - VIL - tOFF tCSD W1/IO1 W4/IO4 VOH - VOL - tRSD tTSD tSCC tSRS tSCP tSC tSCP SC VIH - VIL - Inhibit Rising Transient tSC tSDS tSDH tSZS IN VIH - VIL - Valid Data-in SIO1 SIO4 tTQD tSCA tSOH OUT VOH - VOL - tCQD Valid Data-out tRQD QSF VOH - VOL - TAP MSB (A8) Note: SE = VIL "H" or "L"
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,, , ,,
Semiconductor MSM514262 Real Time Read Transfer Cycle
tRC tRAS tRP RAS VIH - VIL - tAR tCSH tCRP tRCD VIH - CAS VIL - tRSH tCAS tCPN tRAD tRAL tASR tRAH tASC tCAH VIH - A0 - A8 VIL - Row Address tRWH SAM Start Address A0 - A8: TAP tATH tWSR WB/WE VIH - VIL - tCTH tTRP tTLS tRTH tTP VIH - DT/OE V IL - tFSR tRFH VIH - DSF VIL - tOFF W1/IO1 - VOH - W4/IO4 VOL - tSCC tSC tSCP tTSL tTSD VIH - SC VIL - IN VIH - VIL - Open SIO1 SIO4 tSCA tSCA tSOH tTQD tSOH VOH - OUT V OL - Valid Data-out Valid Data-out Valid Data-out Valid Data-out Valid Data-out Previous Row Data New Row Data VOH - QSF V OL - TAP MSB (A8) Note: SE = VIL "H" or "L"
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Semiconductor Split Read Transfer Cycle
tRC tRAS RAS VIH - VIL - tCRP CAS VIH - VIL - tRCD tAR tCSH tRSH tCAS
MSM514262
tRP
tCPN
, ,, ,
tRAD tRAL tASR tRAH tASC tCAH A0 - A8 VIH - VIL - Row Address tWSR tRWH SAM Start Address (n) A0 - A7: TAP WB/WE VIH - VIL - DT/OE VIH - VIL - tTLS tTLH tSTS tRFH tSTH DSF VIH - VIL - tFSR 511 (255) n n+1 (n+256) (n+257) n+2 (n+258)
...............
253 (509)
254 (510)
255 (511)
n+256 (n)
SC
VIH - VIL -
SIO1 SIO4
VOH - VOL -
510 (254)
511 (255)
n (n+256)
n+1 (n+257)
n+2 (n+258)
...............
253 (509)
254 (510)
255 (511)
tSQD
tSQD
QSF
VOH - VOL -
Lower SAM 0 - 255
Upper SAM 256 - 511
Note: SE = VIL
"H" or "L"
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,
Semiconductor MSM514262 Pseudo Write Transfer Cycle
tRC tRAS tRP RAS VIH - VIL - tAR tCSH tCRP tRCD CAS VIH - VIL - tRSH tCAS tCPN tRAD tASR tRAH tASC tRAL tCAH A0 - A8 VIH - VIL - Row Address SAM Start Address A0 - A8: TAP tWSR tRWH WB/WE VIH - VIL - VIH - VIL - VIH - VIL - VOH - VOL - tTLS tTLH DT/OE tFSR tRFH DSF tOFF W1/IO1 W4/IO4 Open tSRD tSCC tSRS tSCP tSC tSCP SC VIH - VIL - Inhibit Rising Transient tSC tESR tREH tSWS SE VIH - VIL - tSDD tSDZ tSDS tSDH IN VIH - VIL - tSEZ SIO1 SIO4 tSCA Valid Data-in OUT VOH - VOL - Valid Data-out tSOH Valid Data-out Open tCQD tRQD QSF VOH - VOL - TAP MSB (A8) Serial Output Data Serial Input Data "H" or "L"
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,
Semiconductor Write Transfer Cycle MSM514262
tRC
tRAS
tRP
RAS
VIH - VIL -
tAR
tCSH
tCRP
tRCD
CAS
VIH - VIL -
tRSH tCAS
tCPN
tRAD
tASR
tRAH
tASC
tRAL tCAH
A0 - A8
VIH - VIL -
Row Address
SAM Start Address A0 - A8: TAP
tWSR
tRWH
WB/WE
VIH - VIL -
tTLS
tTLH
DT/OE
VIH - VIL - VIH - VIL -
tFSR
tRFH
DSF
tOFF
tMS tMH
W1/IO1 W4/IO4
VOH - VOL -
WM1 Data
Open
tSRD
tSCC
tSRS
tSCP
tSC
tSCP
SC
VIH - VIL -
Inhibit Rising Transient
tSC
tESR
tREH
tSWS
SE
VIH - VIL -
tSDS
tSDH
tCQD
tSDS
tSDH
IN
VIH - VIL -
Valid Data-in
Valid Data-in
Valid Data-in
SIO1SIO4
tRQD
OUT
VOH - VOL -
Open
QSF
VOH - VOL -
TAP MSB (A8)
Previous Row Data
WM1 data: 0: Transfer Disable 1: Transfer Enable
New Row Data
"H" or "L"
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Semiconductor Split Write Transfer Cycle
tRC
MSM514262
tRAS RAS VIH - VIL - tCRP CAS VIH - VIL -
tRAD
tRP
tAR tCSH tRCD tRSH tCAS tRAL tCPN
,,,
tASR tRAH tASC tCAH A0 - A8 VIH - VIL - Row Address tWSR tRWH SAM Start Address (n) A0 - A7: TAP WB/WE VIH - VIL - tTLS tTLH DT/OE VIH - VIL - tSTS tRFH tSTH DSF VIH - VIL - tFSR tOFF tMS tMH W1/IO1 W4/IO4 VOH - VOL - WM1 Data Open 511 (255) n (n+256) n+1 (n+257) n+2 (n+258)
...............
253 (509)
254 (510)
255 (511)
n+256 (n)
SC
VIH - VIL -
SIO1 SIO4
VOH - 511 V0L - (255)
n (n+256)
n+1 (n+257)
n+2 (n+258)
...............
253 (509)
254 (510)
255 (511) tSQD
n+256 (n)
tSQD QSF VOH - VOL - Lower SAM 0 - 255 Upper SAM 256 - 511 Note: SE = VIL
"H" or "L"
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Serial Read Cycle (SE = VIL)
RAS VIH - VIL - tTHS tTHH DT/OE VIH - VIL - tSCC tSCC tSCC tSCC tSCC tSC tSC tSC tSC tSC SC VIH - VIL - tSCP tSCA tSCP tSCA tSCP tSCA tSCP tSCA tSCP tSCA tSCP tSOH tSOH tSOH tSOH tSOH SIO1 SIO4 VOH - VOL - Valid Data-out Valid Data-out Valid Data-out Valid Data-out Valid Data-out Valid Data-out Note: SE = VIL "H" or "L"
Semiconductor
MSM514262
Serial Read Cycle (SE Controlled Outputs)
RAS VIH - VIL -
tTHS
tTHH
DT/OE
VIH - VIL -
tSCC
tSCC
tSCC
tSCC
tSCC
tSC
tSC
tSC
tSC
tSC
SC
VIH - VIL -
tSCP
tSCP
tSEP
tSCP
tSCP
tSCP
tSCP
SE
VIH - VIL -
tSZE
IN
VIH - VIL -
SIO1 SIO4
tSCA
tSEA
tSOH
tSEZ
tSCA
tSCA tSOH
tSCA
tSOH
OUT
VOH - VOL -
Valid Data-out
Valid Data-out
Open
Valid Data-out
Valid Data-out
Valid Data-out
"H" or "L"
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Serial Write Cycle (SE = VIL)
RAS VIH - VIL - tTHS tTHH DT/OE VIH - VIL - tSCC tSCC tSCC tSCC tSCC tSC tSC tSC tSC tSC SC VIH - VIL - tSDH tSDH tSDH tSDH tSDH tSCP tSCP tSCP tSCP tSCP tSCP tSDS tSDS tSDS tSDS tSDS SIO1 SIO4 VIH - VIL - Valid Data-in Valid Data-in Valid Data-in Valid Data-in Valid Data-in Note: SE = VIL "H" or "L"
Semiconductor
MSM514262
Serial Write Cycle (SE Controlled Inputs)
RAS VIH - VIL -
tTHS
tTHH
DT/OE
VIH - VIL -
tSCC
tSCC
tSCC
tSCC
tSCC
tSC
tSC
tSC
tSC
tSC
SC
VIH - VIL -
tSCP
tSCP
tSCP
tSCP
tSCP
tSCP
tSWS
tSWIH tSEP
SE
VIH - VIL - VIH - VIL -
tSWH
tSWS tSWH tSE tSDH
tSWIH tSEP
tSWS tSWH
tSDS
tSE tSDH
tSWIS
tSWIS
tSDS
tSDS
tSE tSDH
IN
Valid Data-in
Valid Data-in
Valid Data-in
SIO1 SIO4
OUT
VOH - VOL -
Open
"H" or "L"
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Semiconductor
MSM514262
PIN FUNCTION
Address Input : A0 - A8 The 18 address bits decode an 8-bit location out of the 262,144 locations in the MSM514262 memory array. The address bits are multiplexed to 9 address input pins (A0 - A8) as standard DRAM. 9 row address bits are latched at the falling edge of RAS. The following 9 column address bits are latched at the falling edge of CAS. Row Address Strobe : RAS RAS is a basic RAM control signal. The RAM port is in standby mode when the RAS level is "high". As the standard DRAM's RAS signal function, RAS is control input that latches the row address bits and a random access cycle begins at the falling edge of RAS. In addition to the conventional RAS signal function, the level of the input signals, CAS, DT/OE, WB/WE, DSF and SE at the falling edge of RAS, determines the MSM514262 operation modes. Column Address Strobe : CAS As the standard DRAM's CAS signal function, CAS is the control input signal that latches the column address input and the state of the special function input DSF to select, in conjunction with the RAS control, either read/write operations or the special block write feature on the RAM port when the DSF is held "low" at the falling edge of RAS. CAS also acts as a RAM port output enable signal. Data Transfer/Output Enable : DT/OE DT/OE is also a control input signal having multiple functions. As the standard DRAM's OE signal function, DT/OE is used as an output enable control when DT/OE is "high" at the falling edge of RAS. In addition to the conventional OE signal function, a data transfer operation is started between the RAM port and the SAM port when DT/OE is "low" at the falling edge of RAS. Write-per-Bit/Write Enable : WB/WE WB/WE is a control input signal having multiple functions. As the standard DRAM's WE signal function, it is used to write data into the memory on the RAM port when WB/WE is "high" at the falling edge of RAS. In addition to the conventional WE signal function, the WB/WE determines the write-per-bit function when WB/WE is "low" at the falling edge of RAS, during RAM port operations. The WB/WE also determines the direction of data transfer between the RAM and SAM. When WB/WE is "high" at the falling edge of RAS, the data is transferred from RAM to SAM (read transfer). When WB/WE is "low" at the falling edge of RAS, the data is transferred SAM to RAM (write transfer).
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Semiconductor Write Mask Data/Data Input and Output : W1/IO1 - W4/IO4
MSM514262
W1/IO1 - W4/IO4 have the functions of both Input/Output and a control input signal. As the standard DRAM's I/O pins, input data on the W1/IO1 - W4/IO4 are written into the RAM port during the write cycle. The input data is latched at the falling edge of either CAS or WB/WE, whichever occurs later. The RAM data out buffers, which will output read data from the W1/ IO1 - W4/IO4 pins, becomes low impedance state after the specified access times from RAS, CAS, DT/OE and column address are satisfied and the output data will remain valid as long as CAS and DT/OE are kept "low". The outputs will return to the high impedance state at the rising edge of either CAS or DT/OE, whichever occurs earlier. In addition to the conventional I/O function, the W1/IO1 - W4/IO4 have the function to set the mask data, which select mask input pins out of four input pins, W1/IO1 - W4/IO4, at the falling edge of RAS. Data is written to the DRAM on data lines where the Write-mask data is a logic "1". The write-mask data is valid for only one cycle. Serial Clock : SC SC is a main serial cycle control input signal. All operations of SAM port are synchronized with the serial clock SC. Data is shifted in or out of the SAM registers at the rising edge of SC. In a serial read, the output data becomes valid on the SIO pins after the maximum specified serial access time tSCA from the rising edge of SC. The SC also increments the 9 bits serial pointer which is used to select the SAM address. The pointer address is incremented in a wrap-around mode to select sequential locations after the setting location which is determined by the column address in the read transfer cycle. When the pointer reaches the most significant address location (decimal 511), the next SC clock will place it at the least significant address location (decimal 0). The SC must be held data constant VIH or VIL level during read/pseudo write/write-transfer operations and should not be clocked while the SAM port is in the standby mode to prevent the SAM pointer from being incremented. Serial Enable : SE The SE is a serial access enable control and serial read/write control signal. In a serial read cycle, SE is used as an output control. In a serial write cycle, SE is used as write enable control. When SE is "high", serial access is disable, however, the serial address pointer location is still incremented when SC is clocked even when SE is "high". Special Function Input : DSF The DSF is latched at the falling edge of RAS and CAS and allows for the selection of several RAM port and transfer operating modes. In addition to the conventional multiport DRAM, the special function consisting of flash write, block write, load/read resister and read/write transfer can be invoked.
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Semiconductor Special Function Output : QSF
MSM514262
QSF is an output signal which, during split resister mode, indicates which half of the split SAM is being accessed. QSF "low" indicates that the lower split SAM (0 - 255) is being accessed. QSF "high" indicates that the upper SAM (256 - 511) is being accessed. QSF is monitored so that after it toggles and after allowing for a delay of tSTS, split read/write transfer operation can be performed on the non-active SAM. Serial Input/Output : SIO1 - SIO4 Serial input/output mode is determined by the most recent read, write or pseudo write transfer cycle. When a read transfer cycle is performed, the SAM port is in the output mode. When a write or pseudo write transfer cycle is performed, the SAM port is switched from output mode to input mode.
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Semiconductor
MSM514262
OPERATION MODES
Table-1 shows the function truth table for a listing of all available RAM ports and transfer operation of MSM514262. The RAM port and data transfer operations are determined by the state of CAS, DT/OE, WB/ WE, SE and DSF at the falling edge of RAS and by the level of DSF at the falling edge of CAS. Table-1. Function Truth Table
RASO W/IO CASO ADDRESS Write Register CAS DT/OE WB/WE DSF SE DSF RASO CASO RASO CASO CAS/WEO Mask WM Color 0 1 1 1 1 1 1 1 1 1 1 1 * 0 0 0 0 0 1 1 1 1 1 1 * 0 0 0 1 1 0 0 0 1 1 1 * 0 0 1 0 1 0 0 1 0 0 1 * 0 1 * * * * * * * * * -- * -- * -- * * -- * * -- Column Select -- -- Column Select -- -- * * * * * Din -- * Din -- Color -- WM1 -- WM1 -- -- WM1 WM1 WM1 -- -- -- -- Load Use -- Load Use -- -- Load Use Load Use Load Use -- -- -- -- -- -- -- -- -- -- Use Use -- Use Function C.B.R Refresh Masked Write Transfer Pseudo Write Transfer Split Write Transfer Read Transfer Split Read Transfer Write per Bit Masked Block Write Masked Flash Write Read Write Block Write
* Row TAP WM1 * Row TAP *
* Row TAP WM1 * Row TAP * Row TAP * *
0 Row Column WM1 1 Row * Row Column A2c-8c *
WM1
WM1
0 Row Column * 1 Row * Row Column A2c-8c * * *
Load Load Color Register
If the DSF is 'high" at the falling edge of RAS, special functions such as split transfer, flash write, and load/read color register can be invoked. If the DSF is "low" at the falling edge of RAS and "high" at the falling edge of CAS, the block write feature can be invoked. If the DSF is "low" at the falling edge of RAS and CAS, only the conventional multiport DRAM operating feature can be invoked.
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Semiconductor
MSM514262
RAM PORT OPERATION
Fast Page Mode Fast page mode allows data to be transferred into or out of multiple column locations of the same row by performing multiple CAS cycle during a signal active for a period up to 100m seconds. For the initial fast page mode access, the output data is valid after the specified access times from RAS, CAS, column address and DT/OE. For all subsequent fast page mode read operations, the output data is valid after the specified access times from CAS, column address and DT/OE. When the write-per bit function is enable, the mask data latched at the falling edge of RAS is maintained throughout the fast page mode write or read or read modify write cycle. RAS Only Refresh The data in the DRAM requires periodic refreshing to prevent data loss. Refreshing is accomplished by performing a memory cycle at each of the 512 rows in the DRAM array within the specified 8ms refresh period. Although any normal memory cycle will perform the refresh operation, this function is most easily accomplished with "RAS-only" cycle. CAS before RAS Refresh The MSM514262 also offers an internal refresh function. When CAS is held "low" for a specified period (tCSR) before RAS goes "low", an internal refresh address counter and on-chip refresh control clock generators are enable refresh operation take place. When the refresh operation is completed, the internal refresh address counter is automatically incremented in preparation for the next CAS before RAS cycle. For successive CAS before RAS refresh cycle, CAS can remain "low" while cycling RAS. Hidden Refresh A hidden refresh is a CAS before RAS refresh performed by holding CAS "low" from a previous read cycle. This allows for the output data from the previous memory cycle to remain valid while performing a refresh. The internal refresh address counter provides the address and the refresh is accomplished by cycling RAS after the specified RAS precharge period. Write-per-Bit Function The write per bit selectively controls the internal write enable circuits of the RAM port. Write per bit is enabled when WB/WE held "low at the falling edge of RAS in a random write operation. Also, at the falling edge of RAS, the mask data on the Wi/IOi pins are latched into a write mask register. The write mask data must be presented at the Wi/IOi pins at every falling edge of RAS. A "0" on any of the Wi/IOi pins will disable the corresponding write circuits and new data will not be written into the RAM. A "1" on any of Wi/IOi pins will enable the corresponding write circuits and new data will be written into the RAM.
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Semiconductor Load / Read Color Register
MSM514262
The MSM514262 is provided with an on-chip 4 bits color register for use during the flash write or block write operation. Each bit of the color register corresponds to one of the DRAM I/O blocks. The load color register cycle is initiated by holding CAS, WB/WE, DT/OE and DSF "high" at the falling edge of RAS. The data presented on the Wi/IOi lines is subsequently latched into the color register at the falling edge of either CAS or WB/WE whichever occurs later. The read color register cycle is activated by holding CAS, WB/WE, DT/OE and DSF "high" at the falling edge of RAS and by holding WB/WE "high" at the falling edge of CAS and throughout the remainder of the cycle. The data in the color register becomes valid on the Wi/ IOi lines after the specified access times from RAS and DT/OE are satisfied. During the load/read color register cycle, the memory cells on the row address latched at the falling edge of RAS are refreshed. Flash Write Flash write allows for the data in the color register to be written into all the memory locations of a selected row. Each bit of the color register corresponds to the DRAM I/O blocks and the flash write operation can be selectively controlled on an I/O basis in the same manner as the write per bit operation. A flash write cycle is performed by holding CAS "high" WB/WE "low" and DSF "high" at the falling edge of RAS. The mask data must also be provided on the Wi/IOi lines at the falling edge of RAS in order to enable the flash write operation for selected I/O blocks. Block Write Block write allows for the data in the color register to be written into 4 consecutive column address locations starting from a selected row. The block write operation can be selectively controlled on an I/O basis and a column mask capability is also available. Block write cycle is performed by holding CAS, DT/OE "high" and DSF "low" at the falling edge of RAS and by holding DSF "high" at the falling edge of CAS. The state of the WB/WE input at the falling edge of RAS determines whether or not the I/O data mask is enabled (WB/ WE must be "low" to enable the I/O data mask or "high" to disable mask). At the falling edge of RAS, a valid row address and I/O mask data are also specified. At the falling edge of CAS, the starting column address location and column address data mast be provided. During a block write cycle, the 2 least significant column address locations (A0C, A1C) are internally controlled and only the 7 most significant column addresses (A2C - A8C) are latched at the falling edge of CAS.
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Semiconductor
MSM514262
SAM PORT OPERATION
Single Register Mode High speed serial read or write operation can be reformed through the SAM port independent of the RAM port operation, except during read/write transfer cycles. The preceding transfer operation determines the direction of data flow through the SAM port. If the preceding transfer is a read transfer, the SAM port is in the output mode. If the preceding transfer is write or pseudo write transfer, the SAM port is in the input mode. The pseudo write transfer only switches the SAM port from output mode into mode (Data is not transferred from SAM port to RAM port). Serial data can be read out of the SAM after a read transfer has been performed. The data is shifted out to the SAM starting at any of the 512 bits locations. The TAP location corresponds to the column address selected at the falling edge of CAS during the read or write transfer cycle. The SAM registers are configured as circular data register. The data is shifted out sequentially starting from the selected TAP location to the most significant bit (511) and then wraps around to the least significant bit (0). Split Register Mode In split register mode, data can be shifted into or out of one half of the SAM while a split read or split write transfer is being performed on the other half of the SAM. Conventional (non split) read, write, or pseudo write transfer cycle must precede any split read or split write transfers. The split read and write transfers will not change the SAM port mode set by preceding conventional transfer operation. In the split register mode, serial data can be shifted in or out of the split SAM registers starting from any at the 256 TAP locations, excluding the last address of each split SAM, data is shifted in or out sequentially starting from the selected TAP location to the most significant bit (255 or 511) of the first split SAM and, then the SAM pointer moves to the TAP location selected for the second split SAM to shift data in or out sequentially starting from this TAP location to the most significant bit (511 or 255) and finally wraps around to the least significant bit.
TAP TAP
0
1
2
255
256 257
511
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Semiconductor
MSM514262
DATA TRANSFER OPERATION
The MSM514262 features two types of bidirectional data transfer capability between RAM and SAM, as shown in Figure 1 below. 1) Conventional (non split) transfer : 512 words by 4 bits of data can be loaded from RAM to SAM (Read transfer) or from SAM to RAM (Write transfer). 2) Split transfer : 256 words by 4 bits of data can be loaded from the lower/upper half of the RAM to the lower/upper half of the SAM (Split read transfer) or from the lower/upper half of SAM to the lower/upper half of RAM (Split write transfer). The conventional transfer and split transfer modes are controlled by the DSF input signal.
512 512 4 Memory Array
512 256 4 Memory Array
512 256 4 Memory Array
512 4 1) Conventional Transfer Figure 1.
256 4
256 4
2) Split Transfer
The MSM514262 supports five types of transfer operation : Read transfer , Split read transfer, Write transfer, Pseudo write transfer and Split write transfer as shown in truth table. Data transfer are invoked by holding the DT/OE signal "low" at the falling edge of RAS. The type of transfer operation is determined by the state of CAS, WB/WE, SE and DSF latched at the falling edge of RAS. During conventional transfer operations, the SAM port is switched from input to output mode (Read transfer) or output to input mode (Write/Pseudo write transfer) Whereas it remains unchanged during split transfer operation (Split read transfer or Split write transfer).
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Semiconductor Read Transfer Operation
MSM514262
Read transfer consists of loading a selected row of data from the RAM into the SAM register. A read transfer is invoked by holding CAS "high", DT/OE "low", WB/WE "high" and DSF "low" at the falling edge of RAS. The row address selected at the falling edge of RAS determines the RAM row to be transferred into the SAM. The transfer cycle is completed at the rising edge of DT/OE. When the transfer is completed, the SAM port is set into the output mode. In a read/ real time read transfer cycle, the transfer of a new row of data is completed at the rising edge of DT/OE and this data becomes valid on the SIO lines after the specified access time tSCA from the rising edge of the subsequent SC cycles. The start address of the serial pointer of the SAM is determined by the column address selected at the falling edge of CAS. In a read transfer cycle (which is preceded by a write transfer cycle), SC clock must be held at a constant VIL or VIH, after the SC high time has been satisfied. A rising edge of the SC clock must not occur until after the specified delay tTSD from the rising edge of DT/OE. In a real time read transfer cycle (which is preceded by another read transfer cycle), the previous row data appears on the SIO lines until the DT/OE signal goes "high" and the serial access time tSCA from the following serial clock is satisfied. This feature allows for the first bit of the new row of data to appear on the serial output as soon as the last bit of the previous row has been strobed without any timing loss. To make this continuous data flow possible, the rising edge of DT/OE must be synchronized with RAS, CAS and the subsequent rising edge of SC (tRTH, tCTH and tTSL/tTSD must be satisfied). Write Transfer Operation Write transfer cycle consists of loading the content of the SAM register into a selected row of the RAM. If the SAM data to be transferred must first be loaded through the SAM, a pseudo write transfer operation must precede the write transfer cycles. A write transfer is invoked by holding CAS "high", DT/OE "low", WB/WE "low", SE "low" at the falling edge of RAS. This write transfer is selectively controlled per RAM I/O block by setting the mask data on the Wi/IOi lines at the falling edge of RAS. The row address selected at the falling edge of RAS determines the RAM row address into which the data will be transferred. The column address selected at the falling edge of CAS determines the start address of the serial pointer of the SAM. After the write transfer is completed, the SIO lines are set in the input mode so that serial data synchronized with the SC clock can be loaded. When consecutive write transfer operation are performed, new data must not be written into the serial register until the RAS cycle of the preceding write transfer is completed. Consequently, the SC clock must be held at a constant VIL or VIH during the RAS cycle. A rising edge of the SC clock is only allowed after the specified delay tSRD from rising edge of the RAS, at which time a new row of data can be written in the serial register. Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other address of RAM by write transfer cycle, however, the address to write data must be the same as that of the read transfer cycle or the split read transfer cycle (row address AX8).
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Semiconductor Pseudo Write Transfer Operation
MSM514262
Pseudo write transfer cycle must be performed before loading data into the serial register after a read transfer operation has been excuted. The only purpose of a pseudo write transfer is to change the SAM port mode from output mode to input mode (A data transfer from SAM to RAM does not occur). After the serial register is loaded with new data, a write transfer cycle must be performed to transfer the data from SAM to RAM. A pseudo write transfer is invoked by holding CAS "high", DT/OE "low", WB/WE "low", SE "high" and DSF "low" at the falling edge of RAS. The timing conditions are the same as the one for the write transfer cycle except for the state of SE at the falling edge of RAS. Split Data Transfer and QSF The MSM514262 features a bidirectional split data transfer capability between the RAM and SAM. During split data transfer operation, the serial register is split into two halves which can be controlled independently. Split read or write transfer operation can be performed to or from one half of the serial register while serial data can be shifted into or out of the other half of the register. The most significant column address location (A8C) is controlled internally to determine which half of the serial register will be reloaded from the RAM. QSF is an output in which indicates which half of the serial resister is in an active state. QSF changes state when the last SC clock is applied to active split SAM. Split Read Transfer Operation Split read transfer consists of loading 256 words by 4 bits of data from a selected row of the split RAM into the corresponding non-active split SAM register. Serial data can be shifted out from of the other half of the split SAM register simultaneously. During split read transfer operation, the RAM port input clocks do not have to be synchronized with the serial clock SC, thus eliminating timing restrictions as in the case of real time read transfers. A split read transfer can be performed after a delay of tSTS, from the change of state of the QSF output, is satisfied. Conventional (non-split) read transfer operation must precede split read transfer cycles. Split Write Transfer Operation Split write transfer consists of loading 256 words by 4 bits of data from the non-active split SAM register into a selected row of the corresponding split RAM. Serial data can be shifted into the other half of the split SAM register simultaneously. During split write transfer operation, the RAM port input clocks do not have to be synchronized with the serial clock SC, thus allowing for real time transfer. A split write transfer can be performed after a delay of tSTS, from the change of state of the QSF output, is satisfied. A pseudo write transfer operation must precede split write transfer. The purpose of the pseudo write transfer operation is to switch the SAM port from output mode to input mode and to set the initial TAP location prior to split write transfer operations. Transfer Operation Without CAS During all transfer cycles, the CAS clock must be cycled, so that the column addresses are latched at the falling edge of CAS, to set the SAM TAP location.
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Semiconductor TAP Location in Split Transfer
MSM514262
In a split transfer operation, column address A0C through A7C must be latched at the falling edge of CAS in order to set the TAP location in one of the split SAM registers. During a split transfer, column address A8C is controlled internally and therefore it is ignored internally at the falling edge of CAS. During a split transfer, it is not permissible to set the last address location (A0C - A7C = FF), in either the lower SAM or the Upper SAM, as the TAP location. 2) In the case of multiple split transfers preformed into the same split SAM register, the TAP location specified during the last split transfer, before QSF toggles, will prevail.
1)
POWER-UP
Power must be applied to the RAS and DT/OE input signals to pull them "high" before or at the same time as the VCC supply is turned on. After power-up, a pause of 200 ms minimum is required with RAS and DT/OE held "high". After the pause, a minimum of 8 RAS and SC dummy cycles must be performed to stabilize the internal circuitry, before valid read, write or transfer operations can begin. During the initialization period, the DT/OE signal must be held "high". If the internal refresh counter is used, a minimum 8 CAS before RAS cycles are required instead of 8 RAS cycles.
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Semiconductor
MSM514262
PACKAGE DIMENSIONS
(Unit : mm)
ZIP28-P-400-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.85 TYP.
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Semiconductor
MSM514262
(Unit : mm)
SOJ28-P-400-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.30 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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